CN219288081U - Superconducting circuit and quantum chip - Google Patents

Abstract

The application discloses a superconducting circuit and a quantum chip, and belongs to the field of quantum chip preparation. The coupling units formed by the superconducting wires by the qubits are expanded by means of mutually common bits and thus have a two-dimensional network structure. The superconducting circuit constructed in the method can layout more bits in the limited space of the quantum chip, thereby facilitating the quantum chip to integrate more bits so as to improve the quantum computing performance.

Description

Superconducting circuit and quantum chip

Technical Field

The application belongs to the field of quantum chip preparation, and particularly relates to a testing method and a testing structure.

Background

In quantum chips, in order to obtain better computational performance, it is common to pursue a greater number of qubits. And are typically chosen to be arranged in a one-dimensional chain structure with coupling between two adjacent qubits. The scheme can conveniently layout the quantum bits, and the control circuit and the reading circuit corresponding to the quantum bits can be conveniently arranged. However, the quantum bit expansion manner can lead to rapid increase of the size of the quantum chip, and especially the problem is particularly remarkable when the number of the equivalent quantum bits is greatly increased.

Disclosure of Invention

In view of this, the present application discloses a superconducting circuit and a quantum chip that can be used to increase the integration level of the quantum chip, thereby contributing to the computational effort for increasing the quantum chip. Different from the one-dimensional ground chain layout bit, the bit is expanded in a two-dimensional mode to construct a multi-superconducting circuit, so that the limited space on the chip substrate can be effectively utilized, and more quantum bits are integrated.

The scheme exemplified by the application is implemented as follows.

In a first aspect, examples of the present application provide a superconducting circuit having a plurality of qubits.

The superconducting routing coupling unit is constructed by expanding a given connection mode into a two-dimensional network; the given connection mode is to connect one coupling unit as a starting point with other adjacent coupling units for expansion, and the other coupling units adjacent to the one coupling unit are connected with each other in a mode of sharing two qubits; the coupling unit is formed by sequentially connecting a plurality of quantum bits in a ring shape to form a closed ring, and a circuit configured to read and/or operate the quantum bits is arranged in the ring-shaped area.

By two-dimensionally arranging the qubits, a superconducting circuit having a plurality of bits is formed by extension. The superconducting circuit has a two-dimensional network structure, and therefore, higher bit integration can be achieved, so that higher space utilization can be realized on the substrate of the chip. And the multi-bit structure is constructed in the mode, so that corresponding reading circuits and operation circuits can be conveniently configured for each quantum bit, and the manufacturing difficulty of quantum chips with a larger number of quantum bits can be reduced. That is, for the same number of multi-bit systems, the read lines and the operating lines required for the superconducting circuits in the examples of the present application can be reduced to some extent, thereby reducing the difficulty in manufacturing and layout of these lines.

According to some examples of the present application, the coupling unit has a hexagonal structure and is configured with qubits at least at vertices of the hexagonal structure.

According to some examples of the present application, any one or more sides of the hexagonal structure are each independently configured with at least one qubit.

According to some examples of the present application, in the two common qubits, each qubit is located at a vertex of the hexagonal structure.

According to some examples of the present application, any one or more sides of the hexagonal structure are each independently configured with two couplers and one qubit located between the two couplers.

According to some examples of the present application, any adjacent two bits in the superconducting circuit are connected by a coupler.

According to some examples of the present application, the coupler is an adjustable coupler.

According to some examples of the present application, the qubit is a frequency tunable qubit.

In a second aspect, some examples of the present application provide a quantum chip comprising:

a first chip having a first substrate, a bit network and a main signal line disposed on the first substrate;

the bit network is formed by arranging a plurality of quantum bits in a honeycomb shape, and is provided with a plurality of hexagonal grids which define a first area;

the main signal line is arranged in the first area and is configured to be matched with the qubit to realize reading operation and/or control operation on the qubit;

a second chip flip-chip connected to the first chip, the second chip having a second substrate defining a second region opposite to the first region and a sub-signal line disposed in the second region;

wherein the primary signal line routes signals to the secondary signal line through an interconnect communication structure disposed between the first chip and the second chip.

According to some examples of the present application, the projection of the first chip is located within the second chip in a direction from the first chip to the second chip.

According to some examples of the present application, the second chip has a first region, and a second region, the second region being outside of and surrounding the first region;

the second chip is provided with a pad located in the second region, and the pad is communicatively connected to the sub signal line through a wiring.

The beneficial effects are that:

compared with the prior art, the application example provides a scheme for expanding the quantum bit number in the quantum chip. By implementing this embodiment, the pressure of the chip size increase caused by the integration of more qubits in the quantum chip can be alleviated to some extent. And such a qubit layout can also be used to fabricate quantum chips with a relatively smaller number of control lines.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below.

FIG. 1 is a schematic diagram of a structure of a qubit on a quantum chip according to the related art;

FIG. 2 is a schematic diagram of a structure in which the qubits shown in FIG. 1 are arranged linearly in one dimension;

fig. 3 is a schematic layout diagram of a qubit in a coupling unit having six qubits according to an embodiment of the present application;

fig. 4 is a schematic layout diagram of qubits in a coupling unit having four qubits according to an embodiment of the present application.

Reference numerals illustrate: 100-superconducting circuits; a 101-coupling unit; 100 a-superconducting circuits; 101 a-coupling unit.

Detailed Description

A quantum chip is a central processor in a quantum computing system that performs quantum computation. The quantum chip contains quantum bits as core units of the processor. Depending on the physical system employed to construct the superconducting qubit, the qubit may comprise superconducting quantum circuits, semiconductor quantum dots, ion traps, diamond vacancies, topology quanta, photons, etc. in physical implementation.

Superconducting quantum computing is the best solid quantum computing implementation method with the fastest development at present. Superconducting quantum bits are a two-level system which follows the laws of quantum mechanics; which may be in any superposition of 0 and 1. The energy level structure of the superconducting quantum circuit can be regulated and controlled by externally adding electromagnetic signals, and the design and the manufacture of the superconducting quantum circuit have higher controllability. Meanwhile, the superconducting quantum circuit has unmatched expandability of a plurality of quantum physical systems due to the existing mature integrated circuit process.

The quantum chip based on the superconducting quantum circuit comprises superconducting circuit components such as quantum bits, microwave resonant cavities and the like. Qubits are two-level systems that are constructed using capacitive and josephson junctions with nonlinear inductive properties. Through designing into different shapes, the states of electrical parameters such as capacitance, inductance and the like of different targets are realized.

The Transmon qubit is shaped like a "+" and consists of a cross-shaped capacitor and a superconducting quantum interference device (Superconducting Quantum Interference Device, SQUID) connected with one branch end of the capacitor. Wherein the superconducting quantum interference device comprises one or more josephson junctions. Whereas a josephson junction is a device comprising two electrodes and a thin insulating barrier separating the two electrodes. The materials of the two electrodes may exhibit superconducting properties at or below the critical temperature of the material.

In a quantum chip, there are a plurality of circuit structures of different functions around the qubit. These circuit structures include, but are not limited to: a drive control signal line (also called XY control line or pulse control signal line) for performing XY rotation operation on the qubits, a read resonant cavity, and a coupler for coupling connection between the qubits.

The Z-rotation operation of the qubit is performed by a control signal line in the vicinity of the superconducting quantum interference device, and is called a magnetic flux control signal line (also called a Z control signal line or a frequency control signal line). The magnetic flux regulating signal line is arranged near the superconducting quantum interference device and excites current, and is mutually coupled with the superconducting quantum interference device through magnetic flux.

It should be noted that, both the magnetic flux controlling signal line and the driving control line may be used to control the qubit, but the control manners of the two are basically different.

Wherein the signal transmitted by the magnetic flux modulating signal line will generate a magnetic field and be applied to the region of the superconducting quantum interference device. And accordingly, the magnetic flux passing through the region of the quantum interference device may cause a change in the critical current of the required. And a change in the critical current results in a change in the frequency of the tunable qubit. The control of the frequency of the quantum bit can be realized through the signal transmitted by the magnetic flux control signal line.

Wherein the drive control signal line applies a pulse to the qubit in the form of an electric field, the pulse causing a transition in the energy level of the qubit.

In order to enable those skilled in the art to understand the qubit, fig. 1 illustrates a schematic structure of the qubit arranged on the quantum chip in the related art.

Referring to fig. 1, the qubit uses a single capacitance to ground, for example, a cross-type parallel plate capacitor, and a superconducting quantum interference device having one end grounded and the other end connected to the capacitance.

In fig. 1, the cross-shaped capacitive plate Cq is surrounded by a ground plane (GND). A gap is provided between the cross-shaped capacitive plate Cq and the ground plane (GND), and one end of the superconducting quantum interference device is connected to (the end of one of the capacitive arms of) the cross-shaped capacitive plate Cq, and the other end of the superconducting quantum interference device is connected to the ground plane (GND).

The first end of the cross-shaped capacitive plate Cq is typically used for connecting a superconducting quantum interference device (squid) and the second end is used for coupling with a read resonant cavity (U-shaped region of the meander structure in fig. 1). A certain space needs to be reserved near the first end and the second end of the cross-shaped capacitive plate Cq for arranging microwave transmission lines such as a driving control signal line and a magnetic flux regulating signal line. A certain space needs to be reserved near the resonant cavity for arranging a read signal transmission line (not shown in fig. 1) coupled with the resonant cavity, and the other two ends of the cross-shaped capacitive plate Cq are used for coupling with adjacent qubits. The magnetic flux control signal line, the driving control signal line, the reading signal transmission line and other structures can adopt various proper microwave transmission line structures, and are not repeated here.

As an example, when performing quantum computation, the operations are implemented by:

the frequency of the qubit is first adjusted to the operating frequency (i.e., the initialization of the qubit) using the flux-control signal on the flux-control signal line (Z line).

And then a quantum state regulation signal is applied through a driving control signal line (xy line) to carry out quantum state regulation on the quantum bit in the initial state.

And then reading the quantum state of the regulated quantum bit by adopting the resonant cavity. As an alternative example, in particular, a read probe signal (e.g. a microwave signal with a frequency of 4-8 GHz) is applied/input on a read signal transmission line coupled to the resonant cavity. Then, a read feedback signal (a signal in response to a read probe signal) output via the read signal transmission line is analyzed to determine the quantum state in which the qubit is located.

It is worth noting that the quantum chip performs the quantum computation as follows:

a quantum program in the quantum computing task is compiled into a generated waveform command or the like, and is transmitted to the physical signal generating device.

The physical signal generating device generates a corresponding physical signal and transmits the physical signal to the quantum chip to correspondingly operate the corresponding quantum bit. Then, a quantum state read signal is applied to the corresponding qubit. And determining quantum state information of the quantum bit by using a read feedback signal fed back by the quantum bit based on the quantum state read signal. Then, the quantum computation result is parsed from the quantum state information.

To some extent, the number of qubits in a quantum chip determines its computational power. Thus, one important performance metric for a quantum computing system is the number of qubits it integrates. In order to integrate more qubits, for example, taking the quantum superconducting circuit shown in fig. 1 as an example, the manner of integrating a plurality of qubits is: the plurality of qubits are linearly arranged in one dimension. That is, the respective qubits are sequentially arranged one by one from left to right, and two adjacent qubits are coupled to each other by the left and right capacitance arms of the cross capacitance of each other to realize connection between the qubits. Fig. 2 discloses in a simplified manner a schematic structure of six qubits arranged linearly in one dimension.

However, the layout of the qubits in the manner of fig. 2 occupies a large space, so that the quantum chip is oversized and lacks higher convenience and flexibility in use; for example, a quantum chip that can be accommodated by a dilution refrigerator that provides a very low temperature operating environment for superconducting quantum chips may require redesign, structural modification, and the like. And a corresponding Z control line needs to be configured for each bit in order to adjust the qubit frequency, so that the manufacturing difficulty is great, and the coherence time is easily shortened due to the magnetic flux noise of the Z control line.

Based on this study, in the examples of the present application, the inventors propose a new multi-bit system. Which has a bit layout scheme different from the one-dimensional linear structure of fig. 2, exhibits a two-dimensional distributed structure as a whole, thereby enabling more efficient use of the space of the substrate of the chip. And the new wiring scheme can be researched by utilizing the layout mode, so that the influence of different layout modes on the performance, the manufacture and the like of the multi-bit quantum computing system is compared and inspected, and further, beneficial reference and practice can be provided for manufacturing the quantum computer with high performance and high stability.

In an example, the utility model of the present application proposes a new superconducting circuit. The superconducting circuit integrates a plurality of qubits. And unlike the one-dimensional distribution scheme in fig. 2, these qubits in the examples of the present application are distributed in two dimensions at the substrate.

In general, the new superconducting circuit is constructed by extending the coupling elements into a two-dimensional network in a given connection. The described given connection mode is extended by connecting one coupling unit with other adjacent coupling units as a starting point. And the other coupling units adjacent to the one coupling unit are connected to each other in such a manner as to share two qubits (for example, by capacitive coupling). The coupling unit is formed by sequentially connecting a plurality of quantum bits in a ring shape to form a closed ring, and any one or two of circuits configured to read and operate the quantum bits are arranged in the ring-shaped area. That is, the aforementioned circuit is surrounded by an annular arrangement of a plurality of qubits, and the plurality of qubits of these descriptions form a closed loop.

Although the foregoing mainly describes a superconducting quantum superconducting circuit as shown in fig. 1, the qubit in the examples of the present application may also take other structures. Thus, the qubits in examples of the present application may be, for example, transmon qubits, xmon qubits, gmon qubits, fluxonium qubits, and the like.

Fig. 3 is a schematic diagram of a qubit lattice layout of coupling cells in some examples of the present application. In the superconducting circuit 100 shown in fig. 3, 22 coupling units 101 are disclosed in total, and one is exemplarily indicated.

Wherein each coupling element has a hexagonal structure and each of the six vertices represents a qubit. The qubit may be a frequency tunable superconducting qubit with a Z control line. Alternatively, the qubit may also be a frequency-fixed superconducting qubit without a Z control line; the frequency of which can be adjusted in other ways, such as an adjustable coupler as mentioned later.

There is one circle inside each hexagon (thus 22 circles in total in fig. 3) representing the corresponding line of the coupling unit (for optionally controlling, reading qubits).

It is to be noted that the coupling units may take a triangular shape, a quadrangular shape (as shown in fig. 4, in which the superconducting circuit 100a having 20 coupling units 101a is described), or the like, in addition to the hexagonal structure as in fig. 3.

Further, in some other examples, in addition to configuring the qubits at vertices, one or more qubits may be optionally configured at any one or more sides thereof in the polygonal coupling element. For example, when the coupling unit is hexagonal, in some examples, at least one qubit may be selectively configured independently at any one or more sides of the hexagonal structure. That is, if not specifically stated, the bits on the vertices of the polygon and the bits on the edges of the polygon are described as being different. Thus, no intentional restriction of bits on edges is made when expressing bits on vertices; similarly, no intentional limitation of bits on vertices is made in expressing bits on edges.

In the example of fig. 3, for example, the qubit common to two adjacent coupling elements is located at the vertex of the hexagon. When the sides of the hexagon are configured with qubits, then the qubits shared by two adjacent coupling cells may also be located on the sides of the hexagon. It will be appreciated that in other examples, qubits common to two adjacent coupling elements may also be located at sides of a polygon.

In addition to configuring qubits in superconducting circuits, couplers may alternatively be configured. Thus, in some examples, any two adjacent bits in the superconducting circuit are connected by a coupler.

Taking the structure of fig. 3 as an example, any one or more sides of the hexagonal structure may be configured with two couplers and one qubit located between the two couplers, respectively, independently. Alternatively, any one or more sides of the polygon structure may be provided with a coupler independently. Thus, one coupler disposed on an edge is coupled to the qubits at the vertices at both ends of the edge, respectively.

In other words, one qubit may be chosen to be configured at each vertex of the hexagon. While a coupler may be disposed between two end points (vertices) of either edge. Thus, in a bit structure of a two-dimensional network, a qubit at one vertex can connect 3 (tunable) couplers, while one tunable coupler connects two bits. Thus, in these examples, it may be equivalent to one bit connecting 1.5 couplers, so that the pressure of a large portion of the adjustable coupler control lines may be reduced over a large scale expansion of bits. The above-mentioned coupler may be an adjustable coupler.

In the foregoing embodiment, the coupler is added at the edge, and in other cases, the coupler-bit-coupler structure may be added at the edge instead, and such a structure may bring about a reduction in the number of adjustable couplers as a whole. From this, the number of equivalent one-bit connected adjustable couplers can be calculated to be 1.25.

Further, in other examples, it is optional to continue adding more qubits to the edges of the hexagon, and it is only necessary to ensure that the tunable couplers are on both sides. Thus, an expression (expression 1) for calculating the number of adjustable couplers equivalent to the bit connection can be obtained.

Where N is the number of bits added to each edge and N is the number of equivalent one-bit connected adjustable couplers.

From this expression it can be seen that the greater the number of bits added at the edge, the greater the number of finally equivalent one-bit connected adjustable couplers, the final number of which will approach 1.

In the case of configuring the coupler, each qubit may be configured with an XY control line on which it operates, without a Z control line; correspondingly, the structure providing the function of the Z control line is realized by the adjustable coupler. I.e. the qubit in the superconducting circuit has its independent XY control line without having to configure it with an independent Z line. In this way, the adverse interference of magnetic flux noise generated by the Z control line on the phase decoherence time of the quantum bit can be reduced to a great extent.

In addition, in the superconducting circuit, the qubit may be frequency-tunable, and the frequency thereof may be realized by directly operating the SQUID in the qubit using the Z control line. However, and the tunable range of frequencies may not meet specific requirements based on current processes.

For example, current superconducting qubits are typically composed of capacitively shunted SQUIDs. Whereas SQUIDs are typically symmetric josephson junctions and can thus form a superconducting qubit with adjustable frequency. On this basis, the maximum frequency of the bits can be regulated by controlling the capacitance charge energy (Ec) and the josephson energy (Ej). The adjustable range of the bit frequency can be adjusted by controlling the degree of asymmetry of the josephson junctions in the SQUID. However, to the best of the inventors' knowledge, the current process has a significant limitation on making SQUIDs of higher asymmetry. For example, a qubit frequency tunable range of 100MHz requires a higher asymmetric SQUID, which can be very difficult to implement in a process.

Thus, in order to achieve a more technically convenient frequency tuning of the qubit, it is for example possible to construct the qubit as a fixed frequency (i.e. without a Z control line; this bit is for example constituted by a capacitor in parallel with a single josephson junction and with a separate XY control line), and correspondingly to achieve a tuning of the frequency of the fixed qubit by using an additionally configured tuning control structure.

The advantages of such a design are at least: the adjustable range of the frequency of the quantum bit is controllable, the Z control line is reduced, and accordingly magnetic flux noise caused by configuring an independent Z control line for the quantum bit can be reduced, and meanwhile, the method is easier to realize in technology.

Based on the superconducting circuit, the quantum chip can be constructed. Illustratively, the quantum chip includes a first chip and a second chip. The first chip and the second chip are stacked and flip-chip interconnection is achieved with each other by, for example, a flip-chip bonding technique.

The first chip is provided with a first substrate, a bit network and a main signal line, wherein the bit network and the main signal line are arranged on the first substrate. Accordingly, the bit network is formed by a plurality of (e.g., 4, 5, 6, etc.) qubits arranged in a honeycomb fashion, and accordingly the bit network has a plurality of hexagonal cells. Wherein the hexagonal grid defines a first region. I.e. the surface of the first substrate has a number of hexagonal first areas.

In response thereto, the main signal line is disposed in the first region and configured to match the qubit to enable a read operation and/or a control operation for the qubit. Corresponding to the function of the main signal line, it can be constructed as a read resonant cavity, XY control line.

The second chip has a second substrate and a sub signal line. The second substrate defines a second region opposite to the first region corresponding to the sub signal line. Accordingly, the sub signal line is disposed in the second region.

The primary signal lines route signals to the secondary signal lines through an interconnect communication structure (e.g., indium posts of metallic indium material, and optionally bond pads such as titanium nitride) disposed between the first chip and the second chip. Based on this, a signal source (e.g., an arbitrary waveform generator) that provides a control, read signal can be connected to the secondary signal line via appropriate wiring and cabling to transfer the signal to the primary signal line, and thus can perform a qubit operation. As an example, the sub signal line and the main signal line may be coplanar signal lines.

In view of convenience and workability in connection of the signal source and the sub signal lines, the layout of the sub signal lines may be selected to be controlled, for example, so that the ends thereof avoid the first chip. As an alternative, the projection of the first chip is located within the second chip in the direction of the first chip to the second chip. Corresponding to this, the first substrate is smaller than the second substrate. I.e. the first substrate and the second substrate are stacked, the edge of the first substrate is inside the edge of the second substrate.

It will thus be appreciated that the second substrate has an inner region and an outer region surrounding/encircling the inner region outside the inner region. Thus, the first substrate is in the interior region. Alternatively, in some examples, the inner region is described as a first region and the outer region is described as a second region. On this basis, the secondary signal line may be provided with pads (as described as pads) and is located in the second region of the second substrate. Accordingly, the pad can be communicatively connected to the sub signal line through the wiring.

In embodiments of the present application, the fabrication of superconducting circuits and quantum chips described may use a process that selectively combines one or more of the integrated circuits.

For example, one or more materials (thin films, film layers; may be one or more layers, and where multiple layers are provided, the materials for each layer may be independently selected) may optionally be deposited on the surface of the substrate/base during fabrication of the superconducting circuit (e.g., various coplanar conductor structures).

The foregoing materials are, for example, one or more of superconductors (e.g., aluminum, tantalum, etc.), dielectrics, metals. Depending on the materials selected, these materials may be processed by deposition processes such as chemical vapor deposition, physical vapor deposition (e.g., evaporation or sputtering), or epitaxial techniques, among other deposition processes.

In order to obtain circuits, components having various desired specific structures, the deposited films may optionally be subjected to subsequent processing, for example, which generally includes an operation that may be described as patterning. Thus, one or more materials may need to be removed from the film or substrate during the manufacturing process. And depending on the material to be removed, the removal process may include, but is not limited to, a wet etching technique, a dry etching technique, or a lift-off (lift-off) process. In order to tailor the form of the component obtained after removal of material, known lithographic techniques, the conventional process flows of which include, for example, substrate pretreatment, gumming, pre-baking, exposure, development, post-baking, etching, photoresist removal, etc., may be used to treat the material film layers forming the circuit elements described herein.

The embodiments described above by referring to the drawings are exemplary only and are not to be construed as limiting the present application. For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application clear, the foregoing descriptions of the embodiments of the present application are described in detail with reference to the accompanying drawings. However, as will be appreciated by those of ordinary skill in the art, in the various embodiments of the present application, numerous technical details have been set forth in order to provide a better understanding of the present application. However, the technical solutions claimed in the present application can be implemented without these technical details and with various changes and modifications based on the following embodiments. The division of the examples is for convenience of description, and should not be construed as limiting the specific implementation manner of the present application, and the embodiments may be mutually combined and referred to without contradiction.

It should be noted that the terms "first," "second," and the like in the description and claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that embodiments of the present application described herein may be implemented in sequences other than those illustrated or otherwise described herein.

Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

The foregoing detailed description of the construction, features and advantages of the present application will be presented in terms of embodiments illustrated in the drawings, wherein the foregoing description is merely illustrative of preferred embodiments of the application, and the scope of the application is not limited to the embodiments illustrated in the drawings.

Claims (11)

1. A superconducting circuit having a plurality of qubits, wherein the superconducting routing coupling unit is constructed by expanding a given connection to a two-dimensional network;

wherein the given connection scheme is extended by connecting one coupling unit as a starting point with other adjacent coupling units, and the other coupling units adjacent to the one coupling unit are connected with each other in a manner of sharing two qubits;

the coupling unit is formed by sequentially connecting a plurality of the plurality of qubits in a ring shape to form a closed ring, and a circuit configured to read and/or operate the qubits is arranged in the ring-shaped area.

2. The superconducting circuit of claim 1, wherein the coupling unit has a hexagonal structure and the qubits are arranged at least at vertices of the hexagonal structure.

3. The superconducting circuit of claim 2, wherein any one or more sides of the hexagonal structure are each independently configured with at least one qubit.

4. A superconducting circuit according to claim 2 or claim 3, wherein in the shared two qubits, each qubit is located at a vertex of the hexagonal structure.

5. The superconducting circuit of claim 2 wherein any one or more sides of the hexagonal structure are each independently configured with two couplers and one qubit located between the two couplers.

6. The superconducting circuit of claim 1, wherein any two adjacent bits in the superconducting circuit are connected by a coupler.

7. The superconducting circuit according to claim 5 or 6, wherein the coupler is an adjustable coupler.

8. The superconducting circuit of claim 1, wherein the qubit is a frequency tunable qubit.

9. A quantum chip, comprising:

a first chip having a first substrate, a bit network and a main signal line disposed on the first substrate;

the bit network is formed by arranging a plurality of quantum bits in a honeycomb shape, and is provided with a plurality of hexagonal grids which define a first area;

the main signal line is arranged in the first area and is configured to be matched with the qubit to realize reading operation and/or control operation on the qubit;

a second chip flip-chip connected to the first chip, the second chip having a second substrate defining a second region facing the first region, and a sub-signal line disposed in the second region;

wherein the primary signal line routes signals to the secondary signal line through an interconnect communication structure disposed between the first chip and the second chip.

10. The quantum chip of claim 9, wherein the projection of the first chip is located within the second chip in a direction from the first chip to the second chip.

11. The quantum chip of claim 10, wherein the second chip has a first region and a second region, the second region being outside of and surrounding the first region;

the second chip is provided with a pad located in the second region, and the pad is communicatively connected to the sub signal line through a wiring.

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