CN217588898U - Packaging structure of semiconductor device and electronic equipment - Google Patents

Abstract

The application discloses semiconductor device's packaging structure and electronic equipment, packaging structure includes: a housing having a receiving cavity; the accommodating cavity is provided with an opening; a plurality of first electrode pins are fixed on the side wall of the shell, one end of each first electrode pin is positioned in the containing cavity, and the other end of each first electrode pin penetrates through the side wall of the shell and is positioned outside the containing cavity; the base plate is fixed at the bottom of the accommodating cavity; a plurality of semiconductor devices fixed on the substrate; the semiconductor device is connected with the substrate and is connected with the first electrode pin through the substrate; a sealing cap for sealing the opening of the receiving cavity. According to the technical scheme, the semiconductor devices are packaged simultaneously through the same shell, and compared with a mode that the semiconductor devices are packaged in a plastic package mode respectively and independently, the size of a circuit system is reduced, and the miniaturization design of equipment is facilitated.

Description

Packaging structure of semiconductor device and electronic equipment

Technical Field

The present disclosure relates to the field of semiconductor device package structures, and more particularly, to a semiconductor device package structure and an electronic device.

Background

With the continuous progress of science and technology, more and more electronic devices are widely applied to daily life and work of people, bring great convenience to the daily life and work of people, and become an indispensable important tool for people at present.

The main components of electronic equipment that perform various functions are integrated circuits, and semiconductor devices are important electronic components in the integrated circuits. In order to protect the semiconductor device and facilitate circuit interconnection of the semiconductor device, the semiconductor device generally needs to be protected by a packaging process to form a package structure.

In the existing packaging technology, a single semiconductor device is generally subjected to plastic packaging to form a packaging structure. For an interconnection circuit requiring a plurality of semiconductor devices, the independent packaging mode of each semiconductor device leads to a larger circuit system volume and is inconvenient for the miniaturization design of equipment.

SUMMERY OF THE UTILITY MODEL

In view of the above, the present application provides a package structure of a semiconductor device and an electronic apparatus, and the scheme is as follows:

a package structure of a semiconductor device, comprising:

a housing having a receiving cavity; the accommodating cavity is provided with an opening; a plurality of first electrode pins are fixed on the side wall of the shell, one end of each first electrode pin is positioned in the containing cavity, and the other end of each first electrode pin penetrates through the side wall of the shell and is positioned outside the containing cavity;

the base plate is fixed at the bottom of the accommodating cavity;

a plurality of semiconductor devices fixed on the substrate; the semiconductor device is connected with the substrate and is connected with the first electrode pin through the substrate;

a sealing cap for sealing the opening of the receiving cavity.

Preferably, in the above package structure, a side surface of the housing facing away from the accommodating cavity has a flow channel for guiding a cooling liquid.

Preferably, in the above package structure, the substrate is a double-sided copper-clad ceramic substrate, and the double-sided copper-clad ceramic substrate includes:

a ceramic layer having opposing first and second surfaces;

a first copper layer on the first surface; the first copper layer is provided with a device area for fixedly connecting the semiconductor device;

a second copper layer on the second surface; the second copper layer is used for being fixed with the bottom of the containing cavity.

Preferably, in the above package structure, the semiconductor device is fixedly connected to a surface of the substrate on a side away from the bottom of the accommodating cavity through a first sintering layer;

and the surface of one side of the substrate, which is far away from the semiconductor device, is fixedly connected to the bottom of the accommodating cavity through a second sintering layer.

Preferably, in the above package structure, the semiconductor device forms an interconnection circuit through the substrate and the bonding wire.

Preferably, in the above package structure, the semiconductor device includes at least one of a silicon carbide MOSFET chip, a silicon carbide diode chip, and a silicon carbide IGBT chip.

Preferably, in the above package structure, the semiconductor devices are all diodes, and the interconnection circuit is a rectifier bridge circuit formed by interconnecting a plurality of the diodes.

Preferably, in the above package structure, the package further includes:

one end of each second electrode pin is positioned inside the accommodating cavity, and the other end of each second electrode pin penetrates through the side wall of the shell and is positioned outside the accommodating cavity;

and the thermistor is fixed on the substrate, and two ends of the thermistor are respectively connected with one second electrode pin through the substrate.

The present application further provides an electronic device, including: the package structure of any one of the above.

As can be seen from the above description, in the package structure of a semiconductor device and an electronic apparatus provided in the embodiments of the present application, the package structure includes: a housing having a receiving cavity; the accommodating cavity is provided with an opening; a plurality of first electrode pins are fixed on the side wall of the shell, one end of each first electrode pin is positioned in the containing cavity, and the other end of each first electrode pin penetrates through the side wall of the shell and is positioned outside the containing cavity; the base plate is fixed at the bottom of the accommodating cavity; a plurality of semiconductor devices fixed on the substrate; the semiconductor device is connected with the substrate and is connected with the first electrode pin through the substrate; a sealing cap for sealing the opening of the receiving cavity. According to the technical scheme, the semiconductor devices are packaged simultaneously through the same shell, and compared with a mode that the semiconductor devices are packaged in a plastic package mode respectively and independently, the size of a circuit system is reduced, and the miniaturization design of equipment is facilitated.

Drawings

In order to more clearly illustrate the embodiments of the present application or technical solutions in related technologies, the drawings used in the embodiments or descriptions of the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

The structures, proportions, and dimensions shown in the drawings and described in the specification are for illustrative purposes only and are not intended to limit the scope of the present disclosure, which is defined by the claims, but rather by the claims, it is understood that these drawings and their equivalents are merely illustrative and not intended to limit the scope of the present disclosure.

Fig. 1 is a front plan view of a semiconductor device package structure according to an embodiment of the present disclosure without a cap;

FIG. 2 isbase:Sub>A cross-sectional view of the package structure shown in FIG. 1 along the A-A' direction;

fig. 3 is a front plan view of a semiconductor device package structure capable of being sealed by a sealing cap according to an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a rectifier bridge circuit;

fig. 5 is a schematic diagram illustrating an interconnection structure of a semiconductor device on a surface of a substrate in a package structure according to an embodiment of the disclosure;

fig. 6 is a top view of a back side of a semiconductor device package structure provided by an embodiment of the present application;

fig. 7 is a cut-away view of the semiconductor device package structure of fig. 6;

fig. 8 is a cross-sectional view of a semiconductor device package structure according to an embodiment of the present application;

fig. 9 is a schematic flowchart of a packaging method according to an embodiment of the present disclosure.

Detailed Description

Embodiments of the present application will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the application are shown, and in which it is to be understood that the embodiments described are merely illustrative of some, but not all, of the embodiments of the application. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application.

In order to make the aforementioned objects, features and advantages of the present application more comprehensible, the present application is described in further detail with reference to the accompanying drawings and the detailed description.

Referring to fig. 1 to fig. 3, fig. 1 isbase:Sub>A front plan view ofbase:Sub>A semiconductor device package structure provided with no sealing cap according to an embodiment of the present application, fig. 2 isbase:Sub>A cross-sectional view of the package structure shown in fig. 1 alongbase:Sub>A-base:Sub>A' direction, and fig. 3 isbase:Sub>A front plan view of the semiconductor device package structure provided withbase:Sub>A sealing cap according to an embodiment of the present application after sealing, the package structure includes:

a housing 11, the housing 11 having a receiving cavity 111; the accommodating chamber 111 has an opening; a plurality of first electrode pins 12 are fixed on a side wall 112 of the housing 11, one end of each first electrode pin 12 is located inside the accommodating cavity 111, and the other end of each first electrode pin 12 passes through the side wall 112 of the housing 11 and is located outside the accommodating cavity 111;

a base plate 13, wherein the base plate 13 is fixed at the bottom of the accommodating cavity 111;

a plurality of semiconductor devices 14, the semiconductor devices 14 being fixed on the substrate 13; the semiconductor device 14 is connected to the substrate 13, and is connected to the first electrode pin 12 through the substrate 13; the first electrode pin 12 is used for connecting an external circuit;

a sealing cap 15, wherein the sealing cap 15 is used for sealing the opening of the accommodating cavity 111.

According to the technical scheme, the semiconductor devices 14 are simultaneously packaged through the same shell 11, and compared with the mode that the semiconductor devices 14 are respectively and independently packaged in a plastic package mode, the size of a circuit system is reduced, and the miniaturization design of equipment is facilitated.

The housing 11 is a metal housing. Adopt metal material's casing 11, on the one hand, can improve packaging structure's anti mechanical hitting ability avoids its damage owing to colliding with and leading to, and on the other hand, metal material is comparatively good heat conduction material, the heat that 14 during operations of semiconductor device produced passes through base plate 13 transmits extremely during the bottom of casing 11, can dispel the heat through metal material's casing 11 is rapid, improves semiconductor device 14's radiating efficiency.

In the embodiment of the application, the back surface of the packaging structure is used for fixedly mounting the radiator so as to improve the heat dissipation efficiency of the packaging structure. The front surface of the packaging structure is provided with the sealing cap 15, and the back surface of the packaging structure is the surface of one side of the bottom of the shell 11 departing from the sealing cap 15.

As shown in fig. 2, the substrate 13 is a double-sided copper-clad ceramic substrate, and the double-sided copper-clad ceramic substrate includes: a ceramic layer 131, the ceramic layer 131 having opposing first and second surfaces; a first copper layer 132, the first copper layer 132 being located at the first surface; the first copper layer 132 has a device region 21 for fixedly connecting the semiconductor device; a second copper layer 133, said second copper layer 133 being located at said second surface; the second copper layer 133 is used to fix to the bottom of the receiving cavity 11. The ceramic layer 131 is made of a good insulating material, has a good heat conduction effect, can realize insulation of the upper side and the lower side of the semiconductor device, and can enable heat generated by the semiconductor device 14 to be rapidly transferred downwards, so that the heat dissipation efficiency is improved.

The semiconductor devices 14 are fixedly connected by the same double-sided copper-clad ceramic substrate, so that the semiconductor devices 14 can be conveniently packaged. The first copper layer 142 has a predetermined pattern structure, such that the first copper layer includes a plurality of separated device regions 21, and at least one semiconductor device 14 is fixedly connected to a surface of each of the device regions 21. By arranging the pattern structure of the first copper layer 142, interconnection of a plurality of semiconductor devices 14 through bonding wires 22 is facilitated, and a required interconnection circuit is formed.

The second copper layer 133 completely covers the surface of the ceramic layer 131 facing away from the first copper layer 132, i.e. the second copper layer 133 is a full-surface copper layer. Through the second copper layer 133, not only the fixing of the substrate 13 and the bottom of the accommodating cavity 11 is facilitated, but also the speed of transferring heat from the substrate 13 to the bottom of the housing 11 can be increased, and the heat dissipation efficiency is improved.

In the embodiment of the present application, the semiconductor device 14 is fixedly connected to the surface of the substrate 13 on the side away from the bottom of the accommodating cavity 111 through the first sintering layer; the surface of the substrate 13 facing away from the semiconductor device 14 is fixedly connected to the bottom of the accommodating cavity 11 through a second sintering layer. The first sintered layer and the second sintered layer are not shown in the drawings of the present application.

The first sintering layer and the second sintering layer are nano metal sintering layers, and the nano metal sintering layers are nano silver sintering layers or nano copper sintering layers. The nano metal sintering layer is good in high-temperature resistance, has good connection reliability in a high-temperature environment, has good heat conduction performance, can improve the connection reliability of the packaging structure in a high-temperature working environment, can accelerate heat conduction of devices, and improves heat dissipation performance. Compared with a brazing connection mode, the connection reliability under a high-temperature application environment is improved, and the reliability of a semiconductor device packaging structure is improved.

In the traditional packaging process of discrete devices, a single semiconductor device 14 is basically adopted for packaging, and the topological structure of a circuit is single; the welding mainly adopts a soft soldering mode, the semiconductor device 14 and the metal frame or the substrate are welded together, and then the whole device is subjected to plastic package; and the application end is fixed with the radiator by smearing heat-conducting silicone grease at the bottom. As shown in fig. 1 and 2, the semiconductor device 14 forms an interconnection circuit through the substrate 13 and the bonding wire 22. The semiconductor devices 14 may be connected in series, parallel, or series-parallel to form the interconnect circuit.

In the embodiment of the present application, the same housing 11 is used to simultaneously package the plurality of semiconductor devices 14, and the plurality of semiconductor devices 14 can be interconnected inside the package structure, so that different circuit topologies can be realized inside the package structure based on requirements.

Therefore, the interconnection of the plurality of semiconductor devices 14 is directly realized in the packaging structure, and compared with the packaging structure adopting a plurality of packaged single semiconductor devices in the prior art, the packaging structure not only can reduce the volume of a circuit system, but also has better connection reliability and stability of an internal bonding wire.

Compared with the traditional silicon (Si) material, the silicon carbide (SiC) material has the excellent performances of large forbidden bandwidth, high breakdown electric field strength, high thermal conductivity and the like, so that the SiC device has better high-temperature characteristics, higher blocking voltage, lower power consumption and higher switching speed. In recent years, due to the increasing maturity of SiC materials, siC power electronic devices and high power modules based on SiC power electronic devices are becoming hot spots for research and development. In the present embodiment, the semiconductor device 14 is a silicon carbide chip.

Optionally, the semiconductor device 14 includes at least one of a silicon carbide MOSFET chip, a silicon carbide diode chip, and a silicon carbide IGBT chip. In the package structure, the chip types of the different semiconductor devices 14 may be the same or different, and the implementation manner of each semiconductor device 14 is selected based on a required interconnection circuit, and the chip type of each semiconductor device 14 is not specifically limited in this embodiment of the application.

As shown in fig. 1, the package structure further includes: two second electrode pins 24, one end of each second electrode pin 24 is located inside the accommodating cavity 111, and the other end of each second electrode pin 24 penetrates through the side wall of the shell 11 and is located outside the accommodating cavity 111; and the thermistor 23 is fixed on the substrate 11, and two ends of the thermistor 23 are respectively connected with one second electrode pin 24 through the substrate 13.

Referring to fig. 4, fig. 4 is a schematic diagram of a rectifier bridge circuit, which includes diodes D1 to D4. The cathode of the diode D1 and the cathode of the diode D2 are both connected to the first terminal P1, and the anode of the diode D3 and the anode of the diode D4 are both connected to the second terminal P2. The anode of the diode D1 and the cathode of the diode D3 are both connected to the third terminal P3. The anode of the diode D2 and the cathode of the four diode D4 are both connected to the fourth terminal P4. When the conventional package structure for packaging a single diode is used for realizing the rectifier bridge circuit shown in fig. 4, four diode package structures are required for interconnection.

In the package structure, the rectifier bridge circuit shown in fig. 4 may be implemented by one package structure. At this time, the semiconductor devices 14 are all provided as diodes, and the interconnection circuit is formed by interconnecting a plurality of diodes to form a rectifier bridge circuit as shown in fig. 4. For a single-phase rectifier bridge circuit structure of a diode, the original scheme of adopting 4 plastic packaged discrete devices is adopted, the scheme design of the embodiment of the application can realize the rectification function by one packaging structure, the size of an application system can be reduced, and meanwhile, the thermistor 23 is internally integrated and used for temperature monitoring and feedback in the working process of the device. In addition, a heat dissipation scheme is arranged on the basis of the packaging structure, so that the problem of poor heat dissipation in the application of the existing brazing and plastic packaging process is solved, and the high-temperature application environment of the device is met.

In the traditional packaging of discrete devices, the circuit topology is single, for example, for a single rectifier bridge, 4 finished plastic packaged diode devices are needed for circuit connection, on one hand, the application system is large in size, and on the other hand, the temperature of the devices cannot be monitored and fed back in the application process. Meanwhile, for the traditional brazing process and the plastic package shell, the device cannot work in a high-temperature application environment of more than 200 ℃, heat-conducting silicone grease is coated and fixed with a radiator to dissipate heat, and the heat dissipation effect is poor.

Referring to fig. 5, fig. 5 is a schematic diagram of an interconnection structure of substrate surface semiconductor devices in a package structure according to an embodiment of the present disclosure, in order to increase a circuit operating current when a rectifier bridge circuit is formed by a plurality of semiconductor devices 14 in the package structure, the package structure is provided with 8 semiconductor devices 14, that is, 8 diodes, which are sequentially a 1 st diode d1 to an 8 th diode d8. The cathodes of the 8 diodes are all fixedly connected to the corresponding device regions 21. The first copper layer 132 includes three separate device regions 21, a first device region 211, a second device region 212, and a third device region 213.

The ith diode and the (i + 1) th diode are connected in parallel and are equivalent to a high-current diode. i is an odd number and is less than 8.

Cathodes of the 1 st diode D1 to the 4 th diode are all fixed in the first device region 211, and the first device region 211 is connected to the first terminal P1, which is equivalent to that cathodes of the diode D1 and the diode D2 in fig. 4 are both connected to the first terminal P1.

The anodes of the 5 th diode D5 to the 8 th diode D8 are connected together, and the anode of the 8 th diode D8 is connected to the second terminal P2, which is equivalent to that the anodes of the diode D3 and the diode D4 in fig. 4 are both connected to the second terminal P2.

Anodes of the 3 rd diode D3 and the 4 th diode D4 are both connected to the third device region 213, and the third device region 213 is connected to the third terminal P3, which is equivalent to that the anode of the diode D1 in fig. 4 is connected to the third terminal P3. Cathodes of the 7 th diode D7 and the 8 th diode D8 are fixed in the third device region 213, which is equivalent to that the cathode of the diode D3 in fig. 4 is connected to the third terminal P3.

The anodes of the 1 st diode D1 and the 2 nd diode D2 are both connected to the second device region 212, and the second device region 212 is connected to the fourth terminal P4, which is equivalent to the anode of the diode D2 in fig. 4 being connected to the fourth terminal P4. Cathodes of the 5 th diode D5 and the 6 th diode D6 are both connected to the second device region 212, which is equivalent to that a cathode of the diode D4 in fig. 4 is connected to the fourth terminal P4.

In the package structure, the semiconductor device 14 is not limited to a diode, and the interconnection circuit formed by the plurality of semiconductor devices 14 is not limited to the rectifier bridge circuit described above. In other forms, the package structure may include at least one of a silicon carbide MOSFET chip, a silicon carbide diode chip, and a silicon carbide IGBT chip, and the interconnection circuit formed by the plurality of semiconductor devices 14 may be a power supply circuit, a switch circuit, and the like, and the embodiment of the present application is not particularly limited to the type of the semiconductor device 14 and the interconnection circuit formed by the semiconductor device 14.

In one mode, as shown in fig. 2, a surface of the housing 11 facing away from the cap 15 is provided as a flat surface. In another mode, as shown in fig. 6 and 7, in order to improve the heat dissipation efficiency of the package structure, a side surface of the housing 11 facing away from the sealing cap 15 may be provided with a non-planar structure, so that the heat dissipation area may be increased, and the flow channel 16 may be formed based on the non-planar structure, so as to improve the heat dissipation efficiency through the cooling liquid in the flow channel 1616.

Referring to fig. 6 and 7, fig. 6 is a top view of a back surface of a semiconductor device package structure provided in an embodiment of the present application, and fig. 7 is a cross-sectional view of the semiconductor device package structure shown in fig. 6, on the basis of the above embodiment, in the manner shown in fig. 6 and 7, a side surface of the housing 11 facing away from the accommodating cavity 111 has a flow channel 16 for guiding a cooling liquid. The cooling liquid may be water or ethanol, and the material of the cooling liquid in the embodiments of the present application is not limited.

In the manner shown in fig. 6 and 7, by providing the flow channel 16 on the side surface of the housing 11 away from the accommodating cavity 111, heat conducted from the semiconductor device 14 to the bottom of the bottom case 11 can be quickly taken away by the cooling liquid, so as to improve the heat dissipation efficiency of the package structure, and ensure the reliability and stability of the semiconductor device 14.

As shown in fig. 7, a side surface of the housing 11 facing away from the accommodating cavity 111 may be provided with a raised retaining wall structure 17, and the flow channel 16 may be formed by the retaining wall structure 17. The retaining wall structure 17 and the bottom of the housing 11 are of an integral structure.

Referring to fig. 8, fig. 8 is a cross-sectional view of a semiconductor device package structure according to an embodiment of the present disclosure, which is different from the manner shown in fig. 7 in that, in the manner shown in fig. 8, a side surface of the housing 11 facing away from the accommodating cavity 111 has a recessed structure, and the recessed structure serves as the flow channel 16.

The implementation manner of the flow channel 16 may be set based on requirements, and the specific implementation manner of the flow channel 16 in the embodiment of the present application is not limited.

In the implementation of the present application, the side wall 112 and the bottom of the housing 11 are an integral structure and can be formed by casting or machining with a numerical control machine.

In order to improve the heat dissipation efficiency of the package structure, after the sealing cap 15 is sealed, the accommodating cavity 111 has an insulating cooling liquid therein, and the insulating cooling liquid can rapidly dissipate heat generated by the operation of the semiconductor device 14 into the insulating cooling liquid, and the heat is rapidly transferred to the housing 11 through the insulating cooling liquid. The insulating cooling liquid may be silicon oil, etc., and the specific material of the insulating cooling liquid in the embodiments of the present application is not limited.

Based on the foregoing semiconductor device package structure embodiment, another embodiment of the present application further provides an electronic device, including: the package structure according to any one of the above embodiments.

The electronic equipment adopts the real-time semiconductor device packaging structure, so that the size of a circuit system can be reduced, and the equipment is convenient to miniaturize. And the temperature monitoring feedback can be used in the working process of the semiconductor device through the thermistor integrated in the packaging structure. In addition, through the specific heat dissipation structure design, the problem that the heat dissipation is poor in the application of the existing brazing and plastic packaging process is solved, so that the high-temperature application environment of the device is met.

Based on the above semiconductor device package structure embodiment, another embodiment of the present application further provides a packaging method for preparing the package structure according to any of the above embodiments, where the packaging method is as shown in fig. 9.

Referring to fig. 9, fig. 9 is a schematic flowchart of a packaging method provided in an embodiment of the present application, where the method includes:

step S11: the semiconductor device is fixedly connected to the substrate.

The semiconductor device may be sinter-fixed on the substrate by a sintering process. In this step, in order to monitor the operating temperature of the semiconductor device, the thermistor may be sintered and fixed on the substrate at the same time.

Step S12: and fixing the surface of one side of the substrate, which is far away from the semiconductor device, in a shell.

Wherein the housing has a receiving cavity having an opening; one side surface of the substrate, which is far away from the semiconductor device, is fixed at the bottom of the accommodating cavity; a plurality of first electrode pins are fixed on the side wall of the shell, one end of each first electrode pin is located inside the containing cavity, and the other end of each first electrode pin penetrates through the side wall of the shell and is located outside the containing cavity.

In this step, the substrate of the inherent semiconductor device may be sinter-fixed at the bottom of the accommodation chamber by a sintering process.

Step S13: connecting the substrate with the first pins.

In this step, the substrate is connected to the first pin by a wire bonding process. In this step, the individual semiconductor devices may also be interconnected by bonding wires based on the desired interconnection circuitry. The semiconductor devices can form interconnection circuits with different current specifications and different topological structures in a parallel connection mode, a series connection mode, a parallel connection mode, a series-parallel connection mode and the like.

Step S14: the containing cavity is sealed through a sealing cap.

After the cap is sealed, the packaging structure is tested to detect whether the packaging structure is qualified or not.

The packaging method is simple in manufacturing process and low in manufacturing cost. By the encapsulation method according to the embodiment of the present application, the encapsulation structure according to the embodiment can be formed, and the specific implementation manner of the encapsulation structure can be described with reference to the embodiment, which is not described in detail in the method embodiment.

The embodiments in the present description are described in a progressive manner, or in a parallel manner, or in a combination of a progressive manner and a parallel manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments can be referred to each other. As for the packaging method and the electronic device disclosed in the embodiments, since the packaging structure disclosed in the embodiments corresponds to the packaging method and the electronic device disclosed in the embodiments, the description is relatively simple, and the relevant points can be referred to the description of the relevant parts of the packaging structure.

It should be noted that in the description of the present application, the drawings and the description of the embodiments are to be regarded as illustrative in nature and not as restrictive. Like numerals refer to like structures throughout the description of the embodiments. Additionally, the figures may exaggerate the thicknesses of some layers, films, panels, regions, etc. for ease of understanding and ease of description. It will also be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In addition, "on 8230; means to position an element on or under another element, but not essentially on the upper side of the other element according to the direction of gravity.

The terms "upper," "lower," "top," "bottom," "inner," "outer," and the like refer to an orientation or positional relationship that is based on the orientation or positional relationship shown in the drawings for ease of description and simplicity of description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present application. When a component is referred to as being "connected" to another component, it can be directly connected to the other component or intervening components may also be present.

It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising one of 8230, and" comprising 8230does not exclude the presence of additional like elements in an article or device comprising the same element.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (9)

1. A package structure of a semiconductor device, comprising:

a housing having a receiving cavity; the accommodating cavity is provided with an opening; a plurality of first electrode pins are fixed on the side wall of the shell, one end of each first electrode pin is positioned in the containing cavity, and the other end of each first electrode pin penetrates through the side wall of the shell and is positioned outside the containing cavity;

the base plate is fixed at the bottom of the accommodating cavity;

a plurality of semiconductor devices fixed on the substrate; the semiconductor device is connected with the substrate and is connected with the first electrode pin through the substrate;

a sealing cap for sealing the opening of the receiving cavity.

2. The package structure according to claim 1, wherein a side surface of the housing facing away from the receiving cavity has a flow channel for guiding a cooling liquid.

3. The package structure of claim 1, wherein the substrate is a double-sided copper-clad ceramic substrate comprising:

a ceramic layer having opposing first and second surfaces;

a first copper layer on the first surface; the first copper layer is provided with a device area for fixedly connecting the semiconductor device;

a second copper layer on the second surface; the second copper layer is used for being fixed with the bottom of the accommodating cavity.

4. The package structure according to claim 1, wherein the semiconductor device is fixedly connected to a surface of the substrate on a side facing away from the bottom of the accommodating cavity through a first sintering layer;

and the surface of one side of the substrate, which is far away from the semiconductor device, is fixedly connected to the bottom of the accommodating cavity through a second sintering layer.

5. The package structure of claim 1, wherein the semiconductor devices form an interconnect circuit through the substrate and the bonding wires.

6. The package structure of claim 5, wherein the semiconductor device comprises at least one of a silicon carbide MOSFET chip, a silicon carbide diode chip, and a silicon carbide IGBT chip.

7. The package structure according to claim 5, wherein the semiconductor devices are diodes, and the interconnection circuit is a rectifier bridge circuit formed by interconnecting a plurality of the diodes.

8. The package structure of claim 5, further comprising:

one end of each second electrode pin is positioned inside the accommodating cavity, and the other end of each second electrode pin penetrates through the side wall of the shell and is positioned outside the accommodating cavity;

and the thermistor is fixed on the substrate, and two ends of the thermistor are respectively connected with one second electrode pin through the substrate.

9. An electronic device, comprising: an encapsulation structure according to any one of claims 1 to 8.

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