CN217363031U - On-chip compensation error amplifier for high-current DCDC power module - Google Patents
On-chip compensation error amplifier for high-current DCDC power module Download PDFInfo
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Abstract
The utility model discloses an on-chip compensation error amplifier for a heavy current DCDC power module, which charges a capacitor through current to form a soft start voltage VSS, and when the soft start voltage VSS is lower than a reference voltage VREF, the soft start voltage VSS and a feedback voltage VFB are compared to obtain an output voltage VC; when the soft start voltage VSS rises above the reference voltage VREF, the reference voltage VREF replaces the soft start voltage VSS and is compared with the feedback voltage VFB to obtain the output voltage VC. The eleventh P-type MOS tube MP11, the twelfth P-type MOS tube MP12, the tenth N-type MOS tube MN10 and the eleventh N-type MOS tube MN11 have larger width-to-length ratios, so that the large transconductance characteristic is realized, a secondary dominant pole far away from the origin is formed by the secondary dominant pole and the compensation resistor capacitor, and the system stability is ensured. The method can be applied to a high-current DCDC power supply module, the transconductance of the error amplifier is increased, the output resistance is reduced, the pole position of the output end of the error amplifier is far away from the original point position and serves as a secondary main pole of a power supply module system, and the stability of the system is ensured.
Description
Technical Field
The utility model belongs to the technical field of switching power supply, specifically belong to an on-chip compensation error amplifier for heavy current DCDC power module.
Background
With the scale expansion and the great increase of the operational capability of the electronic system, especially the application of high-quality image acquisition, processing and transmission, the power supply of the electronic system is required to have larger load capacity and faster transient response speed. Modern electronic systems, such as ASICs, FPGAs and processors in high performance communication, server and computing systems, require the use of core power supplies capable of generating 1.0V (or less) voltage directly from 12V or an intermediate bus, and require power supplies to provide on-load capability of up to tens or even hundreds of amps.
As is well known, a current mode DCDC converter usually includes two poles and a zero, and the corresponding zero pole position is set to ensure the system stability. In the high-current DCDC power supply module, in order to guarantee the stability of output voltage and the transient response requirement, the output capacitor needs to be configured up to hundreds of even thousands of microfarads, so that the pole of the output end is close to the original point position, and thus, the pole can only be used as the dominant pole of the high-current DCDC power supply module system, so that the pole of the output end of the error amplifier in the system is required to be used as the secondary dominant pole, and the stability and the better transient response performance of the system can be better guaranteed.
However, the pole at the output of the error amplifier in the prior art cannot be used as the secondary dominant pole, and cannot meet the application requirements.
SUMMERY OF THE UTILITY MODEL
In order to solve the problems existing in the prior art, the utility model provides an on-chip compensation error amplifier of big transconductance for solve above-mentioned problem.
In order to achieve the above object, the utility model provides a following technical scheme:
an on-chip compensation error amplifier for a high-current DCDC power module comprises a first P-type MOS tube MP1, a second P-type MOS tube MP2, a third P-type MOS tube MP3, a fourth P-type MOS tube MP4, a fifth P-type MOS tube MP5, a sixth P-type MOS tube MP6, a seventh P-type MOS tube MP7, an eighth P-type MOS tube MP8, a ninth P-type MOS tube MP9, a tenth P-type MOS tube MP10, an eleventh P-type MOS tube MP11, a twelfth P-type MOS tube MP12, a first N-type MOS tube MN1, a second N-type MOS tube MN2, a third N-type MOS tube MN3, a fourth N-type MOS tube MN4, a fifth N-type MOS tube MN5, a sixth N-type MOS tube MN6, a seventh N-type MOS tube MN7, an eighth N-type MOS tube MN8, a ninth N-type MOS tube MN9, an eleventh N-type MOS tube MN10, an eleventh N-type MOS tube MN 639, a tenth P-type MOS tube MN C and a tenth N-type MOS tube MN 639;
the source electrode of the first P-type MOS transistor MP1, the source electrode of the second P-type MOS transistor MP2, the source electrode of the fourth P-type MOS transistor MP4, the source electrode of the ninth P-type MOS transistor MP9, and the source electrode of the eleventh P-type MOS transistor MP11 are connected to an internal power supply INTVCC;
the gate of the first P-type MOS transistor MP1, the drain of the first P-type MOS transistor MP1, the gate of the third P-type MOS transistor MP3, the gate of the fifth P-type MOS transistor MP5, the gate of the tenth P-type MOS transistor MP10, and the gate of the twelfth P-type MOS transistor MP12 are connected to the drain of the second N-type MOS transistor MN 2;
the grid electrode of the second P-type MOS tube MP2, the grid electrode of the fourth P-type MOS tube MP4 and the drain electrode of the third P-type MOS tube MP3 are connected with the drain electrode of the third N-type MOS tube MN 3;
the drain electrode of the second P-type MOS transistor MP2 is connected to the source electrode of the third P-type MOS transistor MP3, and the drain electrode of the fourth P-type MOS transistor MP4 is connected to the source electrode of the fifth P-type MOS transistor MP 5; the drain of the fifth P-type MOS transistor MP5, the source of the sixth P-type MOS transistor MP6, the seventh P-type MOS transistor MP7 and the source of the eighth P-type MOS transistor MP8 are connected, and the gate of the sixth P-type MOS transistor MP6 is connected to an external feedback voltage VFB;
the drain of the sixth P-type MOS transistor MP6 is connected to the drain of the fourth N-type MOS transistor MN4, the gate of the fifth N-type MOS transistor MN5, and the gate of the ninth N-type MOS transistor MN9, and the gate of the seventh P-type MOS transistor MP7 is connected to the external reference voltage VREF; the drain electrode of the seventh P-type MOS transistor MP7 and the drain electrode of the eighth P-type MOS transistor MP8 are connected to the drain electrode of the sixth N-type MOS transistor MN6, the gate electrode of the seventh N-type MOS transistor MN7 and the gate electrode of the eleventh N-type MOS transistor MN 11;
a gate of the eighth P-type MOS transistor MP8 is connected to an external soft start voltage VSS, a gate of the ninth P-type MOS transistor MP9, a gate of the eleventh P-type MOS transistor MP11, and a drain of the tenth P-type MOS transistor MP10 is connected to a drain of the eighth N-type MOS transistor MN8, a drain of the ninth P-type MOS transistor MP9 is connected to a source of the tenth P-type MOS transistor MP10, a drain of the eleventh P-type MOS transistor MP11 is connected to a source of the twelfth P-type MOS transistor MP12, a drain of the twelfth P-type MOS transistor MP12, a drain of the tenth N-type MOS transistor MN10, and one end of the resistor R are connected to an external output port VC;
the drain electrode of the first N-type MOS tube MN1, the gate electrode of the first N-type MOS tube MN1, the gate electrode of the second N-type MOS tube MN2 and the gate electrode of the third N-type MOS tube MN3 are connected with an external bias current IBIAS;
the gate of the fourth N-type MOS transistor MN4, the gate of the sixth N-type MOS transistor MN6, the gate of the eighth N-type MOS transistor MN8, and the gate of the tenth N-type MOS transistor MN10 are connected to an external bias voltage VBIAS; the source of the fourth N-type MOS transistor MN4 is connected to the drain of the fifth N-type MOS transistor MN5, the source of the sixth N-type MOS transistor MN6 is connected to the drain of the seventh N-type MOS transistor MN7, the source of the eighth N-type MOS transistor MN8 is connected to the drain of the ninth N-type MOS transistor MN9, the source of the tenth N-type MOS transistor MN10 is connected to the drain of the eleventh N-type MOS transistor MN11, the other end of the resistor R is connected to one end of the capacitor C, the source of the first N-type MOS transistor MN1, the source of the second N-type MOS transistor MN2, the source of the third N-type MOS transistor MN3, the source of the fifth N-type MOS transistor MN5, the source of the seventh N-type MOS transistor MN7, the source of the ninth N-type MOS transistor MN9, the source of the eleventh N-type MOS transistor MN11, and the other end of the capacitor C are connected to the ground GND.
Preferably, the soft start voltage VSS is a ramp voltage formed by charging C with a current.
Preferably, when the soft-start voltage VSS is lower than the reference voltage VREF, the soft-start voltage VSS is compared with the feedback voltage VFB to obtain the output voltage VC.
Preferably, when the soft-start voltage VSS rises above the reference voltage VREF, the reference voltage VREF is compared with the feedback voltage VFB instead of the soft-start voltage VSS to obtain the output voltage VC.
Preferably, the ratio of layout areas among the fourth N-type MOS transistor MN4, the fifth N-type MOS transistor MN5, the sixth N-type MOS transistor MN6, and the seventh N-type MOS transistor MN7 is 1: 1.
Preferably, the ratio of layout areas among the ninth P-type MOS transistor MP9, the tenth P-type MOS transistor MP10, the eleventh P-type MOS transistor MP11, and the twelfth P-type MOS transistor MP12 is 1: N, where N is a positive integer greater than 1.
Preferably, the ratio of layout areas among the eighth N-type MOS transistor MN8, the ninth N-type MOS transistor MN9, the tenth N-type MOS transistor MN10, and the eleventh N-type MOS transistor MN11 is 1: N, and N is a positive integer greater than 1.
Compared with the prior art, the utility model discloses following profitable technological effect has:
the utility model provides a big on-chip compensation error amplifier of transconductance, the soft start voltage VSS who charges the formation to the electric capacity through the electric current, the eleventh P type MOS pipe MP11, twelfth P type MOS pipe MP12 and tenth N type MOS pipe MN10 of output stage, eleventh N type MOS pipe MN11 get great width length ratio, realize big transconductance characteristic, form a secondary main pole of keeping away from the original point with compensation resistance capacitance, guarantee system stability. The utility model discloses an in-chip compensation error amplifier can be applied to heavy current DCDC power module, through increase error amplifier's transconductance, reduces output resistance, makes the utmost point position of error amplifier output keep away from the initial point position, as the secondary dominant point of power module system, guarantees system stability.
Drawings
Fig. 1 is a schematic diagram of the large transconductance on-chip compensation error amplifier of the present invention.
Detailed Description
The present invention will now be described in further detail with reference to specific examples, which are intended to be illustrative, but not limiting, of the invention.
Examples
As shown in fig. 1, the large transconductance on-chip compensation error amplifier of the present invention includes a first P-type MOS transistor MP1, a second P-type MOS transistor MP2, a third P-type MOS transistor MP3, a fourth P-type MOS transistor MP4, a fifth P-type MOS transistor MP5, a sixth P-type MOS transistor MP6, a seventh P-type MOS transistor MP7, an eighth P-type MOS transistor MP8, a ninth P-type MOS transistor MP9, a tenth P-type MOS transistor MP10, an eleventh P-type MOS transistor MP11, a twelfth P-type MOS transistor MP12, a first N-type MOS transistor MN1, a second N-type MOS transistor MN2, a third N-type MOS transistor MN3, a fourth N-type MOS transistor MN4, a fifth N-type MOS transistor MN5, a sixth N-type MOS transistor MN6, a seventh N-type MOS transistor MN7, an eighth N-type MOS transistor MN 4624, a ninth N-type MOS transistor MN4, a fifth N-type MOS transistor MN5, an eleventh N-type MOS transistor MN11, a tenth N-type MOS transistor MN10, a tenth N-type MOS transistor MN C.
The specific connection relationship is as follows: the source of the first P-type MOS transistor MP1, the source of the second P-type MOS transistor MP2, the source of the fourth P-type MOS transistor MP4, the source of the ninth P-type MOS transistor MP9, and the source of the eleventh P-type MOS transistor MP11 are connected to the internal power supply INTVCC, the gate of the first P-type MOS transistor MP1, the drain of the first P-type MOS transistor MP1, the gate of the third P-type MOS transistor MP3, the gate of the fifth P-type MOS transistor MP5, the gate of the tenth P-type MOS transistor MP10, the gate of the twelfth P-type MOS transistor MP12 are connected to the drain of the second N-type MOS transistor MN2, the gate of the second P-type MOS transistor MP2, the gate of the fourth P-type MOS transistor MP4, the drain of the third P-type MOS transistor MP3 is connected to the drain of the third N-type MOS transistor MN3, the drain of the second P-type MOS transistor MP2 is connected to the source of the third P-type MOS transistor MP3, the source of the fifth P-type MOS transistor MP4, the drain of the fifth P-type MOS transistor MP 4624 is connected to the drain of the fifth P-type MOS transistor MP 4624, the fifth P-type MOS transistor MP4, the fifth P-type MOS transistor MP 4624 is connected to the drain of the fifth P4624, A seventh P-type MOS transistor MP7 is connected to the source of the eighth P-type MOS transistor MP8, a sixth P-type MOS transistor MP6 is connected to the external feedback voltage VFB, a sixth P-type MOS transistor MP6 is connected to the drain of the fourth N-type MOS transistor MN4, the gate of the fifth N-type MOS transistor MN5, and the gate of the ninth N-type MOS transistor MN9, a seventh P-type MOS transistor MP7 is connected to the external reference voltage VREF, a seventh P-type MOS transistor MP7, a eighth P-type MOS transistor MP8 is connected to the drain of the sixth N-type MOS transistor MN6, a seventh N-type MOS transistor MN7, and an eleventh N-type MOS transistor MN11, an eighth P-type MOS transistor MP8 is connected to the external soft-start voltage VSS, a ninth P-type MOS transistor MP9, an eleventh P-type MOS transistor MP11, a tenth P-type MOS transistor MP6 is connected to the drain of the ninth P-type MOS transistor MP 3527, and the drain of the eighth P-type MOS transistor MP 3642 are connected to the drain of the ninth N-type MOS 9, a drain of the eleventh P-type MOS transistor MP11 is connected to a source of the twelfth P-type MOS transistor MP12, a drain of the twelfth P-type MOS transistor MP12, a drain of the tenth N-type MOS transistor MN10, and one end of the resistor R is connected to the external output port VC, a drain of the first N-type MOS transistor MN1, a gate of the first N-type MOS transistor MN1, a gate of the second N-type MOS transistor MN2, and a gate of the third N-type MOS transistor MN3 are connected to the external bias current IBIAS, a gate of the fourth N-type MOS transistor MN4, a gate of the sixth N-type MOS transistor MN6, a gate of the eighth N-type MOS transistor MN8, and a gate of the tenth N-type MOS transistor MN10 are connected to the external bias voltage VBIAS, a source of the fourth N-type MOS transistor MN4 is connected to the drain of the fifth N-type MOS transistor MN5, a source of the sixth N-type MOS transistor MN6 is connected to a drain of the seventh N-type MOS transistor MN7, a drain of the eighth N-type MOS transistor MN 3527, a drain of the eleventh N-type MOS transistor MN11 is connected to the ninth N-type MOS transistor MN10, the other end of the resistor R is connected with one end of the capacitor C, and the source electrode of the first N-type MOS tube MN1, the source electrode of the second N-type MOS tube MN2, the source electrode of the third N-type MOS tube MN3, the source electrode of the fifth N-type MOS tube MN5, the source electrode of the seventh N-type MOS tube MN7, the source electrode of the ninth N-type MOS tube MN9, the source electrode of the eleventh N-type MOS tube MN11 and the other end of the capacitor C are connected with the ground end GND.
The eleventh P-type MOS tube MP11, the twelfth P-type MOS tube MP12, the tenth N-type MOS tube MN10 and the eleventh N-type MOS tube MN11 of the output stage have larger width-length ratio, namely the ratio of the layout areas among the fourth N-type MOS tube MN4, the fifth N-type MOS tube MN5, the sixth N-type MOS tube MN6 and the seventh N-type MOS tube MN7 is 1: 1.
The ratio of layout areas among the ninth P-type MOS tube MP9, the tenth P-type MOS tube MP10, the eleventh P-type MOS tube MP11 and the twelfth P-type MOS tube MP12 is 1: N, and N is a positive integer greater than 1.
The ratio of layout areas among the eighth N-type MOS transistor MN8, the ninth N-type MOS transistor MN9, the tenth N-type MOS transistor MN10 and the eleventh N-type MOS transistor MN11 is 1: N, and N is a positive integer greater than 1.
In the large-transconductance on-chip compensation error amplifier in the embodiment, the soft start voltage VSS is a ramp voltage formed by charging a capacitor through current, and when the soft start voltage VSS is lower than the reference voltage VREF, the soft start voltage VSS is compared with the feedback voltage VFB to obtain the output voltage VC; when the soft start voltage VSS rises above the reference voltage VREF, the reference voltage VREF replaces the soft start voltage VSS and is compared with the feedback voltage VFB to obtain the output voltage VC. The eleventh P-type MOS tube MP11, the twelfth P-type MOS tube MP12, the tenth N-type MOS tube MN10 and the eleventh N-type MOS tube MN11 have larger width-to-length ratios, so that the large transconductance characteristic is realized, a secondary dominant pole far away from the origin is formed by the secondary dominant pole and the compensation resistor capacitor, and the system stability is ensured.
Claims (7)
1. An on-chip compensation error amplifier for a high-current DCDC power module is characterized by comprising a first P-type MOS tube MP1, a second P-type MOS tube MP2, a third P-type MOS tube MP3, a fourth P-type MOS tube MP4, a fifth P-type MOS tube MP5, a sixth P-type MOS tube MP6, a seventh P-type MOS tube MP7, an eighth P-type MOS tube MP8, a ninth P-type MOS tube MP9, a tenth P-type MOS tube MP10, an eleventh P-type MOS tube MP11, a twelfth P-type MOS tube MP12, a first N-type MOS tube MN1, a second N-type MOS tube MN2, a third N-type MOS tube MN3, a fourth N-type MOS tube MN4, a fifth N-type MOS tube MN5, a sixth N-type MOS tube MN6, a seventh N-type MOS tube MN7, an eighth N-type MOS tube MN 4624, a fourth N-type MOS tube MN9, a ninth N-type MOS tube MN9, an eleventh N-type MOS tube MN10, an eleventh P-type MOS tube MN 63C and a tenth N-type MOS tube MN 639;
the source electrode of the first P-type MOS transistor MP1, the source electrode of the second P-type MOS transistor MP2, the source electrode of the fourth P-type MOS transistor MP4, the source electrode of the ninth P-type MOS transistor MP9, and the source electrode of the eleventh P-type MOS transistor MP11 are connected to an internal power supply INTVCC;
the gate of the first P-type MOS transistor MP1, the drain of the first P-type MOS transistor MP1, the gate of the third P-type MOS transistor MP3, the gate of the fifth P-type MOS transistor MP5, the gate of the tenth P-type MOS transistor MP10, and the gate of the twelfth P-type MOS transistor MP12 are connected to the drain of the second N-type MOS transistor MN 2;
the grid electrode of the second P-type MOS tube MP2, the grid electrode of the fourth P-type MOS tube MP4 and the drain electrode of the third P-type MOS tube MP3 are connected with the drain electrode of the third N-type MOS tube MN 3;
the drain electrode of the second P-type MOS transistor MP2 is connected to the source electrode of the third P-type MOS transistor MP3, and the drain electrode of the fourth P-type MOS transistor MP4 is connected to the source electrode of the fifth P-type MOS transistor MP 5; the drain of the fifth P-type MOS transistor MP5, the source of the sixth P-type MOS transistor MP6, the seventh P-type MOS transistor MP7 and the source of the eighth P-type MOS transistor MP8 are connected, and the gate of the sixth P-type MOS transistor MP6 is connected to an external feedback voltage VFB;
the drain of the sixth P-type MOS transistor MP6 is connected to the drain of the fourth N-type MOS transistor MN4, the gate of the fifth N-type MOS transistor MN5, and the gate of the ninth N-type MOS transistor MN9, and the gate of the seventh P-type MOS transistor MP7 is connected to an external reference voltage VREF; the drain electrode of the seventh P-type MOS transistor MP7 and the drain electrode of the eighth P-type MOS transistor MP8 are connected to the drain electrode of the sixth N-type MOS transistor MN6, the gate electrode of the seventh N-type MOS transistor MN7 and the gate electrode of the eleventh N-type MOS transistor MN 11;
the gate of the eighth P-type MOS transistor MP8 is connected to an external soft-start voltage VSS, the gate of the ninth P-type MOS transistor MP9, the gate of the eleventh P-type MOS transistor MP11, and the drain of the tenth P-type MOS transistor MP10 are connected to the drain of the eighth N-type MOS transistor MN8, the drain of the ninth P-type MOS transistor MP9 is connected to the source of the tenth P-type MOS transistor MP10, the drain of the eleventh P-type MOS transistor MP11 is connected to the source of the twelfth P-type MOS transistor MP12, and the drain of the twelfth P-type MOS transistor MP12, the drain of the tenth N-type MOS transistor MN10, and one end of the resistor R are connected to an external output port VC;
the drain electrode of the first N-type MOS tube MN1, the gate electrode of the first N-type MOS tube MN1, the gate electrode of the second N-type MOS tube MN2 and the gate electrode of the third N-type MOS tube MN3 are connected with an external bias current IBIAS;
the gate of the fourth N-type MOS transistor MN4, the gate of the sixth N-type MOS transistor MN6, the gate of the eighth N-type MOS transistor MN8, and the gate of the tenth N-type MOS transistor MN10 are connected to an external bias voltage VBIAS; the source of the fourth N-type MOS transistor MN4 is connected to the drain of the fifth N-type MOS transistor MN5, the source of the sixth N-type MOS transistor MN6 is connected to the drain of the seventh N-type MOS transistor MN7, the source of the eighth N-type MOS transistor MN8 is connected to the drain of the ninth N-type MOS transistor MN9, the source of the tenth N-type MOS transistor MN10 is connected to the drain of the eleventh N-type MOS transistor MN11, the other end of the resistor R is connected to one end of the capacitor C, the source of the first N-type MOS transistor MN1, the source of the second N-type MOS transistor MN2, the source of the third N-type MOS transistor MN3, the source of the fifth N-type MOS transistor MN5, the source of the seventh N-type MOS transistor MN7, the source of the ninth N-type MOS transistor MN9, the source of the eleventh N-type MOS transistor MN11, and the other end of the capacitor C are connected to ground GND.
2. The on-chip compensated error amplifier for high current DCDC power supply module of claim 1, wherein the soft-start voltage VSS is a ramp voltage formed by charging C with current.
3. The on-chip compensated error amplifier for high current DCDC power supply module of claim 1, wherein the output voltage VC is obtained by comparing the soft-start voltage VSS with the feedback voltage VFB when the soft-start voltage VSS is lower than the reference voltage VREF.
4. The on-chip compensated error amplifier for high current DCDC power supply module of claim 1, wherein when the soft-start voltage VSS rises above the reference voltage VREF, the reference voltage VREF is compared with the feedback voltage VFB instead of the soft-start voltage VSS to obtain the output voltage VC.
5. The on-chip compensation error amplifier for the high-current DCDC power supply module of claim 1, wherein the ratio of layout areas among the fourth N-type MOS transistor MN4, the fifth N-type MOS transistor MN5, the sixth N-type MOS transistor MN6 and the seventh N-type MOS transistor MN7 is 1: 1.
6. The on-chip compensation error amplifier for the large-current DCDC power supply module as claimed in claim 1, wherein the layout area ratio between the ninth P-type MOS transistor MP9, the tenth P-type MOS transistor MP10, the eleventh P-type MOS transistor MP11 and the twelfth P-type MOS transistor MP12 is 1: N, and N is a positive integer greater than 1.
7. The on-chip compensation error amplifier for the large-current DCDC power supply module as claimed in claim 1, wherein the ratio of layout areas between the eighth N-type MOS transistor MN8, the ninth N-type MOS transistor MN9, the tenth N-type MOS transistor MN10 and the eleventh N-type MOS transistor MN11 is 1: N, and N is a positive integer greater than 1.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117118219A (en) * | 2023-10-08 | 2023-11-24 | 西安航天民芯科技有限公司 | On-chip integrated soft start circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117118219A (en) * | 2023-10-08 | 2023-11-24 | 西安航天民芯科技有限公司 | On-chip integrated soft start circuit |
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