CN114895743B - Low starting current circuit for dynamic bias current LDO - Google Patents
Low starting current circuit for dynamic bias current LDO Download PDFInfo
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- CN114895743B CN114895743B CN202210575238.1A CN202210575238A CN114895743B CN 114895743 B CN114895743 B CN 114895743B CN 202210575238 A CN202210575238 A CN 202210575238A CN 114895743 B CN114895743 B CN 114895743B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
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Abstract
The invention relates to a linear voltage regulator chip, in particular to a low starting current circuit for a dynamic bias current LDO. It includes a power circuit and a control circuit. The input end of the power circuit is connected with VIN, and the output end of the power circuit outputs VOUT. The control circuit comprises an operational amplifier and a MOS tube N3, wherein the non-inverting input end of the operational amplifier is connected with a reference voltage VREF, the inverting input end of the operational amplifier is connected with the control circuit in an adapting way, the inverting input end of the operational amplifier is used for receiving a voltage feedback VFB of the control circuit, the output end of the operational amplifier is connected with the grid electrode of the MOS tube N3, and the drain electrode of the MOS tube N3 is connected with the power circuit in an adapting way. It is characterized by also comprising a comparator. The source electrode of the MOS tube N3 is connected with one end of a resistor R3, and the other end of the resistor R3 is grounded. The output end of the power circuit is connected with the non-inverting input end of the comparator, the inverting input end of the comparator is connected with VIN, and the output end of the comparator is connected with the source electrode of the MOS tube N3. The LDO adopting the circuit has small static power consumption and small static current during starting.
Description
Technical Field
The invention relates to a linear voltage regulator chip, in particular to a low starting current circuit for a dynamic bias current LDO.
Background
With the development of technology, more and more linear power chips are needed in the current power field, and LDOs with low output voltage and large current are widely applied to various MCUs and mainboards. As is well known, LDOs include a P-type differential pair transport amplifier and an N-type differential pair transport amplifier, when the LDOs with low output voltages are used, the FB terminal voltage is very low, the working voltage required by the G terminal of the N-type differential pair is relatively high, usually >1V, in this case, the LDOs of the N-type differential pair cannot work normally, but the LDOs of the P-type differential pair transport amplifier do not have the problem, and the LDOs of the P-type differential pair transport amplifier usually adopts a dynamic bias current manner in order to improve the load capacity and dynamic characteristics, as shown in fig. 1. However, the disadvantage of excessive quiescent current during start-up is also brought, and the reason for the generation is that the output does not reach the set value when the input voltage is low, the very high wanted control power P-tube pulled by the G end of the output end N3 of the transport amplifier gives more current to make the output reach the set value, and the path has very high quiescent power consumption, such as the paths of the MOS tube P5 and the MOS tube N3 in fig. 1.
Disclosure of Invention
The invention aims to solve the technical problem of improving a low starting current circuit for a dynamic bias current LDO, and the LDO adopting the circuit has small static power consumption and small static current during starting. The problem of static power consumption is big in the background art, and quiescent current is too big when starting is solved.
In order to solve the problems, the following technical scheme is provided:
The low start-up current circuit for the dynamic bias current LDO of the present invention comprises a power circuit and a control circuit. The input end of the power circuit is connected with VIN, and the output end of the power circuit outputs VOUT. The control circuit comprises an operational amplifier and a MOS tube N3, wherein the non-inverting input end of the operational amplifier is connected with a reference voltage VREF, the inverting input end of the operational amplifier is connected with the control circuit in an adaptive manner, the inverting input end of the operational amplifier is used for receiving a voltage feedback VFB of the control circuit, the output end of the operational amplifier is connected with the grid electrode of the MOS tube N3, and the drain electrode of the MOS tube N3 is connected with the power circuit in an adaptive manner. It is characterized by also comprising a comparator. The source electrode of the MOS tube N3 is connected with one end of a resistor R3, and the other end of the resistor R3 is grounded. The output end of the power circuit is connected with the non-inverting input end of the comparator, the inverting input end of the comparator is connected with VIN, and the output end of the comparator is connected with the source electrode of the MOS tube N3.
The output end of the power circuit is connected with one end of a resistor R1, the other end of the resistor R1 is respectively connected with the output end of the transport amplifier and one end of a resistor R2, and the other end of the resistor R2 is grounded.
The power circuit comprises a first current mirror, wherein the first current mirror comprises a MOS tube P5 and a MOS tube P6. The source electrode of the MOS tube P5 and the source electrode of the MOS tube P6 are connected with VIN, the grid electrode of the MOS tube P5 is connected with the drain electrode of the MOS tube P5 and the grid electrode of the MOS tube P6 respectively, the drain electrode of the MOS tube P5 is connected with the drain electrode of the MOS tube N3, and the drain electrode of the MOS tube P6 is the output end of the power circuit.
The operational amplifier comprises an MOS tube P1, an MOS tube P2 and a current mirror II, wherein the current mirror II comprises an MOS tube N1 and an MOS tube N2. The grid electrode of the MOS tube P1 is the non-inverting input end of the operational amplifier, the grid electrode of the MOS tube P2 is the inverting input end of the operational amplifier, and the source electrode of the MOS tube P1 is connected with the source electrode of the MOS tube P2 to form a power supply end of the operational amplifier. The drain electrode of the MOS tube P1 is respectively connected with the drain electrode of the MOS tube N1, the grid electrode of the MOS tube N1 and the grid electrode of the MOS tube N2, and the source electrode of the MOS tube N1 and the source electrode of the MOS tube N2 are grounded. The drain electrode of the MOS tube P2 is the output end of the operational amplifier and is connected with the drain electrode of the MOS tube P2 and the drain electrode of the MOS tube N2.
The comparator comprises a differential pair, a resistor R4, a resistor R5, a MOS tube N4, a MOS tube N5 and a MOS tube N6; the differential pair comprises a MOS tube P7 and a MOS tube P8. The source electrode of the MOS tube P7 is the non-inverting input end of the comparator, the source electrode of the MOS tube P8 is the inverting input end of the comparator, and the drain electrode of the MOS tube N6 is the output end of the comparator. The grid electrode of the MOS tube P7 is connected with the drain electrode of the MOS tube P7 and the grid electrode of the MOS tube P8 respectively, the drain electrode of the MOS tube P7 is connected with one end of a resistor R4, the other end of the resistor R4 is connected with the drain electrode of the MOS tube N4, the source electrode of the MOS tube N4 is grounded, and the grid electrode of the MOS tube N4 is connected with the grid electrode of the MOS tube N5 and the grid electrode of the MOS tube N1 respectively. The drain electrode of the MOS tube P8 is connected with one end of a resistor R5, the other end of the resistor R5 is respectively connected with the grid electrode of the MOS tube N6 and the drain electrode of the MOS tube N5, and the MOS tube N5 and the source electrode of the MOS tube N6 are grounded.
The power supply end of the operational amplifier is adaptively connected with a current mirror IV, the current mirror IV comprises a MOS tube P3 and a MOS tube P4, the source electrode of the MOS tube P3 and the source electrode of the MOS tube P4 are both connected with a power supply VDD, the grid electrode of the MOS tube P3 is respectively connected with the drain electrode of the MOS tube P3 and the grid electrode of the MOS tube P4, the drain electrode of the MOS tube P3 is connected with a basic current IB, and the drain electrode of the MOS tube P4 is connected with the power supply end of the operational amplifier.
By adopting the scheme, the method has the following advantages:
Because the source electrode of the MOS tube N3 of the low starting current circuit for the dynamic bias current LDO is connected with one end of the resistor R3, the other end of the resistor R3 is grounded, the output end of the power circuit is connected with the non-inverting input end of the comparator, the inverting input end of the comparator is connected with VIN, and the output end of the comparator is connected with the source electrode of the MOS tube N3. When the MOS transistor N6 is in an off state when the input voltage is lower, the resistor R3 is larger in resistance, and when the MOS transistor N6 is static, the source end of the N3 is pulled up to enter a semi-conducting state when small current flows through the resistor R3 because the resistance of the resistor R3 is larger, and the resistor R3 is equivalent to playing a role of stopping, so that the static power consumption of the circuit is reduced. When the input voltage is larger than the output voltage by a certain value, the output end of the comparator is pulled up, N6 is conducted, the resistor R3 is short-circuited by N6, and larger current can flow between the source electrode and the drain electrode of the MOS tube N3, so that the power circuit obtains the driving voltage, the whole chip works normally, the problem of overlarge quiescent current during starting is avoided, and when the input voltage is larger than the output voltage by a certain value, the output light load can be ensured to be normal only by extremely small current through the paths of P5 and N3, and the problem is avoided.
Drawings
FIG. 1 is a schematic diagram of an LDO of a P-type differential pair transport amplifier in the background art;
FIG. 2 is a schematic diagram of a low start-up current circuit for a dynamic bias current LDO of the present invention;
FIG. 3 is a graph of quiescent current waveforms and output voltage waveforms of an LDO without the present circuit for DC scanning at VIN from 0V to 5V;
FIG. 4 is a graph of quiescent current waveforms and output voltage waveforms of an LDO incorporating the circuit of the present invention for DC scanning from 0V to 5V at VIN;
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings.
As shown in fig. 2, the low start-up current circuit for a dynamic bias current LDO of the present invention comprises a power circuit, a control circuit and a comparator 4. The input end of the power circuit is connected with VIN, and the output end of the power circuit outputs VOUT. The control circuit comprises an operational amplifier 2 and a MOS tube N3, wherein the non-inverting input end of the operational amplifier 2 is connected with a reference voltage VREF, the inverting input end of the operational amplifier 2 is connected with the control circuit in an adaptive manner, the inverting input end of the operational amplifier 2 is used for receiving a voltage feedback VFB of the control circuit, the output end of the operational amplifier 2 is connected with the grid electrode of the MOS tube N3, and the drain electrode of the MOS tube N3 is connected with the power circuit in an adaptive manner. The source electrode of the MOS tube N3 is connected with one end of a resistor R3, and the other end of the resistor R3 is grounded. The output end of the power circuit is connected with the non-inverting input end of the comparator 4, the inverting input end of the comparator 4 is connected with VIN, and the output end of the comparator 4 is connected with the source electrode of the MOS tube N3. The output end of the power circuit is connected with one end of a resistor R1, the other end of the resistor R1 is respectively connected with the output end of the transport amplifier and one end of a resistor R2, and the other end of the resistor R2 is grounded.
The resistor R2 plays a role of large resistance, and can be replaced by other electrical elements capable of realizing large resistance.
The power circuit comprises a first current mirror 3, wherein the first current mirror 3 comprises a MOS tube P5 and a MOS tube P6. The source electrode of the MOS tube P5 and the source electrode of the MOS tube P6 are connected with VIN, the grid electrode of the MOS tube P5 is connected with the drain electrode of the MOS tube P5 and the grid electrode of the MOS tube P6 respectively, the drain electrode of the MOS tube P5 is connected with the drain electrode of the MOS tube N3, and the drain electrode of the MOS tube P6 is the output end of the power circuit.
The operational amplifier 2 comprises a MOS tube P1, a MOS tube P2 and a second current mirror 6, wherein the second current mirror 6 comprises a MOS tube N1 and a MOS tube N2. The grid electrode of the MOS tube P1 is the non-inverting input end of the operational amplifier 2, the grid electrode of the MOS tube P2 is the inverting input end of the operational amplifier 2, and the source electrode of the MOS tube P1 is connected with the source electrode of the MOS tube P2 to form a power supply end of the operational amplifier 2. The drain electrode of the MOS tube P1 is respectively connected with the drain electrode of the MOS tube N1, the grid electrode of the MOS tube N1 and the grid electrode of the MOS tube N2, and the source electrode of the MOS tube N1 and the source electrode of the MOS tube N2 are grounded. The drain electrode of the MOS tube P2 is the output end of the operational amplifier 2 and is connected with the drain electrode of the MOS tube P2 and the drain electrode of the MOS tube N2.
The comparator 4 comprises a differential pair 5, a resistor R4, a resistor R5, a MOS tube N4, a MOS tube N5 and a MOS tube N6. The differential pair 5 is a differential pair of current comparators. The differential pair 5 comprises a MOS tube P7 and a MOS tube P8. The source electrode of the MOS tube P7 is the non-inverting input end of the comparator 4, the source electrode of the MOS tube P8 is the inverting input end of the comparator 4, and the drain electrode of the MOS tube N6 is the output end of the comparator 4. The grid electrode of the MOS tube P7 is connected with the drain electrode of the MOS tube P7 and the grid electrode of the MOS tube P8 respectively, the drain electrode of the MOS tube P7 is connected with one end of a resistor R4, the other end of the resistor R4 is connected with the drain electrode of the MOS tube N4, the source electrode of the MOS tube N4 is grounded, and the grid electrode of the MOS tube N4 is connected with the grid electrode of the MOS tube N5 and the grid electrode of the MOS tube N1 respectively. The drain electrode of the MOS tube P8 is connected with one end of a resistor R5, the other end of the resistor R5 is respectively connected with the grid electrode of the MOS tube N6 and the drain electrode of the MOS tube N5, and the MOS tube N5 and the source electrode of the MOS tube N6 are grounded.
The power supply end of the operational amplifier 2 is adaptively connected with a current mirror IV 1, the current mirror IV 1 comprises a MOS tube P3 and a MOS tube P4, the source electrode of the MOS tube P3 and the source electrode of the MOS tube P4 are both connected with a power supply VDD, the grid electrode of the MOS tube P3 is respectively connected with the drain electrode of the MOS tube P3 and the grid electrode of the MOS tube P4, the drain electrode of the MOS tube P3 is connected with a basic current IB, and the drain electrode of the MOS tube P4 is connected with the power supply end of the operational amplifier 2.
The low-starting current circuit of the dynamic bias current LDO of the invention utilizes a resistor R3 to limit excessive static power consumption, a comparator 4 consisting of R4, R5, P7, P8, N4, N5 and N6 is added, when the input voltage is larger than a certain value of the output voltage, N6 is conducted, the chip works normally, and the value is determined by adjusting the proportion of P7 and P8 and the resistance value of R4 and R5.
In this embodiment, the resistance of the resistor R3 is greater than 1 megaohm, and in the static state, because the resistance of R3 is greater, the source end of N3 is pulled up to enter the semi-conductive state when a small current flows, and R3 acts as a stop, thereby reducing the static power consumption of the circuit.
When VIN is larger than VOUT by a certain value, the value is determined by adjusting the proportion of the MOS tube P7 and the MOS tube P8 and the resistance values of the resistor R4 and the resistor R5, the output end of the operational amplifier 2 sends out a signal, the MOS tube N3 is conducted, the output end of the comparator 4 is pulled up, the signal is input into the current mirror I3 through the MOS tube N3 as the basic current of the current mirror I3, and the LDO works normally.
Fig. 3 and 4 show LDO simulation waveforms of VIN from 0V to 5V for DC scan, the upper half of fig. 3 and 4 shows quiescent current waveforms, and the lower half shows output voltage waveforms, as shown in fig. 3, with the maximum quiescent power consumption of 2Ma before LDO without the circuit of the present invention. As shown in FIG. 4, the maximum static power consumption of the LDO after the circuit is added is about 2uA, so that the static power consumption of the LDO is greatly reduced, and the problem of overlarge static current during starting is perfectly solved.
Claims (4)
1. A low start-up current circuit for a dynamic bias current LDO includes a power circuit and a control circuit; the input end of the power circuit is connected with VIN, and the output end of the power circuit outputs VOUT; the control circuit comprises an operational amplifier (2) and a MOS tube N3, wherein the non-inverting input end of the operational amplifier (2) is connected with a reference voltage VREF, the inverting input end of the operational amplifier (2) is connected with the control circuit in an adaptive manner, the inverting input end of the operational amplifier (2) is used for receiving a voltage feedback VFB of the control circuit, the output end of the operational amplifier (2) is connected with the grid electrode of the MOS tube N3, and the drain electrode of the MOS tube N3 is connected with the power circuit in an adaptive manner; characterized by further comprising a comparator (4); the source electrode of the MOS tube N3 is connected with one end of a resistor R3, and the other end of the resistor R3 is grounded; the output end of the power circuit is connected with the non-inverting input end of the comparator (4), the inverting input end of the comparator (4) is connected with VIN, and the output end of the comparator (4) is connected with the source electrode of the MOS tube N3; the operational amplifier (2) comprises a MOS tube P1, a MOS tube P2 and a second current mirror (6), wherein the second current mirror (6) comprises a MOS tube N1 and a MOS tube N2; the grid electrode of the MOS tube P1 is a non-inverting input end of the operational amplifier (2), the grid electrode of the MOS tube P2 is an inverting input end of the operational amplifier (2), and the source electrode of the MOS tube P1 is connected with the source electrode of the MOS tube P2 to form a power supply end of the operational amplifier (2); the drain electrode of the MOS tube P1 is respectively connected with the drain electrode of the MOS tube N1, the grid electrode of the MOS tube N1 and the grid electrode of the MOS tube N2, and the source electrode of the MOS tube N1 and the source electrode of the MOS tube N2 are grounded; the drain electrode of the MOS tube P2 is the output end of the operational amplifier (2) and is connected with the drain electrode of the MOS tube P2 and the drain electrode of the MOS tube N2; the comparator (4) comprises a differential pair (5), a resistor R4, a resistor R5, a MOS tube N4, a MOS tube N5 and a MOS tube N6; the differential pair (5) comprises a MOS tube P7 and a MOS tube P8; the source electrode of the MOS tube P7 is the non-inverting input end of the comparator (4), the source electrode of the MOS tube P8 is the inverting input end of the comparator (4), and the drain electrode of the MOS tube N6 is the output end of the comparator (4); the grid electrode of the MOS tube P7 is respectively connected with the drain electrode of the MOS tube P7 and the grid electrode of the MOS tube P8, the drain electrode of the MOS tube P7 is connected with one end of a resistor R4, the other end of the resistor R4 is connected with the drain electrode of the MOS tube N4, the source electrode of the MOS tube N4 is grounded, and the grid electrode of the MOS tube N4 is respectively connected with the grid electrode of the MOS tube N5 and the grid electrode of the MOS tube N1; the drain electrode of the MOS tube P8 is connected with one end of a resistor R5, the other end of the resistor R5 is respectively connected with the grid electrode of the MOS tube N6 and the drain electrode of the MOS tube N5, and the MOS tube N5 and the source electrode of the MOS tube N6 are grounded.
2. The low start-up current circuit for a dynamic bias current LDO of claim 1, wherein the output of the power circuit is connected to one end of a resistor R1, the other end of the resistor R1 is connected to the output of the sense amplifier and one end of a resistor R2, respectively, and the other end of the resistor R2 is grounded.
3. The low start-up current circuit for a dynamic bias current LDO of claim 1, wherein the power circuit comprises a first current mirror (3), the first current mirror (3) comprising a MOS transistor P5 and a MOS transistor P6; the source electrode of the MOS tube P5 and the source electrode of the MOS tube P6 are connected with VIN, the grid electrode of the MOS tube P5 is connected with the drain electrode of the MOS tube P5 and the grid electrode of the MOS tube P6 respectively, the drain electrode of the MOS tube P5 is connected with the drain electrode of the MOS tube N3, and the drain electrode of the MOS tube P6 is the output end of the power circuit.
4. A low start-up current circuit for a dynamic bias current LDO according to any one of claims 1-3, wherein the power supply end of the operational amplifier (2) is adapted to be connected with a current mirror four (1), the current mirror four (1) comprises a MOS transistor P3 and a MOS transistor P4, the source of the MOS transistor P3 and the source of the MOS transistor P4 are both connected to a power supply VDD, the gate of the MOS transistor P3 is connected to the drain thereof and the gate of the MOS transistor P4, the drain of the MOS transistor P3 is connected to a basic current IB, and the drain of the MOS transistor P4 is connected to the power supply end of the operational amplifier (2).
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210575238.1A CN114895743B (en) | 2022-05-25 | 2022-05-25 | Low starting current circuit for dynamic bias current LDO |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210575238.1A CN114895743B (en) | 2022-05-25 | 2022-05-25 | Low starting current circuit for dynamic bias current LDO |
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| CN114895743A CN114895743A (en) | 2022-08-12 |
| CN114895743B true CN114895743B (en) | 2024-06-25 |
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| CN117032378A (en) * | 2023-08-24 | 2023-11-10 | 无锡迈尔斯通集成电路有限公司 | Low-power consumption LDO circuit based on depletion type MOS tube |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107066014A (en) * | 2017-06-29 | 2017-08-18 | 英麦科（厦门）微电子科技有限公司 | A kind of low pressure difference linear voltage regulator of super low-power consumption |
| CN111474973A (en) * | 2020-05-22 | 2020-07-31 | 深圳市创新微源半导体有限公司 | Novel current foldback circuit applied to L DO |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN207731181U (en) * | 2018-01-26 | 2018-08-14 | 成都市海芯微纳电子科技有限公司 | The LDO linear voltage regulators of New-type CMOS structure |
| US10915121B2 (en) * | 2018-02-19 | 2021-02-09 | Texas Instruments Incorporated | Low dropout regulator (LDO) with frequency-dependent resistance device for pole tracking compensation |
| CN111880596B (en) * | 2020-07-07 | 2022-01-18 | 芯创智（北京）微电子有限公司 | Dynamic bias circuit applied to ultralow static current LDO |
| CN112068627B (en) * | 2020-09-11 | 2021-04-09 | 杭州万高科技股份有限公司 | Voltage output regulating module |
| CN113253792B (en) * | 2021-06-22 | 2022-07-26 | 南京微盟电子有限公司 | Circuit for controlling static power consumption of LDO (Low dropout regulator) voltage drop state |
| CN215642444U (en) * | 2021-09-13 | 2022-01-25 | 苏州大学 | Low quiescent current NMOS type fully integrated LDO circuit |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107066014A (en) * | 2017-06-29 | 2017-08-18 | 英麦科（厦门）微电子科技有限公司 | A kind of low pressure difference linear voltage regulator of super low-power consumption |
| CN111474973A (en) * | 2020-05-22 | 2020-07-31 | 深圳市创新微源半导体有限公司 | Novel current foldback circuit applied to L DO |
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