CN217306496U - Integrated circuit packaging structure containing radio frequency chip - Google Patents

Integrated circuit packaging structure containing radio frequency chip Download PDF

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Publication number
CN217306496U
CN217306496U CN202220899745.6U CN202220899745U CN217306496U CN 217306496 U CN217306496 U CN 217306496U CN 202220899745 U CN202220899745 U CN 202220899745U CN 217306496 U CN217306496 U CN 217306496U
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China
Prior art keywords
layer
circuit
circuit structure
chip
area
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Active
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CN202220899745.6U
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Chinese (zh)
Inventor
崔成强
杨斌
刘宇
华显刚
林挺宇
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Guangdong Fozhixin Microelectronics Technology Research Co ltd
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Guangdong Fozhixin Microelectronics Technology Research Co ltd
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Priority to CN202220899745.6U priority Critical patent/CN217306496U/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Abstract

The utility model discloses an integrated circuit packaging structure who contains radio frequency chip, include: the circuit structure comprises a first plastic packaging layer and a circuit structure, wherein the circuit structure is provided with a first area and a second area; the shielding wall is embedded into the first plastic packaging layer and positioned around the first area, and one end of the shielding wall is connected with the circuit structure; the plurality of conductive columns are embedded into the first plastic package layer and distributed in the second area, and one ends of the conductive columns are connected with the circuit structure; the shielding cover and the third circuit layer are formed by patterning the metal layer and are positioned on one side of the first plastic packaging layer, which is far away from the circuit structure, the periphery of the shielding cover is connected with one end of the shielding wall, the shielding wall and the shielding cover form a shielding cover, and the third circuit layer is connected with the conductive column; the first chip is a radio frequency chip, is positioned in the shielding case and is connected with the circuit structure; the second chip is positioned in the second area and is connected with the circuit structure; the second plastic package layer and a third chip, the third chip is sealed in the second plastic package layer and connected with the third circuit layer. The novel structure is simple, and can effectively reduce crosstalk.

Description

Integrated circuit packaging structure containing radio frequency chip
Technical Field
The utility model relates to an advanced electronic packaging technology field, concretely relates to integrated circuit packaging structure who contains radio frequency chip.
Background
In recent years, with the demand for miniaturization development of electronic products, the packaging technology is continuously innovated, and the intelligent module technology is rapidly developed. Due to the high distribution density of electronic components, the short circuit between electronic components, and the high operating frequency of electronic components, the electromagnetic interference between electronic components from the outside or inside of electronic products is becoming more and more serious. In order to prevent the mutual interference of electromagnetic waves, various anti-electromagnetic wave interference schemes are developed.
The conventional electromagnetic shielding structure has two main types: one is a single wireless or radio frequency module with a metal cover, which has the disadvantages of low integration level and large volume; another conventional electromagnetic shielding package module structure is mainly manufactured by performing a process of forming a groove on a package body after encapsulation, filling metal, and forming an electromagnetic shielding layer on the surface of a package body by metal sputtering, spraying or other coating methods. The disadvantage of this method is that epoxy resin (epoxy) mixed with 70-75% metal material is used to fill the groove part of the plastic package body during packaging, however, high content of metal is difficult to distribute uniformly in the epoxy resin and is easy to deposit on the bottom of the package layer, forming a layered structure of metal accumulation area and epoxy resin area.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide an integrated circuit packaging structure who contains radio frequency chip, its simple structure to can effectively reduce and crosstalk.
To achieve the purpose, the utility model adopts the following technical proposal:
the integrated circuit packaging structure containing the radio frequency chip prepared by the preparation method comprises the following steps:
the circuit structure comprises a first plastic packaging layer and a circuit structure positioned on one side of the first plastic packaging layer, wherein the circuit structure is provided with a first area and a second area;
the shielding wall is embedded into the first plastic package layer and positioned at the periphery of the first area, and the conductive columns are embedded into the first plastic package layer and distributed in the second area, one end of the shielding wall is connected with the circuit structure, and one end of each conductive column is electrically connected with the circuit structure;
the shielding cover and the third circuit layer are formed by patterning a metal layer and are positioned on one side, far away from the circuit structure, of the first plastic packaging layer, the periphery of the shielding cover is connected with one end, far away from the circuit structure, of the shielding wall, the shielding wall and the shielding cover form a shielding cover, and the third circuit layer is connected with one end, far away from the circuit structure, of the conductive column;
the first chip is a radio frequency chip, the first chip is positioned in the shielding case and electrically connected with the circuit structure, and the second chip is positioned in the second area and electrically connected with the circuit structure;
and the second plastic package layer and the plurality of third chips are positioned on one side of the first plastic package layer, which is far away from the circuit structure, and the third chips are packaged in the second plastic package layer and are electrically connected with the third circuit layer.
The utility model discloses use first copper pad and shielding wall as shielding metal covering around, a shaping shield cover during preparation circuit layer, shield cover and metal covering make up into metal shielding cover, carry out the electromagnetic shield to the radio frequency chip, the signal that has reduced the radio frequency chip is to the crosstalk of other chips.
The utility model discloses in, the integrated circuit packaging structure who contains radio frequency chip still includes solder mask and a plurality of metal convex block, the solder mask is located line structure keeps away from one side of first plastic envelope layer covers line structure, just line structure's pad district expose in the solder mask, it is a plurality of metal convex block weld in line structure's pad district. The electric signal is led out through the metal bump.
In one aspect of the present invention, the circuit structure is a single-layer structure, i.e., a first circuit layer.
Specifically, the first circuit layer is formed by patterning a first seed layer and a metal copper layer on the first seed layer.
In another aspect of the present invention, the circuit structure is a double-layer structure. Specifically, the circuit structure comprises a first circuit layer and a second circuit layer, a dielectric layer extending into the patterned hole structure of the first circuit layer is arranged between the first circuit layer and the second circuit layer, a connecting column is embedded in the dielectric layer, one end of the connecting column is connected with the first circuit layer, the other end of the connecting column is connected with the second circuit layer, the second circuit layer is embedded in the first plastic package layer and is electrically connected with the first chip and the second chip, and one surface of the second circuit layer is flush with one surface of the first plastic package layer; the solder mask layer is positioned on one side, far away from the second circuit layer, of the first circuit layer, and the metal bumps are welded on the pad area of the first circuit layer.
The first circuit layer is formed by patterning a first seed layer and a first metal layer positioned on the first seed layer, and the second circuit layer is formed by patterning a second seed layer and a second metal layer positioned on the second seed layer.
Specifically, the first seed layer has a first patterned hole, the first metal layer has a second patterned hole, and the first patterned hole and the second patterned hole correspond to each other one to one.
Specifically, the second seed layer has third patterned holes, the second metal layer has fourth patterned holes, and the third patterned holes correspond to the fourth patterned holes one to one.
Specifically, the third sublayer has fifth patterned holes, the third metal layer has sixth patterned holes, and the fifth patterned holes correspond to the sixth patterned holes one to one.
The materials of the first seed layer and the second seed layer are conventional in the art, and are not described in detail.
The utility model discloses in, the shielding wall passes through circuit structure ground connection.
The utility model has the advantages that: the utility model discloses use first copper pad and shielding wall around as shielding metal casing, a shaping shield cover during preparation circuit layer, shield cover and metal casing make up into the metal shielding cover, carry out the electromagnetic shield to the radio frequency chip, the signal that has reduced the radio frequency chip is to the crosstalk of other chips, just the utility model discloses an integrated circuit packaging structure is simple.
Drawings
In order to more clearly illustrate the technical solution of the embodiments of the present invention, the drawings required to be used in the embodiments of the present invention will be briefly described below. It is obvious that the drawings described below are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be obtained from these drawings without inventive effort.
Fig. 1 is a flowchart of a method for manufacturing an integrated circuit package structure including a radio frequency chip according to embodiment 1 of the present invention.
Fig. 2 is a schematic cross-sectional view of the temporary bonding adhesive attached to the substrate according to embodiment 1 of the present invention.
Fig. 3 is a schematic cross-sectional view of the first circuit layer prepared on the substrate pasted with the temporary bonding glue according to embodiment 1 of the present invention.
Fig. 4 is a schematic cross-sectional view of the first circuit layer after a dielectric layer is formed thereon according to embodiment 1 of the present invention.
Fig. 5 is a schematic cross-sectional view of the dielectric layer of embodiment 1 after forming via holes to form connecting studs and second circuit layers.
Fig. 6 is a schematic cross-sectional view of the shielding wall, the conductive column, and the first chip and the second chip mounted thereon according to embodiment 1 of the present invention.
Fig. 7 is a schematic cross-sectional view of the first plastic package layer prepared according to embodiment 1 of the present invention.
Fig. 8 is a schematic cross-sectional view of the first plastic-sealed layer after a third circuit layer is formed thereon according to embodiment 1 of the present invention.
Fig. 9 is a schematic cross-sectional view of embodiment 1 after a third chip is mounted on the third circuit layer and is molded.
Fig. 10 is a schematic cross-sectional view of an integrated circuit package structure including a radio frequency chip according to embodiment 1 of the present invention.
Fig. 11 is a schematic top view of fig. 6.
Fig. 12 is a schematic top view of the third chip mounted in embodiment 1 of the present invention.
Fig. 13 is a schematic cross-sectional view of an integrated circuit package structure including a radio frequency chip according to embodiment 2 of the present invention.
In the figure:
1. a substrate; 2. a temporary bonding glue; 3. a first circuit layer; 4. a dielectric layer; 5. a second circuit layer; 6. a first copper pad; 7. a second copper pad; 8. a shielding wall; 9. a conductive post; 10. a first chip; 11. a second chip; 12. a first plastic packaging layer; 13. a shield cover; 14. a third circuit layer; 15. a third chip; 16. a second plastic packaging layer; 17. a solder resist layer; 18. and a metal bump.
Detailed Description
The technical solution of the present invention is further explained by the following embodiments with reference to the accompanying drawings.
Wherein the showings are for the purpose of illustration only and are shown by way of illustration only and not in actual form, and are not to be construed as limiting the present patent; for a better understanding of the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
The same or similar reference numerals in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "inner", "outer", etc. are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, it is only for convenience of description and simplification of description, but it is not indicated or implied that the device or element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and therefore, the terms describing the positional relationship in the drawings are used only for illustrative purposes and are not to be construed as limiting the present patent, and the specific meaning of the terms will be understood by those skilled in the art according to the specific circumstances.
In the description of the present invention, unless otherwise explicitly specified or limited, the term "connected" or the like, if appearing to indicate a connection relationship between the components, is to be understood broadly, for example, as being either a fixed connection, a detachable connection, or an integral part; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or may be connected through one or more other components or may be in an interactive relationship with one another. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Example one
The preparation method of the integrated circuit packaging structure containing the radio frequency chip in the embodiment comprises the following steps:
step 1, providing a substrate 1 made of FR-4 material, and pasting a temporary bonding adhesive 2 on the substrate 1, referring to fig. 2;
step 2, manufacturing a first seed layer on the temporary bonding glue 2 through vacuum sputtering;
step 3, forming a first metal layer on the first seed layer through electroplating;
step 4, pasting a photosensitive film on the first metal layer;
step 5, exposing and developing the photosensitive film to expose part of the first metal layer;
step 6, etching the first metal layer exposed out of the photosensitive film and the first seed layer positioned right below the first metal layer, and removing the residual photosensitive film to obtain a first circuit layer 3, referring to fig. 3;
step 7, fabricating a dielectric layer 4 above the first circuit layer 3, referring to fig. 4;
step 8, opening holes in the dielectric layer 4 to form a hole structure exposing part of the first circuit layer 3;
step 9, manufacturing a second seed layer on the inner wall of the hole structure and the dielectric layer 4 through vacuum sputtering;
step 10, filling metal into the hole structure through electroplating to form a connecting column; and manufacturing a second metal layer on the second seed layer by electroplating;
step 11, pasting a photosensitive film on the second metal layer;
step 12, exposing and developing the photosensitive film to expose part of the second metal layer;
step 13, etching the second metal layer exposed out of the photosensitive film and the second seed layer positioned right below the second metal layer, and removing the residual photosensitive film to obtain a second circuit layer 5; the first circuit layer 3 and the second circuit layer 5 are connected through a connecting column to form a circuit structure, as shown in fig. 5;
step 14, manufacturing a first copper pad 6 which is arranged in a surrounding mode and is in a ring shape around the first area A, and manufacturing a plurality of second copper pads 7 which are arranged at intervals in the second area A; the first copper pad 6 and the second copper pad 7 are simultaneously manufactured by processes such as sputtering, electroplating, film pasting, exposure, developing, etching and the like, and the manufacturing process is the same as the preparation process of the first circuit layer 3, and detailed description is omitted;
step 15, manufacturing a fence-type shielding wall 8 on the first copper pad 6, and enclosing a plurality of shielding walls 8 to form a mounting groove, and manufacturing a conductive pillar 9 on the second copper pad 7 (the manufacturing method is the same as the first circuit layer 3, and details are not repeated), referring to fig. 6;
step 16, providing a first chip 10 and three second chips 11, where the first chip 10 is a Radio Frequency (RF) chip, attaching the first chip 10 to the first area and located in the mounting groove, and attaching the second chips 11 to the second area, as shown in fig. 11;
step 17, performing plastic package on the first chip 10, the second chip 11, the shielding wall 8 and the conductive post 9 by using an epoxy plastic package material to form a first plastic package layer 12, referring to fig. 7;
step 18, thinning the first plastic package layer 12 to expose the upper ends of the conductive post 9 and the shielding wall 8;
step 19, manufacturing a third sub-layer on the first plastic packaging layer 12 through vacuum sputtering;
step 20, manufacturing a third metal layer on the third sub-layer through electroplating;
step 21, pasting a photosensitive film on the third metal layer;
step 22, exposing and developing the photosensitive film to expose part of the third metal layer;
step 23, performing etching treatment on the third metal layer exposed out of the photosensitive film and the third sub-layer located right below the third metal layer, and removing the residual photosensitive film to obtain a shielding cover 13 connected to the upper end of the shielding wall 8 and covering the mounting groove and a third circuit layer 14 connected to the upper end of the conductive post 9, referring to fig. 8, where the shielding wall 8 and the shielding cover 13 constitute a shielding enclosure;
step 24, providing a plurality of third chips 15, and attaching the third chips 15 to the third circuit layer 14, referring to fig. 12;
step 25 of performing plastic packaging on the third chip 15 to form a second plastic packaging layer 16 covering the shielding cover and the third chip 15, referring to fig. 9;
step 26, bonding is disassembled to expose the first circuit layer 3;
step 27, brushing solder resist ink on the first circuit layer 3, forming a solder resist layer 17 after curing, and exposing and developing the solder resist layer 17 to expose a pad area of the first circuit layer 3;
step 28, providing a plurality of solder balls (metal bumps 18), and soldering the solder balls to the pad regions of the first circuit layer 3, referring to fig. 10.
In the present embodiment, the metal bump 18 is not limited to a solder ball, and is also applicable to other metal materials commonly used in the art. The shape of the metal bump 18 is not limited to a spherical shape, and the same applies to a square or ellipsoidal lamp.
The substrate 1 in this embodiment is not limited to FR-4 material, but may be a conventional chip packaging carrier such as a glass substrate.
Fig. 10 shows an integrated circuit package structure including a radio frequency chip manufactured by the method of this embodiment, which includes:
the circuit structure comprises a first plastic packaging layer 12 and a circuit structure positioned on one side of the first plastic packaging layer 12, wherein the circuit structure is provided with a first area and a second area;
the shielding wall 8 is embedded into the first plastic package layer 12 and located around the first region, and the conductive pillars 9 are embedded into the first plastic package layer 12 and distributed in the second region, one end of the shielding wall 8 is connected with the circuit structure, and one end of the conductive pillar 9 is electrically connected with the circuit structure;
a shielding cover 13 and a third circuit layer 14, which are formed by patterning a metal layer, are located on one side of the first plastic package layer 12, which is far away from the circuit structure, the periphery of the shielding cover 13 is connected with one end, which is far away from the circuit structure, of the shielding wall 8, the shielding wall 8 and the shielding cover 13 form a shielding cover, and the third circuit layer 14 is connected with one end, which is far away from the circuit structure, of the conductive column 9;
at least one first chip 10 and a plurality of second chips 11 encapsulated in the first plastic package layer 12, wherein the first chip 10 is a radio frequency chip, the first chip 10 is located in the shielding case and electrically connected to the circuit structure, and the second chip 11 is located in the second region and electrically connected to the circuit structure;
the circuit structure comprises a second plastic package layer 16 and a plurality of third chips 15, wherein the second plastic package layer 16 and the plurality of third chips 15 are positioned on one side, far away from the circuit structure, of the first plastic package layer 12, and the third chips 15 are packaged in the second plastic package layer 16 and are electrically connected with the third circuit layer 14.
Specifically, still include solder mask 17 and a plurality of metal bump 18, solder mask 17 is located the circuit structure is kept away from one side of first plastic-sealed layer 12 and is covered the circuit structure, just the pad area of circuit structure expose in solder mask 17, it is a plurality of metal bump 18 weld in the pad area of circuit structure.
Wherein, the circuit structure is a double-layer structure. Specifically, the circuit structure comprises a first circuit layer 3 and a second circuit layer 5, a dielectric layer 4 extending into a patterned hole structure of the first circuit layer 3 is arranged between the first circuit layer 3 and the second circuit layer 5, a connecting column is embedded in the dielectric layer 4, one end of the connecting column is connected with the first circuit layer 3, the other end of the connecting column is connected with the second circuit layer 5, the second circuit layer 5 is embedded into the first plastic package layer 12 and is electrically connected with the first chip 10 and the second chip 11, and one surface of the second circuit layer 5 is flush with one surface of the first plastic package layer 12; the solder mask layer 17 is located on one side of the first circuit layer 3 away from the second circuit layer 5, and the metal bumps 18 are soldered to the pad area of the first circuit layer 3.
Further, the first wiring layer 3 is composed of a first seed layer and a first metal layer which are respectively patterned. Wherein, one surface of the first seed layer is flush with one surface of the dielectric layer 4, and the first metal layer is located on the other surface of the first seed layer and connected with one end of the connection post.
Specifically, the first seed layer has first patterned holes, the first metal layer has second patterned holes, and the first patterned holes correspond to the second patterned holes one to one.
Further, the second wiring layer 5 is composed of a second seed layer and a second metal layer which are respectively patterned. Wherein, the second seed layer is located on the dielectric layer 4, and a surface of the second seed layer contacting the dielectric layer 4 is flush with a surface of the first molding compound layer 12, and the second metal layer is located on the second seed layer and connected with the first chip 10 and the second chip 11, and the first copper pad 6 and the second copper pad 7.
Specifically, the second seed layer has third patterned holes, the second metal layer has fourth patterned holes, and the third patterned holes correspond to the fourth patterned holes one to one.
Further, the third wiring layer 14 is composed of a third sub-layer and a third metal layer which are patterned respectively.
Specifically, the third sublayer has fifth patterned holes, the third metal layer has sixth patterned holes, and the fifth patterned holes correspond to the sixth patterned holes one to one.
In other specific embodiments, the third circuit layer 14 is a patterned third metal layer, that is, a third sub-layer is not required, and a stable electrical connection with the conductive pillar 9 can also be achieved.
Example two
This example is substantially the same as the above examples except for the method of manufacturing the wiring structure.
The method for manufacturing the circuit structure of this embodiment is a method for manufacturing the first circuit layer, and compared with embodiment 1, steps 7 to 13 are omitted, and detailed description is omitted.
Correspondingly, the structure of the integrated circuit package containing the rf chip is shown in fig. 13. Compared with the integrated circuit package structure including the radio frequency chip manufactured in embodiment 1, the circuit structure is a single-layer structure, i.e., the first circuit layer 3, and the dielectric layer 4 and the second circuit layer 5 are omitted, which is not described in detail.
Of course, in other embodiments, three or more layers of circuit structures may be fabricated according to actual requirements.
It should be understood that the above-described embodiments are only preferred embodiments of the present invention and the technical principles applied thereto. It will be understood by those skilled in the art that various modifications, equivalents, changes, and the like can be made to the present invention. However, these modifications are within the scope of the present invention as long as they do not depart from the spirit of the present invention. In addition, certain terms used in the specification and claims of the present application are not limiting, but are used merely for convenience of description.

Claims (4)

1. An integrated circuit package structure including a radio frequency chip, comprising:
the circuit structure comprises a first plastic packaging layer and a circuit structure positioned on one side of the first plastic packaging layer, wherein the circuit structure is provided with a first area and a second area;
the shielding wall is embedded into the first plastic package layer and positioned around the first area, and one end of the shielding wall is connected with the circuit structure;
the plurality of conductive columns are embedded into the first plastic package layer and distributed in the second area, and one ends of the conductive columns are electrically connected with the circuit structure;
the shielding cover and the third circuit layer are formed by patterning a metal layer and are positioned on one side, far away from the circuit structure, of the first plastic packaging layer, the periphery of the shielding cover is connected with one end, far away from the circuit structure, of the shielding wall, the shielding wall and the shielding cover form a shielding cover, and the third circuit layer is connected with one end, far away from the circuit structure, of the conductive column;
the first chip is a radio frequency chip, the first chip is positioned in the shielding case and electrically connected with the circuit structure, and the second chip is positioned in the second area and electrically connected with the circuit structure;
and the second plastic package layer and the plurality of third chips are positioned on one side of the first plastic package layer, which is far away from the circuit structure, and the third chips are packaged in the second plastic package layer and are electrically connected with the third circuit layer.
2. The integrated circuit package structure with the radio frequency chip according to claim 1, further comprising a solder mask layer and a plurality of metal bumps, wherein the solder mask layer is disposed on a side of the circuit structure away from the first plastic package layer and covers the circuit structure, a pad region of the circuit structure is exposed from the solder mask layer, and the plurality of metal bumps are soldered to the pad region of the circuit structure.
3. The package structure of claim 2, wherein the circuit structure is a single layer structure, i.e. the first circuit layer.
4. The integrated circuit package structure with the radio frequency chip according to claim 2, wherein the circuit structure is a double-layer structure including a first circuit layer and a second circuit layer, a dielectric layer extending into the patterned hole structure of the first circuit layer is disposed between the first circuit layer and the second circuit layer, a connection post is embedded in the dielectric layer, one end of the connection post is connected to the first circuit layer, the other end of the connection post is connected to the second circuit layer, the second circuit layer is embedded in the first plastic package layer and electrically connected to the first chip and the second chip, and a surface of the second circuit layer is flush with a surface of the first plastic package layer; the solder mask layer is positioned on one side, far away from the second circuit layer, of the first circuit layer, and the metal bumps are welded on the pad area of the first circuit layer.
CN202220899745.6U 2022-04-18 2022-04-18 Integrated circuit packaging structure containing radio frequency chip Active CN217306496U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202220899745.6U CN217306496U (en) 2022-04-18 2022-04-18 Integrated circuit packaging structure containing radio frequency chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202220899745.6U CN217306496U (en) 2022-04-18 2022-04-18 Integrated circuit packaging structure containing radio frequency chip

Publications (1)

Publication Number Publication Date
CN217306496U true CN217306496U (en) 2022-08-26

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