CN216981778U - Semiconductor circuit with hysteresis function - Google Patents

Abstract

The utility model relates to a semiconductor circuit with hysteresis function, comprising a high-voltage integrated circuit and a switch tube; the high-voltage integrated circuit comprises a driving circuit, an overcurrent protection circuit and a fault logic control circuit, wherein the overcurrent protection circuit comprises a first comparator, a first resistor, a second resistor, a third resistor, a fourth resistor, a reference power supply and an auxiliary power supply; a first input port of the first comparator is an overcurrent detection signal input end, the first input port of the first comparator is grounded through a fourth resistor, the first input port is also connected to an auxiliary power supply through a third resistor, and a second input port of the first comparator is connected to a reference power supply; the output port of the first comparator is connected to the first input port of the first comparator through the second resistor, and the output port of the first comparator is connected to the auxiliary power supply through the first resistor and is also connected to the fault logic control circuit. The circuit can improve the anti-interference capability of overcurrent protection and improve the stability and reliability of circuit operation.

Description

Semiconductor circuit with hysteresis function

Technical Field

The utility model relates to a semiconductor circuit with hysteresis function, belonging to the technical field of semiconductor circuit application.

Background

Semiconductor circuits are a Power-driven class of products that combine Power electronics with integrated circuit technology, also known as Intelligent Power Modules (IPMs). The smart power module integrates a power switching device and an HVIC (High Voltage Integrated Circuit), and incorporates a fault detection Circuit such as an overvoltage, overcurrent, and overheat. The intelligent power module can drive a subsequent circuit to work by receiving a control signal of the MCU on one hand, and can feed back a state detection signal of the system to the MCU on the other hand. Compared with the traditional scheme of separation arrangement, the intelligent power module gains a bigger and bigger market with the advantages of high integration level, high reliability and the like, is particularly suitable for a frequency converter of a driving motor and various inverter power supplies, and is an ideal power electronic device for frequency conversion speed regulation, metallurgical machinery, electric traction, servo drive and frequency conversion household appliances.

In the related art, an overcurrent protection circuit, such as an ITRIP/PFCITRIP circuit, is integrated inside a high-voltage integrated circuit, and when various overcurrent conditions occur, the overcurrent protection circuit can output a related protection signal to a fault logic control circuit, so that an external processor receives the fault signal and timely acts to stop the operation of the circuit, and the safety and reliability of the circuit are improved. However, under a complex working environment, for example, in a low-temperature, high-temperature, low-frequency, high-frequency mode, etc., the ITRIP/PFCITRIP circuit protection function is easily triggered by mistake, and particularly, during a signal transmission process, the ITRIP/PFCITRIP circuit protection function is easily interfered by signals, so that a semiconductor circuit module stops working, normal operation of a product is affected, and application is troublesome.

In summary, there is a need to solve the technical problems in the related art.

SUMMERY OF THE UTILITY MODEL

The utility model aims to solve a series of problems that an overcurrent protection circuit in the existing semiconductor circuit is easily interfered by signals, so that a semiconductor circuit module stops working and normal operation of a product is influenced.

Specifically, the present invention discloses a semiconductor circuit having a hysteresis function, including:

a high-voltage integrated circuit and a switching tube; the high-voltage integrated circuit comprises a driving circuit, an overcurrent protection circuit and a fault logic control circuit, and the driving circuit is connected with the switching tube;

the overcurrent protection circuit comprises a first comparator, a first resistor, a second resistor, a third resistor, a fourth resistor, a reference power supply and an auxiliary power supply; the first input port of the first comparator is an overcurrent detection signal input end of the overcurrent protection circuit, the first input port of the first comparator is grounded through the fourth resistor, the first input port of the first comparator is also connected to the auxiliary power supply through the third resistor, and the second input port of the first comparator is connected to the reference power supply; the output port of the first comparator is connected to the first input port of the first comparator through the second resistor, the output port of the first comparator is connected to the auxiliary power supply through the first resistor, and the output port of the first comparator is further connected to the fault logic control circuit.

Optionally, the driving circuit includes a high-voltage side driving circuit and a low-voltage side driving circuit, and the high-voltage side driving circuit and the low-voltage side driving circuit are connected.

Optionally, the high-voltage side driving circuit includes three identical high-voltage driving units, and each high-voltage driving unit includes an upper bridge arm signal input end, two high-voltage side power supply ends, and a high-voltage side control output end; the high-voltage side control output end is used for outputting a driving signal for driving the upper bridge arm switching tube of one phase.

Optionally, the high voltage driving unit includes a first schmitt trigger, a first filter circuit, a first potential shift circuit, a first dead zone interlocking unit, a pulse generating circuit, a DV/DT filter circuit, a latch, a nor gate, a UV filter circuit, a first MOS transistor, a second MOS transistor, a first current limiting resistor, a second current limiting resistor, and a first output driving circuit;

the input end of the first Schmitt trigger is the upper bridge arm signal input end, and the output end of the first Schmitt trigger is connected with the input end of the first filter circuit; the output end of the first filter circuit is connected with the input end of the first potential displacement circuit; the output end of the potential displacement circuit is connected with the input end of the first dead zone interlocking unit; the output end of the first dead zone interlocking unit is connected with the input end of the pulse generating circuit; the output end of the pulse generating circuit is connected with the grids of the first MOS tube and the second MOS tube, the drains of the first MOS tube and the second MOS tube are connected with the input end of the DV/DT filter circuit, the drain of the first MOS tube is connected to the positive end of the high-voltage side power supply end through the first current limiting resistor, and the drain of the second MOS tube is connected to the positive end of the high-voltage side power supply end through the second current limiting resistor; the output end of the DV/DT filter circuit is connected with the first input end of the latch, and the output end of the UV filter circuit is connected with the second input end of the latch; the output end of the DV/DT filter circuit is connected with the first input end of the NOR logic gate, and the output end of the latch is connected with the second input end of the NOR logic gate; the output end of the NOR logic gate is connected to the input end of the first output driving circuit.

Optionally, the first output driving circuit includes:

a third MOS transistor and a fourth MOS transistor;

the grid of third MOS pipe with the grid of fourth MOS pipe connect in the input of first output drive circuit, the drain electrode of third MOS pipe is connected the positive terminal of high pressure side feed end, the source electrode of third MOS pipe with the drain electrode of fourth MOS pipe connect in the output of first output drive circuit altogether, the source electrode of fourth MOS pipe connect in the negative pole end of high pressure side feed end.

Optionally, the low-voltage side driving circuit includes three identical low-voltage driving units, and each low-voltage driving unit includes a lower bridge arm signal input end, a low-voltage side power supply end, a low-voltage reference end, and a low-voltage side control output end; the low-voltage side control output end is used for outputting a driving signal for driving a one-phase lower bridge arm switching tube.

Optionally, the low-voltage driving unit includes a second schmitt trigger, a second filter circuit, a second potential displacement circuit, a second dead zone interlocking unit, a delay circuit, a second comparator, and a second output driving circuit;

the input end of the second Schmitt trigger is the lower bridge arm signal input end, and the output end of the second Schmitt trigger is connected with the input end of the second filter circuit; the output end of the second filter circuit is connected with the input end of the second potential displacement circuit; the output end of the second potential displacement circuit is connected with the input end of the second dead zone interlocking unit; the output end of the second dead zone interlocking unit is connected with the input end of the delay circuit; the output ends of the pulse generating circuit and the delay circuit are connected with the input end of the second comparator, and the output end of the second comparator is connected with the input end of the second output driving circuit.

Optionally, the second output driving circuit comprises:

a fifth MOS transistor and a sixth MOS transistor;

the grid electrode of the fifth MOS tube and the grid electrode of the sixth MOS tube are connected to the input end of the second output driving circuit in a sharing mode, the drain electrode of the fifth MOS tube is connected with the low-voltage side power supply end, the source electrode of the fifth MOS tube and the drain electrode of the sixth MOS tube are connected to the output end of the second output driving circuit in a sharing mode, and the source electrode of the sixth MOS tube is grounded.

Optionally, the overcurrent protection circuit further includes a delay circuit, a signal memory, a logic or gate circuit, and an NMOS transistor;

the output end of the first comparator is connected with the input end of the delay circuit, the output end of the delay circuit is connected with the input end of the signal memory, the output end of the signal memory is connected to one input end of the logic OR gate circuit, the output end of the logic OR gate circuit is connected to the grid electrode of the NMOS tube, the source electrode of the NMOS tube is grounded, and the drain electrode of the NMOS tube is connected with the fault signal output end.

Optionally, the first input port of the first comparator is a positive input port, and the second input port of the first comparator is a negative input port.

The utility model relates to a semiconductor circuit with hysteresis function, which comprises a high-voltage integrated circuit and a switching tube; the high-voltage integrated circuit comprises a driving circuit, an overcurrent protection circuit and a fault logic control circuit, and the driving circuit is connected with the switching tube; the overcurrent protection circuit comprises a first comparator, a first resistor, a second resistor, a third resistor, a fourth resistor, a reference power supply and an auxiliary power supply; a first input port of the first comparator is an overcurrent detection signal input port of the overcurrent protection circuit, the first input port of the first comparator is grounded through the fourth resistor, the first input port of the first comparator is also connected to the auxiliary power supply through the third resistor, and a second input port of the first comparator is connected to the reference power supply; the output port of the first comparator is connected to the first input port of the first comparator through the second resistor, the output port of the first comparator is connected to the auxiliary power supply through the first resistor, and the output port of the first comparator is further connected to the fault logic control circuit. The semiconductor circuit provided by the utility model can improve the anti-interference capability of the overcurrent protection circuit, thereby improving the overall anti-interference performance of the circuit and improving the stability and reliability of the circuit.

Drawings

FIG. 1 is a schematic diagram of an interface of a semiconductor circuit according to an embodiment of the present invention;

FIG. 2 is a simplified circuit schematic of a semiconductor circuit according to an embodiment of the present invention;

FIG. 3 is a schematic circuit diagram of a driving circuit according to an embodiment of the present invention;

fig. 4 is a schematic circuit diagram of an overcurrent protection circuit according to an embodiment of the present invention.

Detailed Description

It is to be noted that the embodiments and features of the embodiments may be combined with each other without conflict in structure or function. The present invention will be described in detail below with reference to examples.

The semiconductor circuit provided by the utility model is a circuit module which integrates a power switch device, a high-voltage driving circuit and the like together and is sealed and packaged on the outer surface, and is widely applied to the field of power electronics, such as the fields of frequency converters of driving motors, various inversion voltages, variable frequency speed regulation, metallurgical machinery, electric traction, variable frequency household appliances and the like. The semiconductor circuit herein may be referred to by various other names, such as Modular Intelligent Power System (MIPS), Intelligent Power Module (IPM), or hybrid integrated circuit, Power semiconductor Module, Power Module, etc.

With reference to fig. 1, first, the respective interface functions of a semiconductor circuit proposed in the present application will be described with reference to fig. 1. The semiconductor Circuit includes an HVIC (High Voltage Integrated Circuit) chip, a power supply terminal VCC of the HVIC chip can be used as a low-Voltage side power supply positive terminal VDD of the semiconductor Circuit, a Voltage at the VDD is generally 15V, and the HVIC chip generally includes six signal input terminals for receiving upper and lower bridge arm PWM control signals output by the peripheral main control board. The first upper bridge arm signal input end HIN1, the second upper bridge arm signal input end HIN2 and the third upper bridge arm signal input end HIN3 can be respectively used as a U-phase upper bridge arm signal input end UHIN, a V-phase upper bridge arm signal input end VHIN and a W-phase upper bridge arm signal input end WHIN of the semiconductor circuit; similarly, the first lower leg signal input terminal LIN1, the second lower leg signal input terminal LIN2, and the third lower leg signal input terminal LIN3 of the HVIC chip may be respectively used as the U-phase lower leg signal input terminal ULIN, the V-phase lower leg signal input terminal VLIN, and the W-phase lower leg signal input terminal WLIN of the semiconductor circuit. Generally, the voltage ranges of input signals of a first upper bridge arm signal input end HIN1, a second upper bridge arm signal input end HIN2, a third upper bridge arm signal input end HIN3, a first lower bridge arm signal input end LIN1, a second lower bridge arm signal input end LIN2 and a third lower bridge arm signal input end LIN3 of the semiconductor circuit can be 0-5V; a grounding end GND of the HVIC chip is used as a low-voltage side power supply negative end COM of the semiconductor circuit; a first power supply positive end VB1 of the HVIC chip is used as a positive end UVB of a U-phase high-voltage side power supply end of the semiconductor circuit, a high-voltage side control output end HO1 of the HVIC chip is used for outputting a driving signal for driving a U-phase upper bridge arm switching tube, a first power supply negative end VS1 of the HVIC chip is used as a negative end UVS of the U-phase high-voltage side power supply end of the semiconductor circuit, and a filter capacitor can be connected between the positive end UVB of the U-phase high-voltage side power supply end of the semiconductor circuit and the negative end UVS of the U-phase high-voltage side power supply end; a second power supply positive end VB2 of the HVIC chip is used as a positive end VVB of a V-phase high-voltage side power supply end of the semiconductor circuit, a high-voltage side control output end HO2 of the HVIC chip is used for outputting a driving signal for driving a V-phase upper bridge arm switching tube, a second power supply negative end VS2 of the HVIC chip is used as a negative end VVS of the V-phase high-voltage side power supply end of the semiconductor circuit, and a filter capacitor can be connected between the positive end VVB of the V-phase high-voltage side power supply end of the semiconductor circuit and the negative end VVS of the V-phase high-voltage side power supply end; the third power supply positive terminal VB3 of the HVIC chip is used as the positive terminal WVB of the W-phase high-voltage side power supply terminal of the semiconductor circuit, the high-voltage side control output terminal HO3 of the HVIC chip is used for outputting a driving signal for driving the W-phase upper arm switching tube, the third power supply negative terminal VS3 of the HVIC chip is used as the negative terminal WVS of the W-phase high-voltage side power supply terminal of the semiconductor circuit, and the filter capacitor can be connected between the positive terminal WVB of the W-phase high-voltage side power supply terminal of the semiconductor circuit and the negative terminal WVS of the W-phase high-voltage side power supply terminal. The semiconductor circuit also comprises a U-phase low-voltage reference end UN, a V-phase low-voltage reference end VN and a W-phase low-voltage reference end WN; the high voltage input of a semiconductor circuit is typically connected to 300V.

The HVIC chip is used for transmitting 0-5V logic signals received by the HIN1, the HIN2, the HIN3, the LIN1, the LIN2 and the LIN3 to the HO1, the HO2, the HO3, the LO1, the LO2 and the LO3 respectively so as to control the work of the switch tube assembly and achieve the driving purpose. The HO1, HO2 and HO3 output logic signals of VS-VS +15V, and the LO1, LO2 and LO3 output logic signals of 0-15V; input signals of the same phase cannot be at high level at the same time, that is, input signals of the first upper bridge arm signal input end HIN1 and the first lower bridge arm signal input end LIN1 cannot be at high level at the same time, input signals of the second upper bridge arm signal input end HIN2 and the second lower bridge arm signal input end LIN2 cannot be at high level at the same time, and input signals of the third upper bridge arm signal input end HIN3 and the third lower bridge arm signal input end LIN3 cannot be at high level at the same time.

Next, a semiconductor circuit with hysteresis function according to the present invention is described, and as shown in fig. 2, a semiconductor circuit 33 according to the present invention includes a high voltage integrated circuit 10 and a switching tube 56, where the high voltage integrated circuit 10 includes a driving circuit, an overcurrent protection circuit, and a fault logic control circuit 16, and the driving circuit is connected to the switching tube 56.

More specifically, the high-voltage integrated circuit 10 provided by the present application may further include a buffer circuit 11, where the buffer circuit 11 is configured to receive the PWM control signals of the upper and lower bridge arms output by the peripheral main control board, and after receiving the PWM control signal of the corresponding MCU, the PWM control signal may be filtered, amplified, and output to a subsequent driving circuit, so as to implement a relatively stable signal receiving operation and improve driving stability.

In this embodiment, the driving circuit of the high-voltage integrated circuit 10 may include an upper bridge arm driving circuit 100 and a lower bridge arm driving circuit 13, where the upper bridge arm driving circuit 100 may include a bootstrap circuit, a high-voltage side under-voltage protection circuit, and three identical high-voltage driving units. Each high-voltage driving unit comprises an upper bridge arm signal input end for receiving an upper bridge arm PWM control signal output by the peripheral main control board, wherein the signal can be a signal preprocessed by the cache circuit 11, and a high-voltage side control output end for outputting a driving signal for driving a phase of upper bridge arm switching tube to a three-phase upper bridge arm switching tube. Similarly, the lower bridge arm driving circuit 13 may include three identical low-voltage driving units, each low-voltage driving unit includes a lower bridge arm signal input end for receiving a lower bridge arm PWM control signal output by the peripheral main control board, the signal may also be a signal preprocessed by the cache circuit 11, and each low-voltage driving unit further includes a low-voltage side control output end for outputting one driving signal for driving the one-phase lower bridge arm switching tube to the three-phase lower bridge arm switching tube. It is understood that the high-side driving circuit of the driving circuit may be powered by high-voltage direct current, and the low-side driving circuit may be powered by low-voltage direct current, and the specific voltage class is not limited herein.

In the semiconductor circuit in the embodiment of the application, the driving circuit is divided into a high-voltage side driving circuit and a low-voltage side driving circuit to respectively output driving signals to drive the upper bridge arm switching tube and the lower bridge arm switching tube to work, so that the purpose of driving the motor is achieved. The high-voltage side driving circuit and the low-voltage side driving circuit can be supplied with power by adopting independent high-voltage direct current and low-voltage direct current respectively, and can transmit multi-path pulse signals to drive the switching tube to work respectively, so that the problem that false triggering action is caused by the fact that the low-voltage side driving circuit easily receives interference of current in the high-voltage side driving circuit can be effectively avoided, and meanwhile, the design of each part in the driving circuit can be independently built, so that the overall complexity is reduced, the working reliability of the driving circuit can be improved, and the cost is reduced.

In some embodiments, the high-voltage integrated circuit 10 of the present application may further include an over-temperature protection circuit, a short-circuit protection circuit, and a control voltage under-voltage protection circuit, and specific structures of these circuits may be implemented with reference to the prior art, which is not described herein again.

In the embodiment of the application, simultaneously, functions such as undervoltage protection, over-temperature protection, overcurrent protection and short-circuit protection are arranged in the high-voltage integrated circuit 10, so that actions such as upper and lower bridge interlocking and power signal cut-off can be realized when a working process of the circuit breaks down, burning of a product is avoided, and the stability and reliability of circuit operation are ensured. Specifically, the protection circuits described above may be integrated in the working protection circuit 14, and when the circuit detects a certain FAULT, the circuit may feed back a signal to the peripheral main control board, for example, the FAULT signal may be converted from a high level to a low level, so that a corresponding action may be immediately taken to achieve the function of the protection circuit. In some embodiments, when the peripheral main control board performs the protection action, the semiconductor circuit 33 may be protected based on the driving enable circuit 15, the driving enable circuit 15 may be set to be active at a high level and is responsible for turning on and turning off the semiconductor circuit 33, and when the peripheral main control board monitors the FAULT signal transmitted by the working protection circuit 14 through the FAULT logic control circuit 16, the peripheral main control board may output a corresponding control signal to enable the driving enable circuit 15 to maintain a low level state, and turn off the power supply of the semiconductor circuit 33, so as to protect the entire semiconductor circuit from the accidents of fire and damage due to overcurrent, overheat, short circuit, and other factors; when the failure is cleared or resolved by the troubleshooting, the drive enable circuit 15 may restore the high level state again, and the semiconductor circuit 33 is powered on to re-enter the operation preparation state.

Referring to fig. 2, the semiconductor circuit 33 in fig. 2, internally integrates six three-phase full-bridge driving, and the driving output is realized through the working states of six switching tubes, the semiconductor circuit 33 is loaded with low-voltage direct current VCC (which may be 15V voltage generally) and high-voltage direct current, the positive terminal of the high-voltage direct current comprises three ports VB1 to VB3, and the negative terminal comprises three ports VS1 to VS3 (which may be 300-315V voltage generally). The driving circuit is divided into a high-voltage side driving circuit 100 and a low-voltage side driving circuit 13 in fig. 2, so as to respectively drive the three switching tubes Q1-Q3 of the upper bridge arm and the three switching tubes Q4-Q6 of the lower bridge arm to work.

Referring to fig. 3, in the high-side driving circuit 100, each of the high-voltage driving units includes a first schmitt trigger 300, a first filter circuit 301, a first potential shift circuit 302, a first dead zone interlock unit, a pulse generation circuit 304, a DV/DT filter circuit 305, a latch 306, a nor gate 307, a UV filter circuit 311, a first MOS transistor, a second MOS transistor, a first current limiting resistor RS1, a second current limiting resistor RS2, and a first output driving circuit; the first dead zone interlock unit includes a first nand logic gate 303 and a second nand logic gate 308;

the input end of the first schmitt trigger 300 is the upper bridge arm signal input end, and the output end of the first schmitt trigger 300 is connected with the input end of the first filter circuit 301; the output end of the first filter circuit 301 is connected with the input end of the first potential displacement circuit 302; an output end of the first potential shift circuit 302 is connected with a first input terminal of the first nand logic gate 303, an output end of the first potential shift circuit 302 is connected with a first input terminal of the second nand logic gate 308, and an output end of the second nand logic gate 308 is connected with a second input terminal of the first nand logic gate 303; the output end of the first nand logic gate 303 is connected with the input end of the pulse generation circuit 304; the output end of the pulse generating circuit 304 is connected to the gates of the first and second MOS transistors, the drains of the first and second MOS transistors are connected to the input end of the DV/DT filter circuit 305, the drain of the first MOS transistor is connected to the positive terminal of the high-voltage power supply end through the first current limiting resistor RS1, and the drain of the second MOS transistor is connected to the positive terminal of the high-voltage power supply end through the second current limiting resistor RS 2; an output terminal of the DV/DT filter circuit 305 is coupled to a first input terminal of the latch 306, and an output terminal of the UV filter circuit 311 is coupled to a second input terminal of the latch 306; the output of the DV/DT filter circuit 305 is connected to a first input of the nor logic gate 307, and the output of the latch 306 is connected to a second input of the nor logic gate 307; the output of the nor logic gate 307 is connected to the input of the first output driver circuit.

In the embodiment of the present invention, the first schmitt trigger 300 is configured to filter a PWM control signal output by the peripheral main control board, and then stably output the PWM control signal to the first filtering circuit 301 in the subsequent stage, where the first filtering circuit 301 is configured to perform high-frequency and narrow-wave filtering on the received control signal, invert the control signal, and output the control signal to the first potential displacement circuit 302. When the amplitude of the coupled signal is large, the dc variation may interfere with the interface voltage, and the first level shift circuit 302 is configured to compensate the coupled signal accordingly and add a dc level adjustment function, so as to realize stable output of the signal to the first dead zone interlock unit. The pulse generating circuit 304 is configured to output a high-level signal output by the output end of the first nand logic gate 303 to gates of the first MOS transistor and the second MOS transistor for driving conduction, the gate and the source of the MOS transistor are short-circuited to realize unidirectional conduction, and a voltage is output to the positive terminal VB of the high-voltage-side power supply end through the first bootstrap resistor RS1 and the second bootstrap resistor RS 2; the DV/DT filter circuit 305 is configured to receive drain voltages of the first MOS transistor and the second MOS transistor, perform filtering rectification, and stabilize the voltage; the UV filter circuit 311 receives the level signal divided by the bootstrap resistor to perform filtering rectification; the latch 306 is used for receiving signals of the DV/DT filter circuit 305 and the UV filter circuit 311 for temporary storage, and finally enabling level signal output to be synchronous; the nor logic gate 307 is used for receiving the latch 306 signal, and comparing the input high and low levels, thereby controlling the driving turn-on condition of the MOS transistor in the first output driving circuit.

In some embodiments of the present invention, the first output driver circuit comprises:

a third MOS transistor and a fourth MOS transistor; the grid of third MOS pipe with the grid of fourth MOS pipe connect in the input of first output drive circuit, the drain electrode of third MOS pipe is connected the positive terminal of high pressure side feed end, the source electrode of third MOS pipe with the drain electrode of fourth MOS pipe connect in the output of first output drive circuit altogether, the source electrode of fourth MOS pipe connect in the negative pole end of high pressure side feed end.

In the embodiment of the present application, in the low-voltage side driving circuit, the low-voltage side driving unit includes a second schmitt trigger 312, a second filter circuit 313, a second potential displacement circuit 314, a second dead zone interlocking unit, a delay circuit 310, a second comparator 315, and a second output driving circuit; the second deadband interlock unit comprises a third nand logic gate 309;

the input end of the second schmitt trigger 312 is the lower bridge arm signal input end, and the output end of the second schmitt trigger 312 is connected with the input end of the second filter circuit 313; the output end of the second filter circuit 313 is connected with the input end of the second potential displacement circuit 314; an output end of the second potential shift circuit 314 is connected to a second input terminal of the third nand logic gate 309, an output end of the second potential shift circuit 314 is connected to a second input terminal of the second nand logic gate 308, and an output end of the second nand logic gate 308 is connected to a first input terminal of the third nand logic gate 309; the output terminal of the third nand logic gate 309 is connected to the input terminal of the delay circuit 310; the output terminals of the pulse generating circuit 304 and the delay circuit 310 are connected to the input terminal of the second comparator 315, and the output terminal of the second comparator 315 is connected to the input terminal of the second output driving circuit.

In some embodiments, the second output driving circuit includes:

a fifth MOS transistor and a sixth MOS transistor;

the grid electrode of the fifth MOS tube and the grid electrode of the sixth MOS tube are connected to the input end of the second output driving circuit in a sharing mode, the drain electrode of the fifth MOS tube is connected with the low-voltage side power supply end, the source electrode of the fifth MOS tube and the drain electrode of the sixth MOS tube are connected to the output end of the second output driving circuit in a sharing mode, and the source electrode of the sixth MOS tube is grounded.

In this embodiment, the second schmitt trigger 312 is configured to filter the PWM control signal output by the peripheral main control board and then stably output the filtered PWM control signal to the second filter circuit 313 in the subsequent stage, and the second filter circuit 313 is configured to perform high-frequency and narrow-wave filtering on the received control signal, invert the control signal, output the control signal to the second potential displacement circuit 314, and output the control signal to the second dead-zone interlocking unit. The delay unit is used for outputting the control signal output by the second dead zone interlocking unit in a delay way so as to avoid short-circuit faults of the power inverter bridge circuit caused by the fact that the lower bridge arm power tube and the upper bridge arm power tube of the high-voltage side driving circuit are conducted simultaneously.

Referring to fig. 4, in the embodiment of the present application, the overcurrent protection circuit includes a first comparator 104, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a reference power supply REF, and an auxiliary power supply Vcc; the first input port of the first comparator 104 is an overcurrent detection signal input end of the overcurrent protection circuit, the first input port of the first comparator 104 is grounded through the fourth resistor R4, the first input port of the first comparator 104 is further connected to the auxiliary power supply Vcc through the third resistor R3, and the second input port of the first comparator 104 is connected to the reference power supply REF; the output port of the first comparator 104 is connected to the first input port of the first comparator 104 through the second resistor R2, the output port of the first comparator 104 is connected to the auxiliary power supply Vcc through the first resistor R1, and the output port of the first comparator 104 is further connected to the fault logic control circuit.

In the embodiment of the present application, an overcurrent protection circuit with a hysteresis function is provided, and this hysteresis circuit can avoid the oscillation output of the first comparator 104 caused by the parasitic feedback of the input terminal, improve the anti-interference capability of the overcurrent protection circuit, and then can improve the overall anti-interference performance of the circuit, and improve the work efficiency of the product.

Specifically, in the embodiment of the present application, the overcurrent protection circuit includes a first comparator 104, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a reference power supply REF, and an auxiliary power supply Vcc, where a first input port of the first comparator 104 is an overcurrent detection signal input terminal of the overcurrent protection circuit, and the first comparator 104 is configured to compare a set reference voltage with a voltage value detected at a monitoring point and output a corresponding level signal, so that the fault logic control circuit triggers an overcurrent protection function or maintains an operating state.

For example, in some specific embodiments, the positive input terminal of the first comparator 104 may be directly or indirectly connected to the over-current monitoring point, and the negative input terminal of the first comparator 104 may be connected to the reference power supply REF, so that when the voltage at the over-current monitoring point is at a lower level, the output terminal of the first comparator 104 outputs a high level signal, and the FAULT logic control circuit does not trigger the over-current protection function, i.e., does not output a FAULT low level signal; conversely, when the voltage at the overcurrent monitoring point is at a higher level, the output end of the first comparator 104 outputs a low level signal, the FAULT logic control circuit triggers the overcurrent protection function, that is, outputs a FAULT low level signal, and at this time, the external processor receives the FAULT low level signal from the FAULT logic control circuit and can trigger overcurrent protection, for example, the power supply of the high-voltage integrated circuit can be disconnected, so as to protect the high-voltage integrated circuit.

In other specific embodiments, the positive input terminal of the first comparator 104 may be connected to the reference power supply REF, and the negative input terminal of the first comparator 104 may be directly or indirectly connected to the over-current monitoring point, so that when the voltage at the over-current monitoring point is at a lower level, the output terminal of the first comparator 104 outputs a low level signal, and the FAULT logic control circuit does not trigger the over-current protection function, i.e., does not output a FAULT low level signal; on the contrary, when the voltage at the overcurrent monitoring point is at a higher level, the output end of the first comparator 104 outputs a high level signal, the FAULT logic control circuit triggers the overcurrent protection function, that is, outputs a FAULT low level signal, and at this time, the external processor receives the FAULT low level signal from the FAULT logic control circuit and can trigger the overcurrent protection.

In the embodiment of the present application, a feedback circuit is added to the first comparator 104 in the overcurrent protection circuit, and the output state of the first comparator 104 has two states, which are either high level or low level. After adding the feedback circuit, the first comparator 104 is characterized in that when the input voltage gradually increases or gradually decreases, two unequal trigger thresholds exist, so that the transmission characteristic has the shape of a hysteresis curve.

The following describes specific effects of the hysteresis circuit in the overcurrent protection circuit of the semiconductor circuit according to the present application with reference to specific circuits.

Referring to fig. 4, in the embodiment of the present application, a hysteresis circuit in the overcurrent protection circuit includes a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4, where one end of the third resistor R3 is connected to an auxiliary power supply Vcc to form a pull-up, and the other end is connected to the fourth resistor R4 to form signal voltage division processing; the other end of the fourth resistor R4 is connected to ground to form a pull-down, which ensures that the low signal is active. After voltage division processing is performed on the third resistor R3 and the fourth resistor R4, signals pass through the second resistor R2 and the first comparator 104, the other end of the second resistor R2 is connected with the first comparator 104, front and rear signal feedback is achieved, two input ports of the first comparator 104 can compare input voltage signals and output corresponding high and low level signals, output signals can be fed back to the U0 at the over-current monitoring point through the first resistor R1 and are output to the fault logic control circuit after signal processing at the rear end.

Thus, when the first comparator 104 is in a state of outputting a high level, assuming that the output terminal is pulled up to 15V, the first resistor R1 and the second resistor R2 are connected in series and then connected in parallel with the third resistor R3, and the equivalent resistance formula of the circuit is as follows: r ═ R1+ R2) × R3/((R1+ R2) + R3), the voltage at U0 can be calculated according to the principle of resistance voltage division: u0 ═ 15V (R4/(R + R4)); when the first comparator 104 is in a state of outputting a low level, the output is grounded, the fourth resistor R4 and the second resistor R2 are connected in parallel, and the equivalent resistance after the parallel connection is (R4 × R2)/(R4+ R2), and similarly, the voltage at the U0 can be calculated according to the principle of voltage division: u0 ═ 15V (R/(R + R1)). Therefore, two different threshold voltages can be obtained, that is, the triggered voltage thresholds of the first comparator 104 are different in different output states, so that a good hysteresis effect can be achieved, and further, the overall anti-interference performance of the circuit can be improved, and the working efficiency of the product can be improved.

In some specific embodiments, the over-current protection circuit may further include a delay circuit 105, a signal storage 106, a logic or gate 107, and an NMOS transistor 108;

the output end of the first comparator 104 is connected to the input end of the delay circuit 105, the output end of the delay circuit 105 is connected to the input end of the signal memory 106, the output end of the signal memory 106 is connected to one input end of the logical or gate circuit 107, the output end of the logical or gate circuit 107 is connected to the gate of the NMOS transistor 108, the source of the NMOS transistor 108 is grounded, and the drain of the NMOS transistor 108 is connected to the fault signal output end.

In the embodiment of the present application, the overcurrent protection circuit may further include a delay circuit 105, a signal storage 106, a logic or gate 107, an NMOS transistor 108, and other signal processing circuits. When the voltage of the positive input end of the first comparator 104 is smaller than the preset voltage threshold, it is determined that there is no overcurrent risk, the first comparator 104 outputs a low level, the low level signal enters the signal memory 106 after being filtered by the delay circuit 105, and is output to the logical or gate circuit 107 after being processed, because the output of the first comparator 104 is a low level and the output of the logical or gate circuit 107 is a low level, the NMOS transistor 108 is turned off, the Fault signal Fault keeps a high level valid, and the semiconductor circuit works normally. On the contrary, when the voltage at the positive input terminal of the first comparator 104 reaches the preset voltage threshold, it is determined that there is an overcurrent risk, the first comparator 104 outputs a high level, the high level signal enters the signal memory 106 after being filtered by the delay circuit 105, and is output to the logical or gate circuit 107 after being processed, because the output of the first comparator 104 is the high level and the output of the logical or gate circuit 107 is also the high level, the NMOS transistor 108 is turned on, the Fault signal Fault becomes the low level, the protection action is triggered, and the semiconductor circuit is in the power-down protection state.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the utility model. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the utility model and to simplify the description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the utility model.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless explicitly specified otherwise.

In the present invention, unless otherwise explicitly stated or limited, the terms "mounted," "connected," "fixed," and the like are to be construed broadly, e.g., as being permanently connected, detachably connected, or integral; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be interconnected within two elements or in a relationship where two elements interact with each other unless otherwise specifically limited. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

In the present invention, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may be directly contacting the second feature or the first and second features may be indirectly contacting each other through intervening media. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.

Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.

Claims (10)

1. A semiconductor circuit having a hysteresis function, the semiconductor circuit comprising:

a high-voltage integrated circuit and a switching tube; the high-voltage integrated circuit comprises a driving circuit, an overcurrent protection circuit and a fault logic control circuit, and the driving circuit is connected with the switching tube;

the overcurrent protection circuit comprises a first comparator, a first resistor, a second resistor, a third resistor, a fourth resistor, a reference power supply and an auxiliary power supply; a first input port of the first comparator is an overcurrent detection signal input port of the overcurrent protection circuit, the first input port of the first comparator is grounded through the fourth resistor, the first input port of the first comparator is also connected to the auxiliary power supply through the third resistor, and a second input port of the first comparator is connected to the reference power supply; the output port of the first comparator is connected to the first input port of the first comparator through the second resistor, the output port of the first comparator is connected to the auxiliary power supply through the first resistor, and the output port of the first comparator is further connected to the fault logic control circuit.

2. A semiconductor circuit having a hysteresis function according to claim 1, wherein the drive circuit comprises a high-side drive circuit and a low-side drive circuit, and the high-side drive circuit and the low-side drive circuit are connected.

3. The semiconductor circuit with hysteresis function of claim 2, wherein the high-voltage side driving circuit comprises three identical high-voltage driving units, each high-voltage driving unit comprising an upper bridge arm signal input end, two high-voltage side power supply ends and a high-voltage side control output end; the high-voltage side control output end is used for outputting a driving signal for driving the upper bridge arm switching tube of one phase.

4. The semiconductor circuit with hysteresis function of claim 3, wherein the high voltage drive unit comprises a first Schmitt trigger, a first filter circuit, a first potential shift circuit, a first dead zone interlock unit, a pulse generation circuit, a DV/DT filter circuit, a latch, a NOR gate, a UV filter circuit, a first MOS transistor, a second MOS transistor, a first current limiting resistor, a second current limiting resistor, and a first output drive circuit;

the input end of the first Schmitt trigger is the upper bridge arm signal input end, and the output end of the first Schmitt trigger is connected with the input end of the first filter circuit; the output end of the first filter circuit is connected with the input end of the first potential displacement circuit; the output end of the first potential displacement circuit is connected with the input end of the first dead zone interlocking unit; the output end of the first dead zone interlocking unit is connected with the input end of the pulse generating circuit; the output end of the pulse generating circuit is connected with the grids of the first MOS tube and the second MOS tube, the drains of the first MOS tube and the second MOS tube are connected with the input end of the DV/DT filter circuit, the drain of the first MOS tube is connected to the positive end of the high-voltage side power supply end through the first current limiting resistor, and the drain of the second MOS tube is connected to the positive end of the high-voltage side power supply end through the second current limiting resistor; the output end of the DV/DT filter circuit is connected with the first input end of the latch, and the output end of the UV filter circuit is connected with the second input end of the latch; the output end of the DV/DT filter circuit is connected with the first input end of the NOR logic gate, and the output end of the latch is connected with the second input end of the NOR logic gate; the output end of the NOR logic gate is connected to the input end of the first output driving circuit.

5. The semiconductor circuit according to claim 4, wherein the first output driver circuit comprises:

a third MOS transistor and a fourth MOS transistor;

the grid of third MOS pipe with the grid of fourth MOS pipe connect in the input of first output drive circuit, the drain electrode of third MOS pipe is connected the positive terminal of high pressure side feed end, the source electrode of third MOS pipe with the drain electrode of fourth MOS pipe connect in the output of first output drive circuit altogether, the source electrode of fourth MOS pipe connect in the negative pole end of high pressure side feed end.

6. The semiconductor circuit with the hysteresis function of claim 4, wherein the low-voltage side driving circuit comprises three identical low-voltage driving units, each low-voltage driving unit comprising a lower bridge arm signal input terminal, a low-voltage side power supply terminal, a low-voltage reference terminal and a low-voltage side control output terminal; the low-voltage side control output end is used for outputting a driving signal for driving a one-phase lower bridge arm switching tube.

7. The semiconductor circuit with hysteresis function of claim 6, wherein the low voltage driving unit comprises a second Schmitt trigger, a second filter circuit, a second potential displacement circuit, a second dead zone interlocking unit, a delay circuit, a second comparator and a second output driving circuit;

the input end of the second Schmitt trigger is the lower bridge arm signal input end, and the output end of the second Schmitt trigger is connected with the input end of a second filter circuit; the output end of the second filter circuit is connected with the input end of the second potential displacement circuit; the output end of the second potential displacement circuit is connected with the input end of the second dead zone interlocking unit; the output end of the second dead zone interlocking unit is connected with the input end of the delay circuit; the output ends of the pulse generating circuit and the delay circuit are connected with the input end of the second comparator, and the output end of the second comparator is connected with the input end of the second output driving circuit.

8. The semiconductor circuit according to claim 7, wherein the second output driver circuit comprises:

a fifth MOS transistor and a sixth MOS transistor;

the grid electrode of the fifth MOS tube and the grid electrode of the sixth MOS tube are connected to the input end of the second output driving circuit in a sharing mode, the drain electrode of the fifth MOS tube is connected with the low-voltage side power supply end, the source electrode of the fifth MOS tube and the drain electrode of the sixth MOS tube are connected to the output end of the second output driving circuit in a sharing mode, and the source electrode of the sixth MOS tube is grounded.

9. The semiconductor circuit with hysteresis function of claim 1, wherein the over-current protection circuit further comprises a delay circuit, a signal memory, a logic or gate circuit and an NMOS transistor;

the output end of the first comparator is connected with the input end of the delay circuit, the output end of the delay circuit is connected with the input end of the signal memory, the output end of the signal memory is connected to one input end of the logic OR gate circuit, the output end of the logic OR gate circuit is connected to the grid electrode of the NMOS tube, the source electrode of the NMOS tube is grounded, and the drain electrode of the NMOS tube is connected with the fault signal output end.

10. The semiconductor circuit with hysteresis function of claim 1, wherein the first input port of the first comparator is a positive input terminal, and the second input port of the first comparator is a negative input terminal.

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