CN216929978U

CN216929978U - Sine wave clock generation circuit, device and system

Info

Publication number: CN216929978U
Application number: CN202123316030.8U
Authority: CN
Inventors: 赵泽平; 陈志春; 徐永杰; 王日炎; 董峥
Original assignee: GUANGZHOU RUNXIN INFORMATION TECHNOLOGY CO LTD
Current assignee: GUANGZHOU RUNXIN INFORMATION TECHNOLOGY CO LTD
Priority date: 2021-12-24
Filing date: 2021-12-24
Publication date: 2022-07-08
Anticipated expiration: 2031-12-24

Abstract

The present invention relates to the field of communications technologies, and in particular, to a sine wave clock generation circuit, apparatus, and system, including: the crystal oscillator is connected with the second crystal filter through the frequency multiplication amplifying circuit and the clock buffer in sequence, the frequency multiplication amplifying circuit comprises a first amplifying circuit, a frequency multiplication circuit, a second amplifying circuit and an LC filter, the first amplifying circuit is connected with the LC filter through the frequency multiplication circuit and the second amplifying circuit in sequence, the input end of the first amplifying circuit is connected with the output end of the crystal oscillator, and the output end of the LC filter is connected with the input end of the clock buffer. The utility model can generate a multi-path frequency-doubled low-jitter clock, and the waveform of the clock is sine wave, thereby reducing the EMC problem of the clock.

Description

Sine wave clock generation circuit, device and system

Technical Field

The present invention relates to the field of communications technologies, and in particular, to a sine wave clock generating circuit, device and system.

Background

Multi-channel receivers often require multiple local oscillator signals to down-convert the channel signals, which need to be implemented with a frequency synthesizer. In order to obtain a frequency synthesizer with excellent output performance, such as excellent phase noise performance, a high stability reference source is often used.

The reference source commonly used at present is generally generated by a crystal oscillator. In a multi-channel receiver, however, it is not practical to have a crystal oscillator for each channel. Firstly, the resources are seriously wasted, and secondly, due to different initial conditions of different crystal oscillators, the generated waveforms cannot be synchronized in phase, which directly results in the frequency synthesizer not being synchronized in phase at the output. Under the condition of few channels, the output of the crystal oscillator is connected to the reference sources of a plurality of frequency synthesizers to solve the problem, but the crystal oscillator has limited driving capability, and the connection mode can only support 3-5 channels at most. For receivers with dozens or dozens of channels, the clock cannot be multiplexed in this way.

The existing one-to-many clock buffer can be divided into multiple paths of clock outputs after passing through a chip through one path of clock input, and the multiple paths of clock outputs are supplied to a plurality of circuit clocks, so that the driving problem of the clocks is solved. However, the use of such a clock buffer to clock a frequency synthesizer presents two problems:

1. after the clock passes through the clock buffer, indexes such as jitter and the like are deteriorated, so that the output phase noise of the frequency synthesizer is difficult to reach the standard, and the receiving sensitivity of a receiver is influenced;

2. multiple clock outputs, which can cause EMC problems; the method specifically comprises the following steps: since the output of the clock buffer is typically formed by gates, its output waveform is a square wave or near square wave. The harmonic formation of the square wave is quite abundant, as can be seen from the fourier transform. Because the sensitivity of the receiver is often very high, some of the receivers even reach below-100 dBm; the harmonics of the output waveform, although having a significant attenuation compared to the main wave, are still well above the sensitivity threshold of the receiver. Once the harmonic frequency falls within the receiving frequency range of the receiver, it will cause a large interference to the receiving signal of the receiver. In the case of multiple clocks, the interference is superimposed, and the receiver cannot operate normally.

SUMMERY OF THE UTILITY MODEL

In order to solve the above problems, it is a primary object of the present invention to provide a sine wave clock generating circuit, device and system, which can generate multiple frequency-doubled low jitter clocks, and the waveforms of the clocks are sine waves, thereby reducing the EMC problem of the clocks.

In order to achieve the purpose, the utility model adopts the technical scheme that:

a sine wave clock generation circuit, comprising: the crystal oscillator is connected with the second crystal filter through the frequency multiplication amplifying circuit and the clock buffer in sequence, the frequency multiplication amplifying circuit comprises a first amplifying circuit, a frequency multiplication circuit, a second amplifying circuit and an LC filter, the first amplifying circuit is connected with the LC filter through the frequency multiplication circuit and the second amplifying circuit in sequence, the input end of the first amplifying circuit is connected with the output end of the crystal oscillator, and the output end of the LC filter is connected with the input end of the clock buffer.

Further, a first crystal filter is connected between the input end of the first amplifying circuit and the output end of the crystal oscillator.

Further, an input end and an output end of the second crystal filter are both connected with an LC matching circuit.

Further, the frequency doubling circuit comprises a first inductor, a schottky diode module, a capacitor C7 and a second inductor, wherein the first inductor is connected with the second inductor through the schottky diode module and the capacitor C7 in sequence.

Further, the crystal oscillator adopts a 10MHz crystal oscillator.

The present invention also provides a sine wave clock generating apparatus comprising the sine wave clock generating circuit as described above.

The present invention also provides a sine wave clock generation system comprising a sine wave clock generation circuit as described above.

The utility model has the beneficial effects that:

the crystal oscillator is connected with the second crystal filter sequentially through the frequency multiplication amplifying circuit and the clock buffer, and the frequency multiplication amplifying circuit comprises a first amplifying circuit, a frequency multiplication circuit, a second amplifying circuit and an LC filter; the frequency multiplication amplifying circuit can realize frequency multiplication of the oscillation signals, the clock buffer can divide the frequency-multiplied oscillation signals into multiple paths of clock signals, and the second crystal filter can realize sine wave output of the clock signals. Therefore, the utility model can generate a plurality of paths of frequency-doubled low-jitter clocks, and the waveform of the clock is a sine wave, thereby reducing the EMC problem of the clock.

Drawings

FIG. 1 is a schematic diagram of a sine wave clock generation circuit according to the present invention.

Fig. 2 is a schematic circuit diagram of the frequency doubling amplifier circuit according to the present invention.

Fig. 3 is a circuit schematic of the LC filter of the present invention.

Fig. 4 is a circuit schematic of the LC matching circuit of the present invention.

FIG. 5 is a schematic diagram of a circuit structure for implementing 48-way 50MHz sine wave clock output according to the present invention.

The reference numbers illustrate: 1. a first amplifying circuit; 2. a frequency multiplier circuit; 3. a second amplifying circuit; 4. a first inductor; 5. a Schottky diode module; 6. a second inductor.

Detailed Description

Referring to fig. 1-4, the present invention relates to a sine wave clock generating circuit, comprising: the crystal oscillator is connected with the second crystal filter sequentially through the frequency multiplication amplifying circuit and the clock buffer, the frequency multiplication amplifying circuit comprises a first amplifying circuit 1, a frequency multiplication circuit 2, a second amplifying circuit 3 and an LC filter, the first amplifying circuit 1 is connected with the LC filter sequentially through the frequency multiplication circuit 2 and the second amplifying circuit 3, the input end of the first amplifying circuit 1 is connected with the output end of the crystal oscillator, and the output end of the LC filter is connected with the input end of the clock buffer;

in the above scheme, the output frequency of the frequency doubling amplification circuit is n × 10MHz (n is 2, 3, 4, 5, 7), and the output frequency thereof depends on the LC filter; the clock buffer can convert one path of clock signals into a plurality of paths of clock signals, and the clock buffer is a digital circuit, so that the output waveform of the clock buffer is a square wave; in addition, since the clock buffer itself is an active device, the jitter of the clock signal passing through the clock buffer increases, and therefore, the parameter of the added jitter needs to be particularly noticed when the clock buffer is selected;

the output end of the clock buffer is connected with a second crystal filter with corresponding frequency, the bandwidth of the common crystal filter is very narrow, and the common crystal filter can be converted into a sine wave signal with the frequency equal to the frequency of the square wave after the harmonic wave is filtered by the square wave as known from Fourier transform.

The utility model has the beneficial effects that:

the utility model can realize the frequency multiplication of the oscillation signal, and the frequency-multiplied signal meets the harsh jitter index requirement of the frequency synthesizer; the utility model can realize up to 144 paths of clock signal output theoretically; all clock signal outputs of the utility model are sine waves, and a good solution is provided for the EMC problem of a multi-path clock system.

Further, a first crystal filter is connected between the input end of the first amplifying circuit 1 and the output end of the crystal oscillator.

Further, the frequency multiplier circuit 2 includes a first inductor 4, a schottky diode module 5, a capacitor C7, and a second inductor 6, and the first inductor 4 is connected to the second inductor 6 through the schottky diode module 5 and the capacitor C7 in sequence.

Further, the crystal oscillator adopts a 10MHz crystal oscillator; the 10MHz crystal oscillator has high stability and can generate a periodic signal with low jitter of 10 MHz.

It should be noted that for some high frequency band receivers, such as microwave band receivers, the frequency synthesizer often needs a relatively high reference frequency to optimize the phase noise of the output signal. The crystal oscillator commonly used in the market is mainly 10 MHz. Most of radio frequency or microwave measuring instrument devices, such as frequency spectrometers, signal sources, etc., have input and output frequencies of 10MHz at most. When higher frequency is needed to be used as the reference frequency of the frequency synthesizer, if a high-frequency crystal oscillator is directly used, the cost of the device is higher, so the method adopts a mode of frequency multiplication by 10MHz and harmonic extraction to obtain the reference frequency of the higher frequency.

The working principle of the sine wave clock generating circuit is as follows:

the output frequency of the frequency multiplication amplifying circuit can be n × 10MHz (n is 2, 3, 4, 5, 7), and preferably, assuming that the clock frequency of the embodiment of the present invention is 50MHz, there are 48 clock outputs in total.

The output of the 10MHz crystal oscillator enters the frequency doubling amplifying circuit after passing through a first crystal filter (10MHz crystal filter), and an oscillation signal is amplified in the frequency doubling amplifying circuit and then passes through a Schottky diode module 5 to generate a harmonic component of 50 MHz; because the amplitude is small, the harmonic component of 50MHz also needs to be amplified by the second amplifying circuit 3; the amplified signal passes through the LC filter (i.e., a 50MHz LC band pass filter; the LC band pass filter is constructed as shown in fig. 3) to obtain harmonics of the desired frequency.

The output end of the frequency multiplication amplifying circuit is connected with a clock buffer, and because the jitter of the clock buffer is deteriorated every time the clock passes through one buffer, the addjitter parameter of the clock buffer is an important reference index for model selection. (jitter is an indication of the clock in the time domain, which corresponds to the phase noise of the clock in the frequency domain). The clock buffer adopts CDCLVCXX series clock buffer chips, and the addjitter of the CDCLVCXX series clock buffer chips is less than 100fs, thereby meeting the technical index requirements.

The CDCLVCXX series clock buffer chip supports 12 paths of clock output at most. Assuming that 48 clock outputs are required, the structure scheme of fig. 5 may be adopted, in which a signal is first passed through one 1-to-4 clock buffer, and then four outputs of the 1-to-4 clock buffer are respectively connected to four 1-to-12 clock buffers, so as to obtain 4 × 12-48 clock signals.

As shown in fig. 5, a second crystal filter is added to the output of each clock buffer to filter clock harmonics and convert the square wave into a sine wave with the same frequency. Because the Q value of the crystal filter is high, the bandwidth is generally in the KHz level and is enough to restrain out-of-band harmonics. As shown in fig. 4, since neither the input nor output impedance of the second crystal filter is 50 Ω, it is necessary to add LC matching circuits at the input and output thereof.

The sine wave clock signal generating process of the sine wave clock generating circuit is as follows:

first, a 10MHz crystal oscillator generates an ultra low jitter oscillating signal with a frequency of 10 MHz. The oscillation signal passes through a 10MHz crystal filter and is output to the frequency multiplication amplifying circuit;

secondly, after entering the frequency doubling amplifying circuit, the signal is amplified first, then passes through the Schottky diode to generate a harmonic component nx10 MHz, and then is amplified; the amplified signal passes through an LC filter to obtain a harmonic wave of a desired frequency;

thirdly, the clock buffer divides the harmonic into multiple paths of clock signals, when the paths of the clock signals are required to be more, for example, 48 paths of clock signals are required, the signals can pass through a 1-to-4 clock buffer, and then four outputs of the 1-to-4 clock buffer are respectively connected with four 1-to-12 clock buffers, so that 4 × 12-to-48 paths of clock signals are obtained;

fourthly, each path of clock signal is connected with a second crystal filter to filter harmonic waves and convert the harmonic waves into sine wave signals.

Compared with the prior art, the utility model has the following advantages and beneficial effects:

1. the utility model can realize the frequency multiplication of the oscillation signal, and the frequency-multiplied signal meets the harsh jitter index requirement of the frequency synthesizer;

2. the utility model can realize up to 144 paths of clock signal output theoretically;

3. all clock signal outputs of the utility model are sine waves, and a good solution is provided for the EMC problem of a multi-path clock system.

The present invention also provides a sine wave clock generating method of the sine wave clock generating circuit, comprising the steps of:

generating an oscillation signal by the crystal oscillator;

transmitting the oscillation signal to the frequency multiplier circuit 2 through the first crystal filter;

amplifying the oscillation signal through the frequency multiplication amplifying circuit and generating a harmonic wave;

filtering the harmonics by the LC filter;

converting the filtered harmonics into a plurality of clock signals through the clock buffer;

converting the clock signal into a sine wave signal by the second crystal filter.

The sine wave clock generation method, the sine wave clock generation device and the sine wave clock generation system achieve the same technical effects as the sine wave clock generation circuit.

The above embodiments are merely illustrative of the preferred embodiments of the present invention, and not restrictive, and various changes and modifications to the technical solutions of the present invention may be made by those skilled in the art without departing from the spirit of the present invention, and the technical solutions of the present invention are intended to fall within the scope of the present invention defined by the appended claims.

Claims

1. A sine wave clock generation circuit, comprising: the crystal oscillator is connected with the second crystal filter through the frequency multiplication amplifying circuit and the clock buffer in sequence, the frequency multiplication amplifying circuit comprises a first amplifying circuit, a frequency multiplication circuit, a second amplifying circuit and an LC filter, the first amplifying circuit is connected with the LC filter through the frequency multiplication circuit and the second amplifying circuit in sequence, the input end of the first amplifying circuit is connected with the output end of the crystal oscillator, and the output end of the LC filter is connected with the input end of the clock buffer.

2. The sine wave clock generation circuit of claim 1, wherein: and a first crystal filter is connected between the input end of the first amplifying circuit and the output end of the crystal oscillator.

3. The sine wave clock generation circuit of claim 1, wherein: and the input end and the output end of the second crystal filter are both connected with an LC matching circuit.

4. The sine wave clock generation circuit of claim 1, wherein: the frequency doubling circuit comprises a first inductor, a Schottky diode module, a capacitor C7 and a second inductor, wherein the first inductor is connected with the second inductor through the Schottky diode module and the capacitor C7 in sequence.

5. The sine wave clock generation circuit of claim 1, wherein: the crystal oscillator adopts a 10MHz crystal oscillator.

6. A sine wave clock generating apparatus, characterized in that: the apparatus comprising a sine wave clock generation circuit as claimed in any of claims 1-5.

7. A sine wave clock generation system, characterized by: the system includes a sine wave clock generation circuit as claimed in any of claims 1-5.