CN216848053U - Aging testing device with automatic state switching function - Google Patents

Abstract

The utility model relates to an aging testing device of state automatic switch-over, including control module and SoC station module, control module include singlechip, control switching circuit and data option switch, SoC station module include functional module and GPIO module, the GPIO module in select arbitrary GPIO pin and be connected with data option switch input pin, control switching circuit and functional module link to each other, the singlechip select signal pin through control data option switch, strobe the GPIO pin of this SoC station, discern this GPIO pin level, the rethread control switches over the aging testing mode of the functional module of circuit switch this SoC station, realize aging testing mode switch. The method can effectively reduce the labor cost, shorten the testing time, and reduce the testing difficulty and the testing operation complexity.

Description

Aging testing device with automatic state switching function

Technical Field

The utility model relates to an aging testing technique of chip especially indicates an aging testing device of state automatic switch-over.

Background

At present, the aging test of a chip circuit is a key technical test of the reliability of an soc (system on chip) chip circuit, and the long-term operation condition of the chip circuit is simulated by using an electric stress and thermal stress acceleration mode so as to evaluate the service life of the chip and the reliability of long-term power-on operation. The conventional chip circuit burn-in test includes a dynamic burn-in test in addition to a static burn-in test, and the dynamic burn-in test is divided into an internal dynamic burn-in test and an external interconnection dynamic burn-in test. The static aging test only needs to be powered on and put into the incubator, and no program runs in the chip circuit.

On the aging test board card bearing the chip circuit, the interconnection dial switch is added as a conversion medium in the process from the internal dynamic aging test to the external dynamic aging test of the chip circuit, namely, the internal dynamic aging test and the external dynamic aging test are separated, when an internal dynamic aging test mode is used, the input pin of the chip circuit needs to be connected with the dial switch to a fixed level through a series resistor, the output pin is connected with the dial switch to the ground through an RC in series, and the interconnection dial switch is in a disconnected state. When an external interconnection dynamic aging test is required, the dial switch with the input pin series resistor connected with a fixed level needs to be disconnected, the dial switch with the output pin series resistor connected with the RC to the ground is disconnected, and the interconnection dial switch is in a connection state. And generally, only the same type of chips are placed on the whole aging circuit board card for aging test. The problems thus posed are: firstly, if a plurality of functional pins need to be switched in the interconnection aging test from the inside to the outside of each station, manual labor is consumed for manual switching; secondly, the two dynamic test modes can not be freely and flexibly switched during the aging test; thirdly, the chip circuits with different specifications and needing to be tested can not be placed on the same burn-in board more efficiently.

SUMMERY OF THE UTILITY MODEL

Therefore, the utility model aims to solve the technical problem that the problem of aging the integrated circuit board among the prior art not enough in the aspect of the conversion of two kinds of aging testing modes of developments of chip circuit aging testing is overcome to provide one kind and utilize single chip microcomputer control, the dynamic aging testing work of chip circuit is accomplished to more efficient, can satisfy the aging testing device of different users' requirement.

For solving the technical problem, the utility model discloses an aging testing device of state automatic switch-over, including control module and SoC station module, control module and SoC station module link to each other, just control module include singlechip, control switching circuit and data selection switch, wherein the singlechip link to each other with control switching circuit and data selection switch respectively, SoC station module include a plurality of SoC station, just arbitrary SoC station divide into functional module and GPIO module.

The utility model discloses an embodiment, the SoC station on be equipped with the SoC chip of polytypic, and SoC station position order is row arrangement, row arrangement or SoC chip kind and arranges.

In an embodiment of the present invention, the control switching circuit is controlled in a relay control mode.

In an embodiment of the present invention, the data selection switch is controlled by an n-bit data selector; the data selector selects a data selector for n, wherein n is a positive natural number.

In an embodiment of the present invention, the function module includes a UART interface, an SPI interface, an IIC interface and a CAN interface, and the number of the UART interface, the SPI interface, the IIC interface and the CAN interface is an even number.

In an embodiment of the present invention, the GPIO module has a plurality of GPIO pins, and the GPIO module is connected to the data selector signal input pin through the GPIO pins.

In an embodiment of the present invention, the position sequence of the SoC stations is consistent with the sequence of the data selector signal input pins.

Compared with the prior art, the technical scheme of the utility model have following advantage: aging testing device, it is not enough to improve the conversion aspect of two kinds of aging testing modes of traditional ageing integrated circuit board to the developments of chip circuit aging testing, utilizes single chip microcomputer control, the dynamic aging testing work of chip circuit is accomplished to the more efficient, can satisfy different users' requirement.

Drawings

In order to make the content of the present invention more clearly understood, the present invention will be described in further detail with reference to the following embodiments of the present invention, in conjunction with the accompanying drawings.

FIG. 1 is a schematic block diagram of a system single-station test function.

FIG. 2 is a diagram of a UART control switch circuit.

FIG. 3 is a diagram illustrating data channel selection.

Fig. 4 is a block diagram of the switching process of the system dynamic and static test modes.

As shown in the figure: 101. a control module; 102. a single chip microcomputer; 103. controlling the switching circuit; 104. a data selection switch; 105. any one SoC station; 106. the system comprises a functional module, 107, a GPIO module, 301, a first SoC station, 302, a second SoC station, 303, a third SoC station, 304, an nth SoC station, 305 and a SoC station module.

Detailed Description

As shown in fig. 1 to 3, the present embodiment provides an aging test apparatus with automatic state switching, which includes a control module 101 and an SoC workstation module 305, where the control module 101 is connected to the SoC workstation module 305, and the control module 101 includes a single chip 102, a control switching circuit 103 and a data selection switch 104, where the single chip 102 is respectively connected to the control switching circuit 103 and the data selection switch 104, the SoC workstation module 305 includes a plurality of SoC workstations 105, and any one of the workstations SoC 105 is divided into a function module 106 and a GPIO module 107.

The utility model discloses in, according to the ageing requirement of SoC chip developments, all outputs concatenate 10K omega resistance and 0.1uF electric capacity to ground, and all input ports connect 10K omega resistance to fixed level, set up fixed level here and be ground.

Specifically, as shown in fig. 1, a functional module 106 of any SoC workstation 105 of the SoC workstation modules 305 includes an even number of UART interfaces, SPI interfaces, IIC interfaces, CAN interfaces, and the like, and the functional module 106 is connected to the control switching circuit 103 of the control module 101.

Specifically, for convenience of understanding, any GPIO connected to the input pin of the data selection switch 104 in the GPIO module 107 of the SoC workstation is defined as GPIOx.

The SoC stations are provided with multi-type SoC chips, and the SoC stations are arranged in sequence of rows, columns or types of SoC chips.

The control switching circuit 103 adopts a relay control mode for control.

The data selection switch 104 is controlled by an n-bit data selector; the data selector selects a data selector for n, wherein n is a positive natural number.

Specifically, the data selection switch 104 is a one-out-of-more data selection switch 104, that is, a one-out-of-more data selector, the single chip microcomputer 102 is connected to a data selection pin of the data selection switch 104, and the single chip microcomputer 102 starts to gate from the first bit according to a binary addition carry mode and in sequence, that is, gates GPIOx of the first SoC station 301 to be connected to the single chip microcomputer 102 through an output pin of the data selection switch 104.

Specifically, when the internal dynamic aging test is set, the level of GPIOx is low, the SoC workstation functional module 106 connects the 10K Ω resistor and the 0.1uF capacitor in series to ground at the output terminal and connects the 10K Ω resistor to ground at the input terminal according to the dynamic aging requirement.

Specifically, when the SoC workstation needs to change the internal dynamic aging test into the external interconnection dynamic aging test, the low level of the GPIOx becomes the high level, the single chip microcomputer 102 sequentially gates and identifies the GPIOx pin level of the SoC workstation according to the data selection switch 104, and when the single chip microcomputer 102 detects that the GPIOx level of the SoC workstation is the high level, the single chip microcomputer 102 controls the switching circuit 103 to complete the switching control from the internal dynamic aging test of the SoC workstation function module 106 to the external interconnection dynamic aging test mode.

Specifically, when the SoC workstation needs to change the external interconnection dynamic aging test into the internal dynamic aging test, the high level of the GPIOx is changed into the low level, the single-chip microcomputer 102 sequentially gates and identifies the GPIOx pin level of the SoC workstation according to the data selection switch 104, and when the single-chip microcomputer 102 detects that the GPIOx level of the SoC workstation is the low level, the single-chip microcomputer 102 controls the switching circuit 103 to complete the switching control from the external interconnection dynamic aging test to the internal dynamic aging test mode of the SoC workstation function module 106.

The functional module 106 includes a UART interface, an SPI interface, an IIC interface, and a CAN interface, and the number of the UART interface, the SPI interface, the IIC interface, and the CAN interface is an even number.

The GPIO module 107 is provided with a plurality of GPIO pins, and the GPIO module 107 is connected with the signal input pin of the data selector through the GPIO pins.

Specifically, if other different types of SoC chips are placed in the SoC station, the above dynamic two aging test mode switching method is also applicable, that is, the detection apparatus can perform high-temperature aging tests on different types of SoC chips at the same time.

Specifically, since the number of interfaces of the functional module 106 is large and the explanation is complicated, the number of the UART interface, the SPI interface, the IIC interface, and the CAN interface is set to 2 groups for easy understanding.

And the position sequence of the SoC stations is consistent with the sequence of the signal input pins of the data selector.

Furthermore, the modules are integrally installed on a circuit board.

Specifically, for convenience of understanding, a specific operation method of switching between two dynamic aging test modes of the SoC workstation is to take the UART interface of fig. 2 as an example, in fig. 2, UART _ RXD0 is a data receiving pin of UART0, and UART _ TXD0 is a data transmitting pin of UART 0. Similarly, UART _ RXD1 is a data receiving pin of UART1, and UART _ TXD1 is a data transmitting pin of UART 1.

Specifically, in fig. 2, the SC _ SOC _ CTL pin is connected to the single chip microcomputer 102, the U1 is a relay, and the Q1 is an NPN transistor. When the internal dynamic burn-in test mode is performed, the SC _ SOC _ CTL pin is at a low level, the relay U1 is not operated, the output port UART _ TXD0 is connected with the resistor R4 and the capacitor C1 to ground, the UART _ TXD1 is connected with the resistor R9 and the capacitor C2 to ground, and the input ports UART _ RXD0 and UART _ RXD1 are connected with the resistor R1 and the resistor R7 to ground, respectively. During the external interconnection dynamic aging test, the SC _ SOC _ CTL pin is at a high level, the 2 nd pin and the 3 rd pin of the transistor Q1 are turned on, the 5 th pin and the 6 th pin of the relay U1 are turned on, the relay is pulled in, the UART _ RXD0 pin is connected with the UART _ TXD1 pin, the UART _ TXD0 is connected with the UART _ RXD1, meanwhile, the input port UART _ RXD0 and the UART _ RXD1 are respectively disconnected from the resistor R1 and the resistor R7, the output port UART _ TXD0 is disconnected from the resistor R4 and the capacitor C1, and the UART _ TXD1 is disconnected from the resistor R9 and the capacitor C2.

Similarly, the step of pairing the data receiving and transmitting pins of the switching of the two dynamic aging test modes such as the CAN interface is consistent with the UART, the TXD transmitting pin of the CAN0 is connected with the RXD receiving pin of the CAN1 through a relay pin, and the TXD transmitting pin of the CAN1 is connected with the RXD receiving pin of the CAN0 through a relay pin.

Specifically, for convenience of understanding, the hardware circuit of the interface of the functional module 106 for the external interconnection dynamic aging test of the SPI interface and the IIC interface is connected as follows: SPI0 interface master/slave output pin MISO0 is connected to master/slave input pin MOSI1 of SPI1 interface, SPI0 interface master/slave input pin MOSI0 is connected to SPI1 interface master/slave output pin MISO1, and SPI0 serial clock SCK0 is connected to SPI1 serial clock SCK 1.

Specifically, the data line SDA0 and the clock line SCL0 of the IIC0 interface are connected to the data line SDA1 and the clock line SCL1 of the IIC1 interface, respectively.

Specifically, the aging board card of the SoC may have a plurality of kinds of SoC stations, and both of the high-temperature aging test dynamic two kinds of aging test mode switching control lines of each same kind of SoC chip may be connected to an arbitrary GPIO pin of the single chip microcomputer 102, and for convenience of understanding, this GPIO may be connected to the GPIO pin of the single chip microcomputer 102 of this pin of SC _ SoC _ CTL according to what is shown in fig. 2.

Specifically, for convenience of understanding, as shown in fig. 3, any GPIO pin of the GPIO module 107 in the SoC workstation of the SoC workstation module 305 is connected to the input pin of the data selector, that is, the GPIOx pin of the GPIO module 107 in the first SoC workstation 301 is connected to the D0 pin of the data selector, the GPIOx pin of the GPIO module 107 in the second SoC workstation 302 is connected to the D1 pin of the data selector, and so on until the GPIOx pin of the GPIO module 107 in the nth SoC workstation 304 is connected to the Dn-1 pin of the data selector.

Specifically, when the internal dynamic aging test is performed inside the SoC chip, the GPIOx on the SoC workstation is set to be at a low level, and when the functional module 106 of the SoC chip requires the external interconnection dynamic aging test, the GPIOx on the SoC workstation is set to be at a high level.

Specifically, the data selection pins A0 to Am-1 have m bits, the number of the data selection pins and the number of the input pins of the addition of the data selector are in a relation of m power of 2, the data selection pins are connected with any GPIO of the single chip microcomputer 102, the single chip microcomputer 102 controls the data selection pins according to a two-stage addition sequence, and the GPIOx level condition of the SoC station is detected and judged in a single gating mode.

Specifically, for example, when a0 is at a high level and the rest is at a low level, the GPIOx of the first SoC workstation 301 is gated to be connected to the single chip microcomputer 102, the single chip microcomputer 102 detects that the GPIOx is at the high level, and determines that the workstation needs an external interconnection dynamic aging test, and then the single chip microcomputer 102 switches the internal dynamic aging test to the external interconnection dynamic aging test mode of the functional module 106 of the SoC workstation by controlling the switch.

Specifically, for better understanding, two dynamic burn-in test modes of the system are switched as shown in fig. 4, the system is powered on, the default burn-in mode of the high-temperature burn-in test is an internal dynamic burn-in test, and the GPIOx level of all SoC workstations is set to be a low level.

Specifically, the level of a pin connected between the single chip microcomputer 102 and the control switching circuit 103 is a low level, and the single chip microcomputer 102 selects the pin according to the data of the control data selection switch 104, performs a binary addition method, sequentially gates the GPIOx level of the SoC station, and makes a determination here.

Specifically, whether the GPIOx level of the gated SoC workstation is a high level is determined, and if the GPIOx level is a high level, it indicates that the internal dynamic aging test of the gated SoC workstation at this stage is completed, and the functional module 106 needs to be converted into an external interconnection dynamic aging test, and then the level of the pin connecting the single chip microcomputer 102 and the control switching circuit 103 is a high level, the relay magnet of the control switching circuit 103 is attracted, and the external interconnection dynamic aging test mode of the functional module 106 is correctly switched.

Specifically, if the GPIOx level of the gated SoC workstation is low, the next SoC workstation continues to be gated, and the GPIOx level condition is identified.

Specifically, after the GPIOx levels of all SoC workstations are scanned, the next cycle of repeated scanning is automatically entered, and it is further determined whether the workstation needs two dynamic aging modes for conversion.

It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious changes and modifications can be made without departing from the scope of the invention.

Claims (7)

1. The aging test device with the automatic state switching function is characterized by comprising a control module and an SoC station module, wherein the control module is connected with the SoC station module and comprises a single chip microcomputer, a control switching circuit and a data selection switch, the single chip microcomputer is respectively connected with the control switching circuit and the data selection switch, the SoC station module comprises a plurality of SoC stations, and any one SoC station is divided into a function module and a GPIO module.

2. The burn-in test apparatus for automatic switching of states according to claim 1, wherein: the SoC stations are provided with multi-type SoC chips, and the SoC stations are arranged in sequence of rows, columns or types of SoC chips.

3. The burn-in test apparatus for automatic switching of states according to claim 1, wherein: the control switching circuit is controlled in a relay control mode.

4. The burn-in test apparatus for automatic switching of states according to claim 1, wherein: the data selection switch is controlled by an n-bit data selector; the data selector selects a data selector for n, wherein n is a positive natural number.

5. The burn-in test apparatus for automatic switching of states according to claim 1, wherein: the function module comprises a UART interface, an SPI interface, an IIC interface and a CAN interface, and the number of the UART interface, the SPI interface, the IIC interface and the CAN interface is even.

6. The burn-in test apparatus for automatic switching of states according to claim 1, wherein: the GPIO module is provided with a plurality of GPIO pins and is connected with the signal input pin of the data selector through the GPIO pins.

7. The burn-in test apparatus with automatic switching of states as claimed in claim 4, wherein: and the position sequence of the SoC stations is consistent with the sequence of the signal input pins of the data selector.

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