CN111381148B

CN111381148B - System and method for realizing chip test

Info

Publication number: CN111381148B
Application number: CN201811638607.7A
Authority: CN
Inventors: 翟昊方
Original assignee: CRM ICBG Wuxi Co Ltd
Current assignee: CRM ICBG Wuxi Co Ltd
Priority date: 2018-12-29
Filing date: 2018-12-29
Publication date: 2023-02-21
Anticipated expiration: 2038-12-29
Also published as: CN111381148A

Abstract

The invention relates to a system for realizing chip test, which comprises an analog IP module, a test module and a test module, wherein the analog IP module is used for carrying out analog IP test; the digital module is connected with the analog IP module and is used for testing internal communication signals; the input/output unit library is connected with the array module and used for packaging connecting wires; and the test module is connected with the analog IP module, the digital module and the input/output unit library and is used for testing the chip. The invention also relates to a method for realizing the chip test. The system and the method for realizing the chip test solve the error problem of DFT related tools under the condition of meeting the requirement of the minimum pins used by the chip, realize various tests of the chip, and do not need to increase the test pins, thereby reducing the area of the chip as much as possible, controlling the cost, leading the test to be more flexible, controlling the whole chip through the input of individual pins, correspondingly reducing the requirement on a test board card of a test machine, having simple interface and reducing the cost.

Description

System and method for realizing chip test

Technical Field

The invention relates to the field of chips, in particular to the field of chip testing, and specifically relates to a system and a method for realizing chip testing.

Background

In the case of sufficient pins, a chip test design generally uses one pin exclusively as a test enable, and selects several pins alternatively as test modes, and according to different test modes, required excitation is driven through the pins, and comparison is observed through output.

During DFT, only corresponding test pins are defined in the running script, the state is confirmed, the read-in IO library is a pure digital standard IO library, the structure definition is clear, and tools can be automatically inserted into a scan chain, scan chain inspection, coverage rate statistics and the like.

The test enable exists independently, the test mode pins are enough, the used pure digital standard IO library is used, the testability design of the circuit is based on the sufficient pins, the IO port is relatively simple, the applicability is not high, the defects caused by the fact that the number of the pins is too large, the area is too large, the cost is too high are overcome, the requirements on a board card of a test machine are correspondingly improved, the test cost is increased, and the efficiency is reduced.

Disclosure of Invention

The invention aims to overcome the defects of the prior art and provides a system and a method for realizing chip testing, which have the advantages of high efficiency, low cost and wider application range.

In order to achieve the above object, the system and method for realizing chip test of the present invention are as follows:

the system for realizing chip testing is mainly characterized by comprising the following components:

the simulation IP module is used for carrying out simulation IP test;

the digital module is connected with the analog IP module and is used for testing internal communication signals;

the input/output unit library is connected with the digital module and used for packaging a connecting line;

the test module is connected with the analog IP module, the digital module and the input/output unit library and is used for testing the chip;

the test module comprises a control pin, and the control pin is connected with the input/output unit library through pins of the input/output unit library and is used for controlling different test modes of the chip.

Preferably, the test module further comprises:

the input selection control unit is connected with the analog IP module and used for selecting a normal function mode and a test mode of the input end of the analog IP module, providing an input pin of a scan chain and controlling the state of the clock reset module in different modes;

the output selection control unit is connected with the analog IP module and used for transmitting a corresponding normal function signal to the PAD output end in a normal function mode and transmitting an output signal of the analog IP module or the clock reset module to be tested to the PAD output end in a test mode;

the port multiplexing test control unit is connected with the input and output unit library and is used for controlling the input and output and analog/digital selection of PAD;

the port selection control unit is connected with the input and output unit library and is used for transmitting a normal signal of an input pin of the PAD to the glue _ scan module in a normal function mode; in the test mode, the test signal on the PAD input pin is transmitted to the test module test _ ctrl _ top.

Preferably, the port multiplexing test control unit is divided into a normal function mode control state and a test mode control state.

The method for realizing the chip test based on the system is mainly characterized by comprising the following steps:

(1-1) selecting a functional mode and a test mode through the control pin;

(1-2) synthesizing and inserting chains for the digital logic by using a synthesis and insertion chain tool, and performing layout and wiring and post-simulation netlist integration modification;

(1-3) carrying out scan chain inspection and other test pattern simulation and generating a test pattern;

and (1-4) driving corresponding excitation into chip pins according to the information of the test codes and a specified time sequence, and judging chip abnormality through data output and output values of the test codes.

Preferably, the step (1-1) specifically comprises the following steps:

(1-1.1) judging whether the state of the control pin is 1, if so, entering a test mode by the chip, and continuing the step (1-1.2); otherwise, the chip is in a normal functional mode;

(1-1.2) different test modes are controlled by scan chain mode and register state.

Preferably, the steps (1-3) specifically include the following steps:

(1-3.1) judging whether the scan chain of the subsequent artificial netlist is normal according to the scan chain mode, if so, generating a test vector, otherwise, continuing the step (1-1);

(1-3.2) simulating other test modes, and driving in an excitation by an I2C protocol;

and (1-3.3) verifying the correctness of each function of the chip through the output signal, generating a test code and verifying the function.

Preferably, the method further includes a wafer Test (CP, chip bonding) and a Final Test (FT, final Test), wherein the wafer Test is a wafer level Test, generally referred to as "intermediate Test", and the Final Test is a packaged Chip level Test, generally referred to as "finished Test", and the wafer Test (CP, chip bonding) and the Final Test (FT, final Test) specifically include the following steps:

(2-1) performing a contact test;

(2-2) performing a standby current test and a working current test;

(2-3) performing scan chain test and memory self-test;

and (2-4) performing a clock reset test and each analog IP test.

Preferably, the method further comprises a specific step of entering the test mode, specifically comprising the following steps:

(3-1) designing an analog/digital multiplexing pin;

and (3-2) applying high voltage to the pin to generate a signal from low to high, and entering a test mode.

(4-1) typing a test mode code into the pin;

and (4-2) entering a test mode through decoding.

By adopting the system and the method for realizing the chip test, the error problem of DFT related tools is solved under the condition of meeting the requirement of the minimum pins used by the chip, various tests of the chip are realized, the test pins are not required to be added, so that the chip area is reduced as much as possible, the cost is controlled, the test becomes more flexible, the whole chip can be controlled by the input of individual pins, the requirement on a test board card of a test machine table is correspondingly reduced, the interface is simple, the cost is reduced, and the invention relates to the mass production of chips and the stable test.

Drawings

Fig. 1 is a schematic structural diagram of a system for implementing chip testing according to the present invention.

FIG. 2 is a flow chart of a method for implementing chip testing according to the present invention.

FIG. 3 is a flow chart of FT testing using the method of the present invention for implementing chip testing.

Fig. 4 is a schematic circuit diagram of entering a test mode in the method for implementing chip testing according to the present invention.

Detailed Description

In order to more clearly describe the technical contents of the present invention, the following further description is given in conjunction with specific embodiments.

The system for realizing chip test of the invention comprises:

the simulation IP module is used for carrying out simulation IP test;

the input and output unit library is connected with the digital module and used for packaging a connecting line;

As a preferred embodiment of the present invention, the test module further comprises:

the output selection control unit is connected with the analog IP module and is used for transmitting a corresponding normal function signal to the PAD output end in a normal function mode and transmitting an output signal of the tested analog IP module or the clock reset module to the PAD output end in a test mode;

the port selection control unit is connected with the input and output unit library and is used for transmitting a normal input pin signal of the PAD to the glue _ scan module in a normal function mode; in the test mode, a test signal on the PAD input pin is transmitted to the test module test _ ctrl _ top.

As a preferred embodiment of the present invention, the port multiplexing test control unit is divided into a normal function mode control state and a test mode control state.

The method for realizing the chip test based on the system comprises the following steps:

(1-1) selecting a functional mode and a test mode through the control pin;

(1-1.1) judging whether the state of the control pin is 1, if so, entering a test mode by the chip, and then

The subsequent step (1-1.2); otherwise, the chip is in a normal functional mode;

(1-1.2) controlling different test modes by scan chain mode and register state;

As a preferred embodiment of the present invention, the step (1-3) specifically comprises the following steps:

As a preferred embodiment of the present invention, the method further comprises a wafer Test (CP, chip bonding) and a Final Test (FT, final Test), wherein the wafer Test is a wafer level Test generally called "middle Test", the Final Test is a packaged Chip level Test generally called "finished Test", and the wafer Test (CP, chip bonding) and the Final Test (FT, final Test) specifically comprise the following steps:

(2-1) performing a contact test;

(2-2) performing a standby current test and a working current test;

(2-3) carrying out scan chain test and memory self-test;

and (2-4) performing a clock reset test and each simulation IP test.

As a preferred embodiment of the present invention, the method further includes a specific step of entering a test mode, specifically including the following steps:

(3-1) designing an analog/digital multiplexing pin;

(3-2) applying high voltage to the pin to generate a signal from low to high, and entering a test mode.

(4-1) typing a test mode code into the pin;

and (4-2) entering a test mode through decoding.

In the specific implementation mode of the invention, under the limited pins of the chip, the testability design of DFT, analog trimming, performance and the like of the chip is solved by adopting the self-built digital-analog universal pins. The problem of errors when the self-built digital-analog universal pin cell library cannot be completely described and a tool is inserted into DFT is well solved, and other test modes can also work normally.

DFT is referred to herein as design for testability. PAD is actually a passivation hole, IO is generally composed of two parts, one is PAD, the other is a circuit, input and output of a chip are achieved, the PAD is used for connecting a gold wire during packaging, and a probe is in contact with the PAD during wafer testing. The IP refers to an IP core, i.e., a pre-designed circuit function module. MUX IN, MUX OUT and TEST GPIO respectively refer to input selection control, output selection control and a port multiplexing TEST control module, FT refers to final TEST of a chip, and CP refers to wafer TEST. mem _ bist: memory and self-test module.

The digital-analog universal pin is a reference standard IO bank, multiplexing of analog input and output is increased, the digital-analog universal pin is formed by a hardware circuit, and the structure of the digital-analog universal pin can be referred to as that shown in FIG. 4.

The chip of the invention has been tested and verified to have functional reliability through packaging, and the product model is CS4977.

Chip testability design generally provides for testing of internal IP, digital logic, memory, and the entire chip by way of MUX IN, MUX OUT. In order to realize the test function, the communication signals of the PAD module, the analog IP module (analog _ top) and the modules (glue _ top) inside the whole digital module are all linked through the test module (test _ ctrl _ top), and the relationship between the test module and each module is shown in fig. 1.

The interior of the test module can be divided into four parts, and each part has the following functions:

1. MUX IN: entering and selecting a test mode; the selection of a normal function mode and a test mode of the input end of the analog IP module is realized; providing an input pin of a scan chain; and controlling the states of the clock reset module in different modes.

2. MXU OUT: in the normal function mode, the module transmits a corresponding normal function signal to the PAD output; and in the test mode, the output signal of the tested analog IP module or the clock reset module is transmitted to the PAD output end, so that the external PIN can observe whether the output waveform is correct or not.

3. TEST GPIO: the input and output of PAD and analog/digital selection are controlled, which can be divided into normal function mode control or test mode control.

4. TEST SCAN MUX: in the normal function mode, the normal signal of the input pin of the PAD is transmitted to the glue _ scan module so as to enable the sub-modules in the PAD to work normally; in the test mode, the test signal on the PAD input pin is transmitted to the test module test _ ctrl _ top.

The design for testability of the chip satisfies the test flow of the chip, generally, the FT test (final test) is the most complete, and the flow is shown in fig. 3.

The contact test is directly performed on all pins without entering a test mode, and each subsequent test needs to enter each test mode. The following begins with entering test mode.

For the testability design of a chip, under the condition of not occupying normal functional pins, what is needed to do first is how to enter a test mode, and there can be several methods:

1. an analog/digital multiplexing pin is designed, when a high voltage is applied to the pin, for example, 3.3V is a normal number, the voltage can be applied to more than 7V, and a signal from low to high can be generated, so that a test mode can be entered, and the circuit diagram is shown in fig. 4.

2. Test mode codes are typed in through individual pins, and whether to enter a test mode is controlled later through decoding.

The first method has the advantages that the analog/digital multiplexing pin can still be used in a functional mode, the pin is not wasted, and the DFT test code is generated in a tool and can be directly used for circuit test without considering the splicing and time sequence control of the test mode code and the DFT test code; in the second method, the test mode can be prevented from being mistakenly entered in an unpredictable situation in the normal function mode, but DFT splicing codes and debugging time sequences are required, and time sequence problems may be considered in other modes.

The two schemes for entering the test mode are different from the structural principle, and only one special test pin can be saved.

As shown in FIG. 4, PAD is the pin of the chip, and only the input pin is shown in the figure. Wherein the dotted line frame is an input pin with normal function, the working voltage is 5.5V, when the digital signal is input, the ie _ dig switch controls the input, the digital signal is output to the inside of the chip through c _ dig, ie _ ana is used for controlling analog input in a switching mode, the analog signal is output to the inside of the chip through c _ ana, and pe is used for controlling pull-up and pull-down; when 7V voltage is added to PAD, a Zener tube is subjected to reverse breakdown (Z1) and forward conduction (Z2) and an MOS tube (M1) is conducted, finally, test _ en outputs high level (namely, a test mode is entered), the added 7V voltage is composed of Vz1+ Vz2+ VM1=5.5V +0.7V +0.8V, and Z3 is used for ensuring that the normal function in a virtual line frame cannot be influenced when the voltage exceeds 5.5V.

After entering the test mode, each test mode is selected next. Taking the first method as an example, the scan _ mode is selected as the scan chain test mode when being in the high level, and is selected as the other test mode when being in the low level, and the other test mode can be controlled by the I2C module through the register to control the digital part test and the analog IP test mode.

Other test modes only need to be test _ en of 1 (PAD plus high voltage 7V is generated), scan _ mode is 0, different test modes are selected by I2C device addressing, and different device addresses correspond to different test modes;

Test_en

Scan_mode

Pad1

Pad2

Pad3

Pad4

Pad5

state of state

0

x

i ² c_scl

i ² c_sda

x

NORMAL_FUNC

1

scan_clk

scan_rstn

scan_en

scan_in

scan_out

SCAN_TEST

1

0

test_clk

test_rstn

i ² c_scl

i ² c_sda

Test_out

OTHER_TEST

The test mode in the table is mainly controlled by test _ en, the test _ en is a normal function mode when being 0 and is a test state when being 1, the SCAN _ mode is used for selecting a SCAN mode or other test modes, and Pad1 to Pad5 are other pins, and the purposes of the test modes are different.

So far, the circuit design has no problem from the code design point of view, and other test modes except the scan chain mode are quite flexible and controllable, but errors can occur to the DFT tool and the subsequent scan chain test vector generation tool for the design, and the problems are as follows:

1. the digital-analog mixed interface causes tool reading errors because the IO library description LIB file cannot be clearly described due to excessive signals;

2. the DFT tool can not identify the test mode and the scan chain mode and can not insert the scan chain correctly for the high voltage application and the test mode code input;

3. the scan chain test vector generation tool can firstly check each problem of the scan chain through the simulation model module, and cannot generate test vectors for the complex IO which cannot be identified.

The problems are solved, the test pins used by DFT are all led to a TOP layer in an RTL code stage before synthesis, signals originally connected with a test module are suspended, dot _ toutch is set, after synthesis and DFT completion, chain insertion, inspection and coverage rate statistics are correct, tools are used for inspection and generating test vectors for DFT simulation after synthesis, and finally, a netlist is modified, original connection is recovered, and the modified netlist is handed to a rear end for layout and wiring; otherwise, after the back-simulated netlist comes out, the port used by DFT is led to the TOP layer, then a tool is used for scan chain inspection and generation of a back-simulated test vector, and a scan chain mode back simulation is carried out to generate a test code.

If the used test pattern code enters the test pattern, the previous pattern code and the code of the scan chain need to be spliced, and the timing sequence needs to be adjusted to finally finish the scan chain test by considering the deviation between simulation and actual test when the chip is used for CP and FT tests.

The simulation is mainly carried out through back simulation, two extreme conditions are generally simulated, in the actual test, the working voltage and the temperature are in normal ranges, the test and the simulation can input data with the same time sequence, but during data output comparison, the phase relation between the simulation data and a clock can be referred, if the simulation is low-voltage and high-temperature (in the worst case, the data is slowly turned), the chip test environment is generally better, the data is quickly turned, and the data can be compared in the forward direction during data comparison.

Other methods can be adopted to enter a test mode, and when DFT is performed, chain insertion and test vector generation can be performed automatically, but a large amount of manpower is needed, the cost is increased, and the risk of reducing the test coverage rate is reduced. The specific operation is to manually string the scan chains without using a DFT tool to generate test vectors by itself, or to manually insert the chains into the underlying logic by using the tool and then to manually link the chains to the interface. The common point is to realize scan chain inspection and ensure the chip to be normal.

The method for realizing the chip test based on the system comprises the following operation processes:

1. test module design and pin design: the former is digital design, and the latter is analog layout design; the design of the test module is that test enable (test _ en) and scan chain mode (scan _ mode) are determined, and the states of each input/output pin in the functional mode and the test mode, and the working states of the internal part and IP are selected through a control pin; the pin design implements the function of a test pin as in fig. 3.

2. System integration: the test mode, PAD, IP and digital logic are integrated, and the test pins are defined to be directly pulled to the top layer input and output, so that the normal operation of a comprehensive chain-inserting tool is facilitated.

3. Synthesizing and inserting chains: and synthesizing and inserting chains for the digital logic by using a synthesis and insertion chain tool, and removing the top-layer test pin from the synthesized netlist to connect the top-layer test pin to the input and output of the self-built universal pin.

4. Laying out and wiring: and performing clock tree insertion, layout and wiring and the like on the synthesized netlist.

5. And (3) post-simulation netlist integration modification: and the test pins are continuously pulled to the top layer input and output, so that the tool can conveniently perform insertion chain inspection and generate test codes.

6. Scan chain inspection, other test pattern simulation and test pattern generation: checking whether the scan chain mode of the simulated netlist is normal by using TetraMax, and generating a test vector for simulation and a test code when the scan chain mode passes the check; and other test modes are subjected to simulation, the I2C protocol inputs excitation, so that an internal circuit works, signals are output to judge whether each function of the chip is correct, the excitation is input when a test code is generated for testing the chip, and the function is verified.

7. Testing and debugging the chip: and the test machine drives corresponding excitation into the chip pins according to the specified time sequence according to the information of the test code, and judges whether the chip is abnormal or not by comparing the data output with the output value of the test code.

The system and the method for realizing the chip test solve the error problem of DFT related tools under the condition of meeting the requirement of the minimum pins used by the chip, realize various tests of the chip, and do not need to increase the test pins, thereby reducing the area of the chip as much as possible, controlling the cost, leading the test to be more flexible, controlling the whole chip through the input of individual pins, correspondingly reducing the requirement on a test board card of a test machine table, having simple interface and reducing the cost.

In this specification, the invention has been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A system for implementing chip testing, the system comprising:

the simulation IP module is used for carrying out simulation IP test;

a digital module connected to the analog IP module for testing internal communication signals, and further comprising: the system comprises a clock reset module, a digital internal insertion scanning chain part, a memory and a self-detection module;

the test module is connected with the analog IP module, the digital module and the input/output unit library and is used for testing the chip; the test module comprises a control pin, the control pin is connected with the input/output unit library through pins of the input/output unit library and is used for controlling different test modes of the chip;

the test module still include:

the port multiplexing test control unit is connected with the input and output unit library and is used for controlling the input and output of the PAD and the analog/digital selection;

the port selection control unit is connected with the input and output unit library and is used for transmitting a normal input pin signal of the PAD to the glue _ scan module in a normal function mode; in a test mode, transmitting a test signal on a PAD input pin to a test module test _ ctrl _ top;

the port multiplexing test control unit is divided into a normal function mode control state and a test mode control state;

when the system enters a test mode control state, the selection of different test modes is realized by addressing the I2C device, and different device addresses correspond to different test modes.

2. A method for implementing chip testing based on the system of claim 1, the method comprising the following steps:

(1-1) selecting a functional mode and a test mode through the control pin;

and (1-4) inputting corresponding excitation into chip pins according to the information of the test code and a specified time sequence, and judging chip abnormality according to data output and the output value of the test code.

3. The method for realizing chip testing according to claim 2, wherein the step (1-1) comprises the following steps:

4. The method for realizing chip testing according to claim 2, wherein the steps (1-3) specifically comprise the following steps:

(1-3.1) judging whether the scan chain of the emulated netlist is normal or not according to the scan chain mode, if so, generating a test vector, otherwise, continuing the step (1-1);

5. The method for implementing chip testing according to claim 2, wherein the method further comprises wafer testing and final testing, and specifically comprises the following steps:

(2-1) performing a contact test;

(2-2) performing a standby current test and a working current test;

(2-3) carrying out scan chain test and memory self-test;

and (2-4) performing a clock reset test and each analog IP test.

6. The method for implementing chip testing according to claim 2, wherein the method further comprises a specific step of entering a test mode, specifically comprising the steps of:

(3-1) designing an analog/digital multiplexing pin;

7. The method for implementing chip testing according to claim 2, wherein the method further comprises a specific step of entering a test mode, specifically comprising the steps of:

(4-1) typing a test mode code into the pin;

and (4-2) entering a test mode through decoding.