CN216672860U - Four-switch control circuit - Google Patents
Four-switch control circuit Download PDFInfo
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- CN216672860U CN216672860U CN202121317130.XU CN202121317130U CN216672860U CN 216672860 U CN216672860 U CN 216672860U CN 202121317130 U CN202121317130 U CN 202121317130U CN 216672860 U CN216672860 U CN 216672860U
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Abstract
The utility model provides a four-switch control circuit, comprising: the first sub-circuit comprises a first MOS tube, a second MOS tube, a third MOS tube and a fourth MOS tube; the second sub-circuit comprises a comparison module and a trigger module; a third sub-circuit; the first sub-circuit is connected to the first input end of the adding unit, the third sub-circuit is connected to the second input end of the adding unit, the second sub-circuit is connected to the output end of the adding unit, and the voltage of the first sub-circuit and the voltage of the third sub-circuit are added to the second sub-circuit; and the fourth sub-circuit is connected to the first sub-circuit and comprises an operational amplifier, and the second sub-circuit adopts the output voltage of the operational amplifier.
Description
Technical Field
The utility model relates to the field of circuits, in particular to a four-switch control circuit.
Background
The four-switch buck-boost converter can work in buck, buck-boost and boost modes, so that the output can be kept stable when the input voltage is greater than, close to or less than the output voltage;
however, the four-switch circuit is not easy to control, and the existing four-switch control circuit is too complicated and has higher cost.
SUMMERY OF THE UTILITY MODEL
The utility model aims to provide a four-switch control circuit.
The utility model aims to solve the problems of the existing four-switch control circuit.
Compared with the prior art, the technical scheme and the beneficial effects of the utility model are as follows:
a four-switch control circuit comprising: the first sub-circuit comprises a first MOS tube, a second MOS tube, a third MOS tube and a fourth MOS tube; the second sub-circuit comprises a comparison module and a trigger module; a third sub-circuit; the first sub-circuit is connected to the first input end of the adding unit, the third sub-circuit is connected to the second input end of the adding unit, the second sub-circuit is connected to the output end of the adding unit, and the voltage of the first sub-circuit and the voltage of the third sub-circuit are added to the second sub-circuit; and the fourth sub-circuit is connected to the first sub-circuit and comprises an operational amplifier, and the second sub-circuit adopts the output voltage of the operational amplifier.
As a further improvement, the drain of the first MOS transistor is connected to the voltage input end, the drain of the first MOS transistor is connected to the first input end of the adding unit, the drain of the second MOS transistor is connected to the source of the first MOS transistor, the source of the second MOS transistor is grounded, the drain of the third MOS transistor is connected to the voltage output end, the drain of the fourth MOS transistor is connected to the source of the third MOS transistor, and the source of the fourth MOS transistor is grounded.
As a further improvement, the first sub-circuit further includes: one end of the first capacitor is connected to the voltage input end, and the other end of the first capacitor is grounded; one end of the second capacitor is connected to the voltage output end, and the other end of the second capacitor is grounded; and one end of the inductor is connected to the source electrode of the first MOS tube, and the other end of the inductor is connected to the source electrode of the third MOS tube.
As a further improvement, the comparison module comprises: a positive phase input terminal of the first comparator is connected to the output terminal of the addition unit; the inverting input end of the second comparator is connected to the inverting input end of the first comparator; the positive phase input end of the voltage amplifier is connected to the positive phase input end of the first comparator, and the negative phase input end of the voltage amplifier is grounded; and the first difference calculation units are connected to the inverting input end of the first comparator and the inverting input end of the second comparator.
As a further improvement, the trigger module comprises: a first end of the first trigger is connected to a clock signal end, a second end of the first trigger is connected to an output end of the first comparator, a third end of the first trigger is connected to a grid electrode of the first MOS transistor, and a fourth end of the first trigger is connected to a grid electrode of the second MOS transistor; the first end of the second trigger is connected to the clock signal end, the second end of the second trigger is connected to the output end of the second comparator, the third end of the second trigger is connected to the grid electrode of the fourth MOS tube, and the fourth end of the second trigger is connected to the grid electrode of the third MOS tube.
As a further improvement, the third sub-circuit includes: a current source; one end of the third capacitor is connected to the current source, and the other end of the third capacitor is grounded; and the control switch is connected in parallel with the third capacitor, and the control end of the control switch is connected to the grid electrode of the second MOS tube.
As a further improvement, the fourth dividing circuit further comprises: one end of the first resistor is connected to a voltage output end, and the other end of the first resistor is connected to a negative phase input end of the operational amplifier; one end of the second resistor is connected to the negative phase input end of the operational amplifier, and the other end of the second resistor is grounded; the positive pole of the power supply is connected to the positive phase input end of the operational amplifier, and the negative pole of the power supply is grounded; one end of the third resistor is connected to the output end of the operational amplifier; and one end of the fourth capacitor is connected to the third resistor, and the other end of the fourth capacitor is grounded.
As a further refinement, the comparison module includes: a positive phase input terminal of the first comparator is connected to the output terminal of the addition unit; a positive phase input end of the second comparator is connected to the positive phase input end of the first comparator; a first difference calculation unit connected to an inverting input terminal of the first comparator; and the second difference calculation unit is connected to the inverting input end of the second comparator.
As a further improvement, the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor are all N-channel MOS transistors.
The utility model has the beneficial effects that: the method for staggering the peak comparison values of Buck and Boost leg is adopted to realize closed-loop control of the four-switch circuit, the design is ingenious, the control method is simple and easy to realize, and the cost of the four-switch control circuit is reduced.
Drawings
Fig. 1 is a circuit diagram of a four-switch circuit.
Fig. 2 is a circuit diagram of a four-switch control circuit according to an embodiment of the present invention.
Fig. 3 is a diagram of logic control signals of the Buck-Boost and MOSFET driving waveforms provided in an embodiment of the present invention.
Fig. 4 is a waveform diagram of a MOSFET driving signal and an inductor current of a Buck-Boost according to an embodiment of the present invention when an input voltage is greater than an output voltage.
Fig. 5 is a waveform diagram of a MOSFET driving signal and an inductor current of a Buck-Boost according to an embodiment of the present invention when an input voltage is less than an output voltage.
Fig. 6 is a circuit diagram of a four-switch control circuit according to a second embodiment of the present invention.
Fig. 7 is a diagram of logic control signals and MOSFET driving waveforms of Buck-Boost according to a second embodiment of the present invention.
In the figure:
1. first sub-circuit 2, second sub-circuit 21, first comparator
22. Second comparator 23, voltage amplifier 24, first flip-flop
25. Second flip-flop 26, first difference calculating unit 27, second difference calculating unit
3. Third shunting circuit 31, current source 32, control switch
4. Fourth divider 41, first resistor 42, second resistor
43. Third resistor 44, fourth capacitor 5, and summing unit
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings of the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the utility model, as claimed, but is merely representative of selected embodiments of the utility model. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
Example one
Referring to fig. 1, MOSFETs Q1 and Q2 are Buck Leg MOSFETs, and MOSFETs Q3 and Q4 are Boost Leg MOSFETs.
When the Q1 is normally on, the Q2 is normally off, and the Q3 and the Q4 are alternately turned on, the circuit works in a Boost mode;
when the Q3 is normally on, the Q4 is normally off, and the Q1 and the Q2 are alternately turned on, the circuit works in a Buck mode;
when Q1 and Q2 are alternately conducted and Q3 and Q4 are alternately conducted, the circuit works in a Buck-Boost mode;
the driving signals of Q1 and Q2 are complementary, and the driving signals of Q3 and Q4 are complementary; the duty ratio of the conduction of the Q1 is set as D1, the duty ratio of the conduction of the Q4 is set as D2, and the switching frequency of the Q1 is obtained according to the magnetic balance of the inductive current in one switching period
VIN×D1＝VOUT×(1-D2)
Namely:
referring to fig. 2, a four-switch control circuit includes: the first sub-circuit 1 comprises a first MOS tube Q1, a second MOS tube Q2, a third MOS tube Q3 and a fourth MOS tube Q4; the second subcircuit 2 comprises a comparison module and a trigger module; a third subcircuit 3; an adding unit 5, wherein the first sub-circuit 1 is connected to a first input end of the adding unit 5, the third sub-circuit 3 is connected to a second input end of the adding unit 5, the second sub-circuit 2 is connected to an output end of the adding unit 5, and the voltage of the first sub-circuit 1 and the voltage of the third sub-circuit 3 are added to the second sub-circuit 2; and the fourth sub-circuit 4 is connected to the first sub-circuit 1, the fourth sub-circuit 4 comprises an operational amplifier GM, and the second sub-circuit 2 adopts the output voltage of the operational amplifier GM.
The drain of the first MOS transistor Q1 is connected to a voltage input terminal, the drain of the first MOS transistor Q1 is connected to the first input terminal of the adding unit, the drain of the second MOS transistor Q2 is connected to the source of the first MOS transistor Q1, the source of the second MOS transistor Q2 is grounded, the drain of the third MOS transistor Q3 is connected to a voltage output terminal, the drain of the fourth MOS transistor Q4 is connected to the source of the third MOS transistor Q3, and the source of the fourth MOS transistor Q4 is grounded.
The first sub-circuit 1 further includes: a first capacitor CINSaid first capacitor CINIs connected to the voltage input terminal, the first capacitor CINThe other end of the first and second electrodes is grounded; a second capacitor COUTSaid second capacitor COUTIs connected to the voltage output terminal, the second capacitor COUTThe other end of the first and second electrodes is grounded; inductor LMSaid inductance LMIs connected to the source of the first MOS transistor Q1, the inductor LMAnd the other end of the third transistor is connected to the source of the third MOS transistor Q3.
The comparison module comprises: a first comparator 21, a non-inverting input terminal of the first comparator 21 being connected to an output terminal of the adding unit 5; a second comparator 22, an inverting input terminal of the second comparator 22 being connected to an inverting input terminal of the first comparator 21; a voltage amplifier 23, a non-inverting input terminal of the voltage amplifier 23 being connected to the non-inverting input terminal of the first comparator 21, and an inverting input terminal of the voltage amplifier 23 being grounded; first difference calculating units 26, the first difference calculating units 26 are connected to the inverting input terminal of the first comparator 21 and the inverting input terminal of the second comparator 22.
The trigger module includes: a first flip-flop 24, a first terminal of the first flip-flop 24 is connected to a clock signal terminal, a second terminal of the first flip-flop 24 is connected to the output terminal of the first comparator 21, a third terminal of the first flip-flop 24 is connected to the gate of the first MOS transistor Q1, and a fourth terminal of the first flip-flop 24 is connected to the gate of the second MOS transistor Q2; a second flip-flop 25, a first terminal of the second flip-flop 25 is connected to the Clock signal terminal Clock, a second terminal of the second flip-flop 25 is connected to the output terminal of the second comparator 22, a third terminal of the second flip-flop 25 is connected to the gate of the fourth MOS transistor Q4, and a fourth terminal of the second flip-flop 25 is connected to the gate of the third MOS transistor Q3. The first flip-flop 24 and the second flip-flop 25 are both RS flip-flops.
The third sub-circuit 3 includes: a current source 31; third capacitor CRAMPSaid third capacitance CRAMPIs connected to the current source 31, the third capacitor CRAMPThe other end of the first and second electrodes is grounded; a control switch 32, the control switch 32 being connected in parallel to the third capacitor CRAMPAnd the control end of the control switch 32 is connected to the gate of the second MOS transistor Q2.
The fourth sub-circuit further includes: a first resistor 41, one end of the first resistor 41 being connected to a voltage output terminal, and the other end of the first resistor 41 being connected to a negative phase input terminal of the operational amplifier GM; a second resistor 42, wherein one end of the second resistor 42 is connected to the negative phase input end of the operational amplifier GM, and the other end of the second resistor 42 is grounded; the positive electrode of the power supply Vref is connected to the positive phase input end of the operational amplifier GM, and the negative electrode of the power supply Vref is grounded; a third resistor 43, one end of the third resistor 43 being connected to the output terminal of the operational amplifier GM; and a fourth capacitor 44, wherein one end of the fourth capacitor 44 is connected to the third resistor 43, and the other end of the fourth capacitor 44 is grounded.
The first MOS transistor Q1, the second MOS transistor Q2, the third MOS transistor Q3 and the fourth MOS transistor Q4 are all N-channel MOS transistors.
Referring to fig. 2 to 5, the output voltage is divided by a voltage dividing resistor and then compared with a reference voltage Vref to generate an error amplification signal VCOMPThen, V is adjustedCOMPApplying a bias voltage VCOMP_ZCComparing the current sampling value with the current sampling value to control the drive of the MOSFET;
the circuit adopts the current of a Buck Leg tube, adds the current sample to a harmonic compensation value to generate a sampling value of a Buck loop, multiplies the sampling value of the Buck loop by n (n is more than 1) to form a sampling value of a Boost loop, and combines the two values with the same error amplification value VCOMP-VCOMP_ZC(VCOMP_ZCIs a bias voltage) are compared;
when the clock arrives, the circuit can turn on Q1 and Q4 of Buck Leg and Boost Leg; because the sampling value of the Boost is n times of Buck, the sampling value of the Boost is compared with V firstlyCOMP-VCOMP_ZCThe comparator output will reset the second flip-flop 25 of Boost, so Q4 of Boost Leg is closed and Q3 is open; then, the sampled value of Buck is compared to VCOMP-VCOMP_ZCThe comparator output will reset Buck's first flip-flop 24, turn off Q1, turn on Q2; until the next clock arrives, Q2 and Q3 of Buck Leg and Boost Leg are closed at the same time, and Q1 and Q4 are opened; (ii) a
When the output voltage is higher, the output V of GMCOMPWill drop so that D1, D2 become smaller and VOUT will drop according to equation (1); when the output voltage is low, the output V of GMCOMPWill rise, making D1, D2 bigger, VOUT will rise according to equation (1); the circuit realizes closed-loop feedback control;
referring to fig. 3 to 4, the operating timing of the circuit is as follows: q1 and Q4 are switched on, and Q2 and Q3 are switched off; q4 off, Q3 on; q1 is off and Q2 is on.
Example two
Referring to fig. 6, the difference between the present embodiment and the first embodiment is that the comparing module includes: a first comparator 21, a non-inverting input terminal of the first comparator 21 being connected to an output terminal of the adding unit; a second comparator 22, wherein a non-inverting input terminal of the second comparator 22 is connected to a non-inverting input terminal of the first comparator 21; a first difference calculation unit 26, wherein the first difference calculation unit 26 is connected to the inverting input terminal of the first comparator 21; a second difference calculation unit 27, said second difference calculation unit 27 being connected to an inverting input of said second comparator 22.
As shown in fig. 6 to 7, the output voltage is divided by the voltage dividing resistor and then compared with the reference voltage Vref to generate the error amplification signal VCOMPWill VCOMPApplying a bias voltage VCOMP_ZCComparing the current sampling value with the Buck Leg MOSFET to control the drive of the Buck Leg MOSFET; will VCOMPApplying a bias voltage VCOMP_ZCAnd VB (VB is the difference value of comparison voltages of Buck Leg and Boost Leg) and a current sampling value VSENSEComparing and controlling the drive of a Boost Leg MOSFET;
the circuit adopts the current of a Buck Leg upper tube, and a compensated current sampling value V is obtained by adding the current sampling value and a harmonic compensation valueSENSEComparing the current with the comparison voltage of Buck Leg and Boost Leg respectively;
when the clock arrives, the circuit can turn on Q1 and Q4 of Buck Leg and Boost Leg; the comparison value of the Boost comparator is V less than that of the Buck comparatorBThe current sampling value is compared to VCOMP-VCOMP_ZC-VBThe comparator output will reset the second flip-flop 25 of Boost, so Q4 of Boost Leg is closed and Q3 is open; then, the current sampling value is compared to VCOMP-VCOMP_ZCThe comparator output will reset Buck's first flip-flop 24, turn off Q1, turn on Q2; when the next clock arrives, Q2 and Q3 of Buck Leg and Boost Leg are closed at the same time, and Q1 and Q4 are opened;
when the output voltage is higher, the output V of GMCOMPWill drop so that D1, D2 become smaller and VOUT will drop according to equation (1); when the output voltage is low, the output V of GMCOMPWill rise so that D1, D2 become bigger according to the formula (1)VOUT will rise; the circuit realizes closed-loop feedback control.
The working principle, working process and the like of the present embodiment can refer to the corresponding contents of the foregoing embodiments.
The above examples are only for illustrating the technical solution of the present invention and not for limiting the same. It will be understood by those skilled in the art that any modifications and equivalents may be made thereto without departing from the spirit and scope of the present invention as set forth in the appended claims.
Claims (9)
1. A four-switch control circuit, comprising:
the first sub-circuit comprises a first MOS tube, a second MOS tube, a third MOS tube and a fourth MOS tube;
the second sub-circuit comprises a comparison module and a trigger module;
a third sub-circuit;
the first sub-circuit is connected to the first input end of the adding unit, the third sub-circuit is connected to the second input end of the adding unit, the second sub-circuit is connected to the output end of the adding unit, and the voltage of the first sub-circuit and the voltage of the third sub-circuit are added to the second sub-circuit;
and the fourth sub-circuit is connected to the first sub-circuit and comprises an operational amplifier, and the second sub-circuit adopts the output voltage of the operational amplifier.
2. The four-switch control circuit according to claim 1, wherein a drain of the first MOS transistor is connected to a voltage input terminal, a drain of the first MOS transistor is connected to the first input terminal of the adding unit, a drain of the second MOS transistor is connected to a source of the first MOS transistor, a source of the second MOS transistor is grounded, a drain of the third MOS transistor is connected to a voltage output terminal, a drain of the fourth MOS transistor is connected to a source of the third MOS transistor, and a source of the fourth MOS transistor is grounded.
3. A four-switch control circuit according to claim 2, wherein the first sub-circuit further comprises:
one end of the first capacitor is connected to the voltage input end, and the other end of the first capacitor is grounded;
one end of the second capacitor is connected to the voltage output end, and the other end of the second capacitor is grounded;
and one end of the inductor is connected to the source electrode of the first MOS tube, and the other end of the inductor is connected to the source electrode of the third MOS tube.
4. A four-switch control circuit according to claim 2, wherein the comparing module comprises:
a positive phase input end of the first comparator is connected to the output end of the addition unit;
the inverting input end of the second comparator is connected to the inverting input end of the first comparator;
the positive phase input end of the voltage amplifier is connected to the positive phase input end of the first comparator, and the negative phase input end of the voltage amplifier is grounded;
and the first difference calculation units are connected to the inverting input end of the first comparator and the inverting input end of the second comparator.
5. A four-switch control circuit according to claim 4, wherein the trigger module comprises:
a first end of the first trigger is connected to a clock signal end, a second end of the first trigger is connected to an output end of the first comparator, a third end of the first trigger is connected to a grid electrode of the first MOS transistor, and a fourth end of the first trigger is connected to a grid electrode of the second MOS transistor;
the first end of the second trigger is connected to the clock signal end, the second end of the second trigger is connected to the output end of the second comparator, the third end of the second trigger is connected to the grid electrode of the fourth MOS tube, and the fourth end of the second trigger is connected to the grid electrode of the third MOS tube.
6. A four-switch control circuit according to claim 1, wherein the third divide circuit comprises:
a current source;
one end of the third capacitor is connected to the current source, and the other end of the third capacitor is grounded;
and the control switch is connected in parallel with the third capacitor, and the control end of the control switch is connected to the grid electrode of the second MOS tube.
7. A four-switch control circuit as claimed in claim 1, wherein the fourth divide circuit further comprises:
one end of the first resistor is connected to a voltage output end, and the other end of the first resistor is connected to a negative phase input end of the operational amplifier;
one end of the second resistor is connected to the negative phase input end of the operational amplifier, and the other end of the second resistor is grounded;
the positive pole of the power supply is connected to the positive phase input end of the operational amplifier, and the negative pole of the power supply is grounded;
one end of the third resistor is connected to the output end of the operational amplifier;
and one end of the fourth capacitor is connected to the third resistor, and the other end of the fourth capacitor is grounded.
8. A four-switch control circuit according to claim 2, wherein the comparing module comprises:
a positive phase input end of the first comparator is connected to the output end of the addition unit;
a positive phase input end of the second comparator is connected to the positive phase input end of the first comparator;
a first difference calculation unit connected to an inverting input terminal of the first comparator;
and the second difference calculation unit is connected to the inverting input end of the second comparator.
9. The four-switch control circuit according to claim 1, wherein the first MOS transistor, the second MOS transistor, the third MOS transistor and the fourth MOS transistor are all N-channel MOS transistors.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113422512A (en) * | 2021-06-11 | 2021-09-21 | 英麦科（厦门）微电子科技有限公司 | Four-switch control circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113422512A (en) * | 2021-06-11 | 2021-09-21 | 英麦科（厦门）微电子科技有限公司 | Four-switch control circuit |
| CN113422512B (en) * | 2021-06-11 | 2024-05-07 | 拓尔微电子股份有限公司 | Four-switch control circuit |
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