CN216526087U - Crystal oscillator failure detection circuit for suppressing power supply noise - Google Patents
Crystal oscillator failure detection circuit for suppressing power supply noise Download PDFInfo
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- CN216526087U CN216526087U CN202122927911.7U CN202122927911U CN216526087U CN 216526087 U CN216526087 U CN 216526087U CN 202122927911 U CN202122927911 U CN 202122927911U CN 216526087 U CN216526087 U CN 216526087U
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Abstract
The utility model discloses a crystal oscillator failure detection circuit for suppressing power supply noise, which comprises a dummy branch, a failure detection module and a crystal oscillator; and generating a reference voltage VREF by using a dummy branch of the main oscillation circuit, wherein the reference voltage VREF is used as a reference voltage of the failure detection module, and the reference voltage is compared with an input pin signal XI _ OUT of the crystal oscillator to obtain a failure detection judgment result. The branch where the first NMOS transistor M1 is located is a main branch where the crystal oscillator oscillates to provide current, and the branch where the second NMOS transistor M0 is located is a dummy branch; the first current source I1 and the second current source I0 are a set of matched current mirror structures, and the first NMOS transistor M1 and the second NMOS transistor M0 are a set of matched NMOS transistors, so that the first NMOS transistor M1 and the second NMOS transistor M0 have the same VDS. According to the utility model, the dummy branch of the main oscillation circuit is used for generating reference voltage to carry out failure detection judgment, and VREF = VDS + R0I 0 reference voltage changes along with the process angle, so that the failure detection result depends on the size of R0I 0, and therefore the change of the process angle does not influence the failure detection judgment result.
Description
Technical Field
The utility model relates to the technical field of semiconductors, in particular to a crystal oscillator failure detection circuit for suppressing power supply noise.
Background
Because the crystal oscillator has the characteristics of high stability and high precision, the crystal oscillator is generally used as a clock source in the MCU. The operation state of the crystal oscillator is related to the state of the whole chip clock, so a detection circuit is needed to indicate the operation state of the crystal oscillator. When the crystal oscillator stops vibrating due to some accidental conditions (similar to the conditions of crystal pin breakage and the like), the detection circuit can give out reliable indication signals in time, and the MCU can know to carry out related operations, so that the system cannot run away.
In the MCU, the structure of the crystal oscillator is usually composed of a crystal outside the chip and a start-up circuit inside the chip, so the module has a PAD pin requiring ESD (electrostatic protection) processing. Due to the fact that the ESD tube is large in size, large parasitic capacitance can couple power supply noise to pins of the crystal oscillator, and detection results of the crystal oscillator failure detection circuit are affected after the power supply noise is amplified by an internal amplifier of the crystal oscillator.
At present, most of designs adopt a signal obtained by carrying out operational amplification on signals of input and output pins of a crystal oscillator as an input decision signal of a crystal oscillator failure detection circuit, as shown in fig. 3, however, because the operational amplification has a certain gain, input noise can be amplified, and thus the decision result of the failure detection circuit is influenced. Another implementation compares the signal at the input pin of the crystal oscillator with a fixed reference voltage, as shown in fig. 4, but since the DC point of the oscillation start circuit of the crystal oscillator varies with the process angle, and the reference voltage does not substantially vary with the process angle, the decision result of the failure detection circuit is affected.
SUMMERY OF THE UTILITY MODEL
In order to solve the defects in the prior art, the utility model aims to provide a crystal oscillator failure detection circuit for suppressing power supply noise, which utilizes a dummy branch of a main oscillation circuit to generate a reference voltage, thereby solving the problem of power supply noise and the problem of fluctuation along with a process angle.
In order to realize the purpose of the utility model, the technical scheme adopted by the utility model is as follows:
a crystal oscillator failure detection circuit for suppressing power supply noise comprises a dummy branch, a failure detection module and a crystal oscillator;
the failure detection module comprises input signals XI _ OUT and VREF, wherein the input signals XI _ OUT are signals of an input pin of the crystal oscillator, and the input signals VREF are reference voltage signals generated by a dummy branch circuit; outputting a signal OSC _ FAIL which is a failure detection judgment result;
the crystal oscillator comprises a first current source I1 and a first NMOS transistor M1 which are connected in series;
the dummy branch comprises a second current source I0, a second resistor R0 and a second NMOS transistor M0 which are connected in series; the output end of the second current source I0 is connected to the first end of the second resistor R0, the second end of the second resistor R0 is connected to the drain of the second NMOS transistor M0, and the source of the second NMOS transistor M0 is grounded; the drain electrode and the gate electrode of the second NMOS tube M0 are connected; a first end of the second resistor R0 generates a reference voltage VREF;
the first current source I1 and the second current source I0 are a set of matched current mirror structures, the first NMOS transistor M1 and the second NMOS transistor M0 are a set of matched NMOS transistors, and the first NMOS transistor M1 and the second NMOS transistor M0 have the same source-drain voltage VDS.
Further, the first current source I1 and the first NMOS transistor M1 are connected in series to form a branch for the crystal oscillator to oscillate and supply current; the output end of the first current source I1 is connected to the drain of the first NMOS transistor M1, and the source of the first NMOS transistor M1 is grounded; a first resistor R1 is connected between the drain electrode and the grid electrode of the first NMOS tube M1, the drain electrode of the first NMOS tube M1 forms a pin XO through ESD, the grid electrode of the first NMOS tube M1 forms a pin XI through ESD, and two ends of the pin XO and the pin XI are connected with an oscillation crystal; the gate of the first NMOS transistor M1 generates the signal XI _ OUT at the input pin of the crystal oscillator.
Further, the reference voltage VREF = VDS + R0 × I0.
Further, the failure detection module includes a first operational amplifier COMP1, a signal of a positive input end of the first operational amplifier COMP1 is XI _ OUT, a signal of a negative input end of the first operational amplifier COMP 3832 is VREF, and an output end of the first operational amplifier COMP1 is connected to gates of a third PMOS transistor M3 and a fourth NMOS transistor M4;
the power supply also comprises a third current source I3, a third PMOS tube M3, a fourth NMOS tube M4 and a fourth current source I4 which are connected in series, wherein the output end of the third current source I3 is connected with the source electrode of the third PMOS tube M3, the drain electrode of the third PMOS tube M3 is connected with the drain electrode of the fourth NMOS tube M4, the source electrode of the fourth NMOS tube M4 is connected with the input end of the fourth current source I4, the output end of the fourth current source I4 is grounded, and the gates of the third PMOS tube M3 and the fourth NMOS tube M4 are connected in series;
the connection point of the drain electrode of the third PMOS tube M3 and the drain electrode of the fourth NMOS tube M4 forms an output voltage V0, and is grounded through a capacitor C0; the output voltage V0 outputs a signal OSC _ FAIL through the buffer circuit as a failure detection determination result.
Further, when the crystal oscillator is not oscillating, XI _ OUT = VDS, XI _ OUT < VREF, the output of the first comparator COMP1 is 0, and the output voltage V0=1 through the inverter formed by the third PMOS transistor M3 and the fourth NMOS transistor M4, OSC _ FAIL =1, which indicates that the crystal oscillator is not oscillating normally.
When the crystal oscillator starts oscillation and the oscillation amplitude is higher than VREF, the output of the first comparator COMP1 is inverted between 0 and 1, the third current source I3, the third PMOS transistor M3, the fourth NMOS transistor M4, the fourth current source I4 and the capacitor C0 connected in series form an RC filter circuit, and the magnitudes of the currents I3, I4 and the capacitance C0 are reasonably designed, so that the output voltage V0 is at a low level, and then OSC _ FAIL =0, which indicates that the crystal oscillator starts oscillation normally.
Further, a first end of the first resistor R1 is connected to the positive input terminal of the first operational amplifier COMP0, a second end of the first resistor R1 is connected to the negative input terminal of the second operational amplifier COMP0, and an output terminal OSC _ OUT of the second operational amplifier COMP0 is an output clock signal source.
Further, the width of the single finger structures of the first NMOS transistor M1 and the second NMOS transistor M0 is completely the same, and the placement on the layout is completely matched.
Compared with the prior art, the failure detection circuit has the advantages that the failure detection judgment is carried out by utilizing the reference voltage generated by the dummy branch of the main oscillation circuit, the voltage of the input pin of the crystal oscillator and the reference voltage are the same along with the change of the process angle, so that the result of the failure detection module depends on the size of R0I 0, and the judgment result of the failure detection circuit cannot be influenced by the change of the process angle. Meanwhile, compared with the prior art shown in fig. 3, the noise existing on the power supply cannot be amplified, and the judgment result output by the comparator cannot be influenced by reasonably designing the value of VREF.
Drawings
FIG. 1 is a schematic diagram of a crystal oscillator failure detection circuit that suppresses power supply noise;
FIG. 2 is a waveform diagram of the operation of a crystal oscillator failure detection circuit for suppressing power supply noise;
FIG. 3 is a circuit schematic of a first prior art arrangement;
fig. 4 is a circuit schematic of a second prior art arrangement.
Detailed Description
The technical solution of the present invention is further described below with reference to the accompanying drawings and examples. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present application is not limited thereby.
As shown in fig. 1, the crystal oscillator failure detection circuit for suppressing power supply noise according to the present invention includes a dummy branch, a failure detection module, and a crystal oscillator.
The crystal oscillator comprises a crystal outside a chip and a starting circuit inside the chip, wherein the starting circuit inside the chip comprises a branch circuit which is formed by a first current source I1 and a first NMOS transistor M1 which are connected in series and is used for providing required current for oscillation of the crystal oscillator, the output end of the first current source I1 is connected with the drain electrode of the first NMOS transistor M1, and the source electrode of the first NMOS transistor M1 is grounded; the drain and the gate of the first NMOS transistor M1 are connected to a first resistor R1.
The first end (the drain of the first NMOS transistor M1) of the first resistor R1 forms a pin XO through an ESD (electrostatic protection circuit), the second end (the gate of the first NMOS transistor M1) of the first resistor R1 forms a pin XI through an ESD (electrostatic protection circuit), and two ends of the pins XO and XI are connected to an oscillation crystal outside the chip.
A first end of the first resistor R1 is connected to the positive input end of the first operational amplifier COMP0, a second end of the first resistor R1 is connected to the negative input end of the second operational amplifier COMP0, and an output end pin OSC _ OUT of the second operational amplifier COMP0 is an output clock signal source.
The dummy branch comprises a second current source I0, a second resistor R0 and a second NMOS transistor M0 which are connected in series, the output end of the second current source I0 is connected with the first end of a second resistor R0, the second end of the second resistor R0 is connected with the drain electrode of the second NMOS transistor M0, and the source electrode of the second NMOS transistor M0 is grounded; the drain and the gate of the second NMOS transistor M0 are connected.
The branch where the first NMOS transistor M1 is located is a main branch where the crystal oscillator oscillates to provide a required current, and the branch where the second NMOS transistor M0 is located is a dummy branch, and is mainly used for providing a reference voltage for the failure detection module. The first current source I1 and the second current source I0 are a group of matched current mirror structures, the first NMOS transistor M1 and the second NMOS transistor M0 are a group of matched NMOS transistors, the width of a single finger (finger insertion structure) is identical, the placement on the layout is also completely matched, and the NMOS transistors M0 and M1 have the same source-drain voltage VDS through the design of the current mirror I0.
The second resistor R0 is connected to the drain of the second NMOS transistor M0 to generate a reference voltage VREF, VREF = VDS + R0 × I0, and VREF and XI _ OUT are inputs of the failure detection module.
Since M0 and M1 are closely matched on the layout, the variation of M0 and M1 with process corner is the same, so the result of the failure detection module depends only on the size of R0I 0.
The failure detection module comprises a first operational amplifier COMP1, a signal of a positive input end of the first operational amplifier COMP1 is XI _ OUT, a signal of a negative input end of the first operational amplifier COMP1 is VREF, and an output end of the first operational amplifier COMP1 is connected with gates of a third PMOS tube M3 and a fourth NMOS tube M4.
The failure detection module comprises a third current source I3, a third PMOS tube M3, a fourth NMOS tube M4 and a failure detection main branch circuit formed by connecting the fourth current source I4 in series, wherein the output end of the third current source I3 is connected with the source electrode of the third PMOS tube M3, the drain electrode of the third PMOS tube M3 is connected with the drain electrode of the fourth NMOS tube M4, the source electrode of the fourth NMOS tube M4 is connected with the input end of the fourth current source I4, the output end of the fourth current source I4 is grounded, and the gates of the third PMOS tube M3 and the fourth NMOS tube M4 are connected.
The connection point of the drain electrode of the third PMOS tube M3 and the drain electrode of the fourth NMOS tube M4 forms an output voltage V0, and is grounded through a capacitor C0; the output voltage V0 outputs the signal OSC _ FAIL through the buffer circuit as the detection result of the failure detection circuit. The buffer circuit may employ a schmitt trigger.
As shown in fig. 2, in the operation process of the crystal oscillator failure detection circuit for suppressing power supply noise according to the present invention, when the crystal oscillator is not vibrating, XI _ OUT = VDS; therefore, XI _ OUT < VREF, the output of the first comparator COMP1 is 0, the output of the first comparator COMP1 passes through the inverter formed by M3 and M4, the output voltage V0 is 1, OSC _ FAIL =1, which indicates that the crystal oscillator is not normally started, and otherwise, the crystal oscillator is normally started.
Assuming that there is noise on the power supply, the output of the first comparator COMP1 remains 0 as long as the value of VREF is reasonably designed.
When the crystal oscillator starts oscillation and the oscillation amplitude is higher than VREF, the output of the first comparator COMP1 will be inverted between 0 and 1, and at this time, the output of the first comparator COMP1 is similar to an ac signal with a certain frequency, and at this time, the series-connected third current source I3, third PMOS transistor M3, fourth NMOS transistor M4, fourth current source I4 and capacitor C0 form an RC filter circuit, and the magnitudes of currents of I3 and I4 and the capacitance of C0 are designed reasonably, so that the output voltage V0 is low, and OSC _ FAIL =0 indicates that the crystal oscillator starts oscillation normally.
Compared with the prior art, the failure detection circuit has the advantages that the failure detection judgment is carried out by utilizing the reference voltage generated by the dummy branch of the main oscillation circuit, the reference voltage changes along with the process angle, so that the result of the failure detection module depends on the size of R0I 0, and the judgment result of the failure detection circuit cannot be influenced by the change of the process angle. Meanwhile, noise existing on a power supply does not influence a judgment result output by the comparator through reasonably designing the VREF value.
The present applicant has described and illustrated embodiments of the present invention in detail with reference to the accompanying drawings, but it should be understood by those skilled in the art that the above embodiments are merely preferred embodiments of the present invention, and the detailed description is only for the purpose of helping the reader to better understand the spirit of the present invention, and not for limiting the scope of the present invention, and on the contrary, any improvement or modification made based on the spirit of the present invention should fall within the scope of the present invention.
Claims (6)
1. A crystal oscillator failure detection circuit for suppressing power supply noise, characterized by: the device comprises a dummy branch, a failure detection module and a crystal oscillator;
the failure detection module comprises input signals XI _ OUT and VREF, wherein the input signals XI _ OUT are signals of an input pin of the crystal oscillator, and the input signals VREF are reference voltage signals generated by a dummy branch; outputting a signal OSC _ FAIL which is a failure detection judgment result;
the crystal oscillator comprises a first current source I1 and a first NMOS transistor M1 which are connected in series;
the dummy branch comprises a second current source I0, a second resistor R0 and a second NMOS transistor M0 which are connected in series; the output end of the second current source I0 is connected to the first end of the second resistor R0, the second end of the second resistor R0 is connected to the drain of the second NMOS transistor M0, and the source of the second NMOS transistor M0 is grounded; the drain electrode and the grid electrode of the second NMOS tube M0 are connected; a first end of the second resistor R0 generates a reference voltage VREF;
the first current source I1 and the second current source I0 are a group of matched current mirror structures, the first NMOS transistor M1 and the second NMOS transistor M0 are a group of matched NMOS transistors, and the first NMOS transistor M1 and the second NMOS transistor M0 have the same source-drain voltage.
2. The power supply noise suppressing crystal oscillator failure detection circuit of claim 1, wherein:
the first current source I1 and the first NMOS transistor M1 are connected in series to form a branch circuit for providing current for the oscillation of the crystal oscillator; the output end of the first current source I1 is connected to the drain of the first NMOS transistor M1, and the source of the first NMOS transistor M1 is grounded; a first resistor R1 is connected between the drain electrode and the grid electrode of the first NMOS tube M1, the drain electrode of the first NMOS tube M1 forms a pin XO through ESD, the grid electrode of the first NMOS tube M1 forms a pin XI through ESD, and two ends of the pin XO and the pin XI are connected with an oscillation crystal; the gate of the first NMOS transistor M1 generates the signal XI _ OUT at the crystal oscillator input pin.
3. The power supply noise suppressing crystal oscillator failure detection circuit of claim 1, wherein:
reference voltage VREF = VDS + R0 × I0.
4. The power supply noise suppressing crystal oscillator failure detection circuit of claim 3, wherein:
the failure detection module comprises a first operational amplifier COMP1, wherein a signal of a positive input end of the first operational amplifier COMP1 is XI _ OUT, a signal of a negative input end of the first operational amplifier COMP1 is VREF, and an output end of the first operational amplifier COMP1 is connected with gates of a third PMOS tube M3 and a fourth NMOS tube M4;
the power supply also comprises a third current source I3, a third PMOS tube M3, a fourth NMOS tube M4 and a fourth current source I4 which are connected in series, wherein the output end of the third current source I3 is connected with the source electrode of the third PMOS tube M3, the drain electrode of the third PMOS tube M3 is connected with the drain electrode of the fourth NMOS tube M4, the source electrode of the fourth NMOS tube M4 is connected with the input end of the fourth current source I4, the output end of the fourth current source I4 is grounded, and the gates of the third PMOS tube M3 and the fourth NMOS tube M4 are connected in series;
the connection point of the drain electrode of the third PMOS tube M3 and the drain electrode of the fourth NMOS tube M4 forms an output voltage V0, and is grounded through a capacitor C0; the output voltage V0 outputs a signal OSC _ FAIL through the buffer circuit as a failure detection determination result.
5. The power supply noise suppressing crystal oscillator failure detection circuit of claim 2, wherein:
a first end of the first resistor R1 is connected to the positive input end of the first operational amplifier COMP0, a second end of the first resistor R1 is connected to the negative input end of the second operational amplifier COMP0, and an output end OSC _ OUT of the second operational amplifier COMP0 is an output clock signal source.
6. The power supply noise suppressing crystal oscillator failure detection circuit of claim 1, wherein:
the width of the single finger inserting structure of the first NMOS tube M1 and the second NMOS tube M0 is completely the same, and the placement on the layout is completely matched.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122927911.7U CN216526087U (en) | 2021-11-26 | 2021-11-26 | Crystal oscillator failure detection circuit for suppressing power supply noise |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122927911.7U CN216526087U (en) | 2021-11-26 | 2021-11-26 | Crystal oscillator failure detection circuit for suppressing power supply noise |
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| Publication Number | Publication Date |
|---|---|
| CN216526087U true CN216526087U (en) | 2022-05-13 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202122927911.7U Active CN216526087U (en) | 2021-11-26 | 2021-11-26 | Crystal oscillator failure detection circuit for suppressing power supply noise |
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| CN (1) | CN216526087U (en) |
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- 2021-11-26 CN CN202122927911.7U patent/CN216526087U/en active Active
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