CN214380843U - Low-frequency oscillation circuit, oscillator, power supply, and electronic device - Google Patents
Low-frequency oscillation circuit, oscillator, power supply, and electronic device Download PDFInfo
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- CN214380843U CN214380843U CN202120639210.0U CN202120639210U CN214380843U CN 214380843 U CN214380843 U CN 214380843U CN 202120639210 U CN202120639210 U CN 202120639210U CN 214380843 U CN214380843 U CN 214380843U
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Abstract
The utility model relates to a low frequency oscillation circuit, oscillator, power and electronic equipment, the circuit includes: the reference current generating module is used for generating reference current; the loop oscillation module is connected to the reference current generation module, and includes a second delay oscillation unit, a first inverter, a second nand gate, and a first nand gate, where the second delay oscillation unit is configured to delay the second signal for a second time according to the reference current, the first delay oscillation unit is configured to delay the first signal for a first time according to the reference current, and an oscillation frequency of the first signal is a reciprocal of a sum of the first time and the second time. The embodiment of the utility model provides an oscillating frequency of the first signal of low frequency oscillation circuit output is relevant with very first time, second time, and is irrelevant with mains voltage, has eliminated mains voltage and has improved oscillating frequency's stability to oscillating frequency's influence.
Description
Technical Field
The utility model relates to an integrated circuit technical field especially relates to a low frequency oscillation circuit, oscillator, power and electronic equipment.
Background
Oscillators (oscillators) are electronic components used to generate repetitive electronic signals (usually sine waves or square waves), and are essential components in electronic devices and circuit designs.
SUMMERY OF THE UTILITY MODEL
In view of this, the present invention provides a low frequency oscillation circuit, the circuit includes:
the reference current generating module is used for generating reference current;
a loop oscillation module connected to the reference current generation module and including a second delay oscillation unit, a first inverter, a second NAND gate, and a first NAND gate,
a first input end of the second delay oscillation unit is connected to an output end of the first inverter for receiving a second signal, an output end of the second delay oscillation unit is connected to a first input end of the second nand gate, a second input end of the second nand gate is connected to an output end of the first nand gate, an output end of the second nand gate is connected to a second input end of the first nand gate and an input end of the second inverter, a first input end of the first nand gate is connected to an output end of the first delay oscillation unit, an input end of the first inverter and a first input end of the first delay oscillation unit are connected to an output end of the second inverter for receiving a first signal,
a second input terminal of the second delay oscillation unit and a second input terminal of the first delay oscillation unit are connected to the reference current generation module, the second delay oscillation unit is configured to delay the second signal for a second time according to the reference current, the first delay oscillation unit is configured to delay the first signal for a first time according to the reference current,
wherein the oscillation frequency of the first signal is the inverse of the sum of the first time and the second time.
In one possible implementation, the reference current generating module comprises a first PMOS transistor, a second PMOS transistor, a resistor, a first NMOS transistor, wherein,
the source of the first PMOS transistor is connected with the source of the second PMOS transistor and used for receiving power supply voltage, the gate of the first PMOS transistor is connected with the gate of the second PMOS transistor, the drain of the first PMOS transistor and the first end of the resistor,
a second terminal of the resistor is connected to the source of the first NMOS transistor and ground,
a drain of the second PMOS transistor is connected to a drain of the first NMOS transistor and a gate of the first NMOS transistor,
wherein the width-to-length ratios of the first PMOS transistor and the second PMOS transistor are the same,
wherein the current flowing through the resistor is the reference current.
In one possible embodiment, the first delay oscillating unit includes a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a second NMOS transistor, a third NMOS transistor, a first capacitor, a third inverter, and a fourth inverter, wherein,
a source of the third PMOS transistor is connected to a source of the fourth PMOS transistor for receiving the supply voltage, a drain of the third PMOS transistor is connected to a source of the fifth PMOS transistor,
a gate of the fifth PMOS transistor is connected to a gate of the second NMOS transistor for receiving the first signal,
the drain of the fifth PMOS transistor is connected to the drain of the second NMOS transistor, the first end of the first capacitor, and the gate of the fourth PMOS transistor,
a source of the second NMOS transistor is connected to the second terminal of the first capacitor, a source of the third NMOS transistor, and ground,
a gate of the third NMOS transistor is connected to a gate of the first NMOS transistor,
the drain of the third NMOS transistor is connected to the drain of the fourth PMOS transistor and the input terminal of the third inverter,
the output end of the third inverter is connected to the input end of the fourth inverter, and the output end of the fourth inverter is connected to the first input end of the first nand gate.
In one possible embodiment, the second delay oscillating unit includes a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a second capacitor, a fifth inverter, and a sixth inverter, wherein,
a gate of the sixth PMOS transistor is connected to the gate of the third PMOS transistor, the gate of the first PMOS transistor, and the gate of the second PMOS transistor, a source of the sixth PMOS transistor is connected to the source of the seventh PMOS transistor for receiving the power supply voltage, a drain of the sixth PMOS transistor is connected to the source of the eighth PMOS transistor,
a gate of the eighth PMOS transistor is connected to a gate of the fourth NMOS transistor for receiving the second signal,
a drain of the eighth PMOS transistor is connected to a drain of the fourth NMOS transistor, the first terminal of the second capacitor, and a gate of the seventh PMOS transistor,
a source of the fourth NMOS transistor is connected to the second terminal of the second capacitor, a source of the fifth NMOS transistor, and ground,
a gate of the fifth NMOS transistor is connected to a gate of the first NMOS transistor,
a drain of the fifth NMOS transistor is connected to a drain of the seventh PMOS transistor and an input terminal of the fifth inverter,
the output end of the fifth inverter is connected to the input end of the sixth inverter, and the output end of the sixth inverter is connected to the first input end of the first nand gate.
In one possible implementation, the width-to-length ratios of the third, fourth, sixth, and seventh PMOS transistors are the same as the width-to-length ratios of the first and second PMOS transistors,
the width-to-length ratios of the first NMOS transistor, the third NMOS transistor and the fifth NMOS transistor are the same.
In one possible embodiment, the first capacitance is the same as the capacitance of the second capacitance.
In a possible embodiment, the oscillation frequency of the first signal is related to the resistance, the first capacitance, and the second capacitance.
According to another aspect of the present invention, an oscillator is provided, the oscillator comprising the low frequency oscillation circuit.
According to another aspect of the present invention, a power supply is provided, the power supply comprising the oscillator.
According to another aspect of the present invention, an electronic device is provided, the electronic device comprising the power supply.
The embodiment of the utility model provides a low frequency oscillation circuit, first delay oscillation unit, second delay oscillation unit all produce the reference current delay signal that the module produced through reference current for the oscillation frequency of the first signal of oscillation circuit output is relevant with very first time, second time, and is irrelevant with mains voltage, has eliminated mains voltage to oscillation frequency's influence, has improved oscillation frequency's stability.
Other features and aspects of the present invention will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the present invention and, together with the description, serve to explain the principles of the invention.
Fig. 1 shows a schematic diagram of a low frequency oscillation circuit according to an embodiment of the present invention.
Fig. 2 shows a schematic diagram of a low frequency oscillation circuit according to an embodiment of the present invention.
Fig. 3 shows a schematic diagram of oscillation time according to an embodiment of the present invention.
Detailed Description
Various exemplary embodiments, features and aspects of the present invention will be described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers can indicate functionally identical or similar elements. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.
In the description of the present invention, it is to be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are used in the orientation or positional relationship indicated in the drawings for convenience in describing the present invention and for simplicity in description, and are not intended to indicate or imply that the device or element so referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically limited otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," and "fixed" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art.
The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.
Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present invention. It will be understood by those skilled in the art that the present invention may be practiced without some of these specific details. In some instances, methods, means, elements and circuits that are well known to those skilled in the art have not been described in detail so as not to obscure the present invention.
Referring to fig. 1, fig. 1 is a schematic diagram of a low frequency oscillation circuit according to an embodiment of the present invention.
As shown in fig. 1, the circuit includes:
a reference current generating module 10 for generating a reference current Ir;
a loop oscillation module 20 connected to the reference current generation module 10 and including a second delay oscillation unit 220, a first delay oscillation unit 210, a first inverter N1, a second inverter N2, a second NAND gate NAND2, and a first NAND gate NAND1, wherein,
a first input terminal of the second delay oscillating unit 220 is connected to an output terminal of the first inverter N1 for receiving a second signal a2, an output terminal of the second delay oscillating unit 220 is connected to a first input terminal of the second NAND gate NAND2, a second input terminal of the second NAND gate NAND2 is connected to an output terminal of the first NAND gate NAND1, an output terminal of the second NAND gate NAND2 is connected to a second input terminal of the first NAND gate NAND1 and an input terminal of the second inverter N2, a first input terminal of the first NAND gate 1 is connected to an output terminal of the first delay oscillating unit 210, an input terminal of the first inverter N1 and a first input terminal of the first delay oscillating unit 210 are connected to an output terminal of the second inverter N2 for receiving a first signal OUT,
a second input terminal of the second delay oscillating unit 220 and a second input terminal of the first delay oscillating unit 210 are connected to the reference current generating module 10, the second delay oscillating unit 220 is configured to delay the second signal a2 for a second time according to the reference current Ir, the first delay oscillating unit 210 is configured to delay the first signal OUT for a first time according to the reference current Ir,
wherein the oscillation frequency of the first signal OUT is an inverse of a sum of the first time and the second time.
The embodiment of the utility model provides a low frequency oscillation circuit, first delay oscillation unit, second delay oscillation unit all produce the reference current delay signal that the module produced through reference current for the oscillation frequency of the first signal of oscillation circuit output is relevant with very first time, second time, and is irrelevant with mains voltage, has eliminated mains voltage to oscillation frequency's influence, has improved oscillation frequency's stability.
In a possible implementation manner, the oscillation circuit of the embodiment of the present invention may further include an output unit for buffering the first signal OUT and then outputting the buffered first signal OUT, and to a specific implementation manner of the output unit, the embodiment of the present invention is not limited.
A possible implementation of the low frequency oscillating circuit is exemplarily described below.
Referring to fig. 2, fig. 2 is a schematic diagram of a low frequency oscillation circuit according to an embodiment of the present invention.
In one possible implementation, as shown in fig. 2, the reference current generating module 10 may include a first PMOS transistor MP1, a second PMOS transistor MP2, a resistor R, and a first NMOS transistor MN1, wherein,
a source of the first PMOS transistor MP1 is connected to a source of the second PMOS transistor MP2 for receiving a power supply voltage VDD, a gate of the first PMOS transistor MP1 is connected to a gate of the second PMOS transistor MP2, a drain of the first PMOS transistor MP1, a first end of the resistor R,
a second terminal of the resistor R is connected to the source of the first NMOS transistor MN1 and ground,
the drain of the second PMOS transistor MP2 is connected to the drain of the first NMOS transistor MN1 and the gate of the first NMOS transistor MN1,
wherein the width-to-length ratios of the first and second PMOS transistors MP1 and MP2 are the same,
wherein the current flowing through the resistor R is the reference current Ir.
Through above reference current generation module, the embodiment of the utility model provides a can produce required reference current, and, through setting first PMOS transistor MP1, second PMOS transistor MP 2's width to length ratio is the same, the embodiment of the utility model provides a can make the electric current Ir0 of the drain end of second PMOS transistor equal with reference current Ir to make follow-up reference current Ir that utilizes realize low frequency oscillation, produce the oscillation signal (first signal) that oscillation frequency and mains voltage are irrelevant.
In one example, the MOS transistor is a metal-oxide-semiconductor (semiconductor) field effect transistor, or referred to as a metal-insulator-semiconductor (insulator). The source and drain of the MOS tube can be exchanged, in most cases, the two regions are the same, and even if the two ends are exchanged, the performance of the device cannot be influenced. The PMOS tube is mainly conducted by holes, and the NMOS tube is mainly conducted by electrons.
In one possible implementation, as shown in fig. 2, the first delay oscillating unit 210 may include a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a second NMOS transistor MN2, a third NMOS transistor MN3, a first capacitor C1, a third inverter N3, and a fourth inverter N4, wherein,
a source of the third PMOS transistor MP3 is connected to a source of the fourth PMOS transistor MP4 for receiving the power supply voltage VDD, a drain of the third PMOS transistor MP3 is connected to a source of the fifth PMOS transistor MP5,
a gate of the fifth PMOS transistor MP5 is connected to a gate of the second NMOS transistor MN2, for receiving the first signal OUT,
a drain of the fifth PMOS transistor MP5 is connected to the drain of the second NMOS transistor MN2, the first terminal of the first capacitor C1, the gate of the fourth PMOS transistor MP4,
a source of the second NMOS transistor MN2 is connected to the second terminal of the first capacitor C1, a source of the third NMOS transistor MN3, and ground VSS,
the gate of the third NMOS transistor MN3 is connected to the gate of the first NMOS transistor MN1 (connection point N _ BIAS),
the drain of the third NMOS transistor MN3 is connected to the drain of the fourth PMOS transistor MP4 and the input terminal of the third inverter N3,
the output end of the third inverter N3 is connected to the input end of the fourth inverter N4, and the output end of the fourth inverter N4 is connected to the first input end of the first NAND gate 1.
In one possible implementation, as shown in fig. 2, the second delay oscillating unit 220 may include a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a second capacitor C2, a fifth inverter N5, and a sixth inverter N6, wherein,
a gate of the sixth PMOS transistor MP6 is connected to the gate of the third PMOS transistor MP3, the gate of the first PMOS transistor MP1 and the gate of the second PMOS transistor MP2 (the connection point is P _ BIAS), a source of the sixth PMOS transistor MP6 is connected to the source of the seventh PMOS transistor MP7 for receiving the power voltage VDD, a drain of the sixth PMOS transistor MP6 is connected to the source of the eighth PMOS transistor MP8,
the gate of the eighth PMOS transistor MP8 is connected to the gate of the fourth NMOS transistor MN4, for receiving the second signal a2,
a drain of the eighth PMOS transistor MP8 is connected to the drain of the fourth NMOS transistor MN4, the first end of the second capacitor C2, and the gate of the seventh PMOS transistor MP7,
a source of the fourth NMOS transistor MN4 is connected to the second terminal of the second capacitor C2, a source of the fifth NMOS transistor MN5, and ground VSS,
the gate of the fifth NMOS transistor MN5 is connected to the gate of the first NMOS transistor MN1 (connection point N _ BIAS),
a drain of the fifth NMOS transistor MN5 is connected to a drain of the seventh PMOS transistor MP7 and an input terminal of the fifth inverter N5,
the output end of the fifth inverter N5 is connected to the input end of the sixth inverter N6, and the output end of the sixth inverter N6 is connected to the first input end of the first NAND gate 1.
The embodiment of the utility model provides a set up to the symmetrical form through delaying oscillation unit with first delay oscillation unit, second, can simplify circuit design, practice thrift the cost, the generation duty cycle is about 50% square wave to improve circuit's work efficiency.
In one possible implementation, the width-to-length ratios of the third PMOS transistor MP3, the fourth PMOS transistor MP4, the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7 are the same as the width-to-length ratios of the first PMOS transistor MP1 and the second PMOS transistor MP2,
the width-to-length ratios of the first NMOS transistor MN1, the third NMOS transistor MN3 and the fifth NMOS transistor MN5 are the same.
The embodiment of the present invention provides a through setting up third PMOS transistor MP3, fourth PMOS transistor MP4, sixth PMOS transistor MP6, seventh PMOS transistor MP7 have a same width-length ratio as first PMOS transistor MP1, second PMOS transistor MP2, first NMOS transistor MN1, third NMOS transistor MN3, fifth NMOS transistor MN5 have a same width-length ratio, so that drain current Ir1 of the third PMOS transistor, drain current Ir2 of the fourth PMOS transistor, drain current Ir3 of the sixth PMOS transistor, and drain current Ir4 of the seventh PMOS transistor are all equal and all equal to reference current Ir, so as to realize low frequency oscillation by using reference current Ir, and generate an oscillation signal (first signal) whose oscillation frequency is independent of power supply voltage.
In one possible implementation, the first capacitor C1 is the same as the second capacitor C2.
In a possible implementation, the oscillation frequency of the first signal OUT is related to the resistor R, the first capacitor C1 and the second capacitor C2.
The following is an exemplary description of the principles implemented by embodiments of the present invention.
In one possible implementation, the second NAND gate NAND2 may further receive an enable signal EN input by an external controller to control the operation of the oscillation circuit.
In one example, when the input enable signal EN is 0, as shown in fig. 2, the signal F2 is 1, the signal a1 is 0, the signal B1 is 1, the signal D1 is 0, the signal E1 is 0, and the signal F1 is 1; meanwhile, the second signal a2 is equal to 1, the signal B2 is equal to 0, the signal D2 is equal to 1, and the signal E2 is equal to 1.
In one example, when the input enable signal EN changes from 0 to 1, since the first delay oscillation unit and the second delay oscillation unit are symmetrical, the second delay oscillation unit is taken as an example below, and logic analysis and formula derivation are performed.
When the enable signal EN changes from 0 to 1, the second signal a2 changes from 1 to 0, and the level at the point of the signal B2 starts to charge from 0, when the signal B2 charges to VDD-VGSP7(VGSP7 represents the gate-source voltage of the seventh PMOS transistor), the seventh PMOS transistor MP7 is just in the off-state, and when the voltage at the point of the signal B2 continues to rise, the seventh PMOS transistor MP7 is off; after the seventh PMOS transistor MP7 is turned off, the signal D2 changes from 1 to 0, and the signal E2 also changes from 1 to 0 at this time, thereby completing the delay of the second signal a 2; since the delay time of the logic gate is negligible with respect to the charging time of the capacitor, the delay time of the second delay oscillating unit can be obtained by the following.
In one example, the formula for charging the capacitor may be:
Q＝Ir3*Tf＝(VDD-VGSP7)*C2equation 1
Wherein Q represents the capacitance of the capacitor, Ir3Drain current Ir3 of the sixth PMOS transistor, VDD power supply voltage, C2 capacitance of the second capacitor, and TfIndicating the charging time.
From equation 1, the charging time of the capacitor can be deduced:
Tf＝(VDD-VGSP7)*C2/Ir3equation 2
As mentioned above, the reference current IrCan be expressed as:
Ir＝(VDD-VGSP1) /R formula 3
Wherein, VGSP1Representing the gate-source voltage of the first PMOS transistor and R representing the resistance of the resistor R.
Since Ir-Ir 3-Ir 4, C1-C2,
according to the current formula of the saturation region:
here, if the current I and the width-to-length ratio W/L are equal, neglecting the substrate bias effect, the VGSP7 can be regarded as VGSP1 (K and Vth in the formula are process parameters, and basically all PMOS transistors can be regarded as being equal, and all NMOS transistors can be regarded as being equal), so that the VGSP7 is about VGSP1 at this time, and the charging time (second time) is simplified:
Tf＝(VDD-VGSP7)*C2/Ir3＝(VDD-VGSP7)*C2/((VDD-VGSP1)/R)＝R*C2equation 5
The same can be deduced for the charging time (first time) of the upper half (first delay oscillating unit):
Tr＝(VDD-VGSP4)*C1/Ir1＝(VDD-VGSP4)*C1/((VDD-VGSP1)/R)＝R*C1equation 6
According to the formula 5 and the formula 6, the total charging time can be obtained:
Tt＝Tr+Tf＝R*C1+R*C2＝2*R*C1equation 7
Referring to fig. 3, fig. 3 is a schematic diagram illustrating oscillation time according to an embodiment of the present invention.
In one example, as shown in fig. 3, one clock cycle Tt is Tr + Tf, and Tr/Tf is the delay generated by two symmetrical circuits, respectively, and different charging times are controlled to generate different Tr and Tf, thereby generating different delay times Tt. The relationship between frequency and delay time is F ═ 1/Tt。
It can be seen that the total time TtIndependent of the supply voltage VDD, i.e. the oscillation frequency is independent of the supply voltage VDD.
The embodiment of the utility model provides a low frequency oscillation circuit, first delay oscillation unit, second delay oscillation unit all produce the reference current delay signal that the module produced through reference current for the oscillation frequency of the first signal of oscillation circuit output is relevant with very first time, second time, and is irrelevant with mains voltage, has eliminated mains voltage to oscillation frequency's influence, has improved oscillation frequency's stability.
The frequency of the oscillation circuit is less affected by a power supply, the frequency is stable under the condition of wide power supply voltage, the cost is lower, and the occupied area is smaller.
While various embodiments of the present invention have been described above, the above description is intended to be illustrative, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen in order to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims (10)
1. A low frequency oscillator circuit, the circuit comprising:
the reference current generating module is used for generating reference current;
a loop oscillation module connected to the reference current generation module and including a second delay oscillation unit, a first inverter, a second NAND gate, and a first NAND gate,
a first input end of the second delay oscillation unit is connected to an output end of the first inverter for receiving a second signal, an output end of the second delay oscillation unit is connected to a first input end of the second nand gate, a second input end of the second nand gate is connected to an output end of the first nand gate, an output end of the second nand gate is connected to a second input end of the first nand gate and an input end of the second inverter, a first input end of the first nand gate is connected to an output end of the first delay oscillation unit, an input end of the first inverter and a first input end of the first delay oscillation unit are connected to an output end of the second inverter for receiving a first signal,
a second input terminal of the second delay oscillation unit and a second input terminal of the first delay oscillation unit are connected to the reference current generation module, the second delay oscillation unit is configured to delay the second signal for a second time according to the reference current, the first delay oscillation unit is configured to delay the first signal for a first time according to the reference current,
wherein the oscillation frequency of the first signal is the inverse of the sum of the first time and the second time.
2. The circuit of claim 1, wherein the reference current generation module comprises a first PMOS transistor, a second PMOS transistor, a resistor, a first NMOS transistor, wherein,
the source of the first PMOS transistor is connected with the source of the second PMOS transistor and used for receiving power supply voltage, the gate of the first PMOS transistor is connected with the gate of the second PMOS transistor, the drain of the first PMOS transistor and the first end of the resistor,
a second terminal of the resistor is connected to the source of the first NMOS transistor and ground,
a drain of the second PMOS transistor is connected to a drain of the first NMOS transistor and a gate of the first NMOS transistor,
wherein the width-to-length ratios of the first PMOS transistor and the second PMOS transistor are the same,
wherein the current flowing through the resistor is the reference current.
3. The circuit of claim 2, wherein the first delay oscillating unit comprises a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a second NMOS transistor, a third NMOS transistor, a first capacitor, a third inverter, and a fourth inverter, wherein,
a source of the third PMOS transistor is connected to a source of the fourth PMOS transistor for receiving the supply voltage, a drain of the third PMOS transistor is connected to a source of the fifth PMOS transistor,
a gate of the fifth PMOS transistor is connected to a gate of the second NMOS transistor for receiving the first signal,
the drain of the fifth PMOS transistor is connected to the drain of the second NMOS transistor, the first end of the first capacitor, and the gate of the fourth PMOS transistor,
a source of the second NMOS transistor is connected to the second terminal of the first capacitor, a source of the third NMOS transistor, and ground,
a gate of the third NMOS transistor is connected to a gate of the first NMOS transistor,
the drain of the third NMOS transistor is connected to the drain of the fourth PMOS transistor and the input terminal of the third inverter,
the output end of the third inverter is connected to the input end of the fourth inverter, and the output end of the fourth inverter is connected to the first input end of the first nand gate.
4. The circuit of claim 3, wherein the second delay oscillating unit comprises a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a second capacitor, a fifth inverter, and a sixth inverter, wherein,
a gate of the sixth PMOS transistor is connected to the gate of the third PMOS transistor, the gate of the first PMOS transistor, and the gate of the second PMOS transistor, a source of the sixth PMOS transistor is connected to the source of the seventh PMOS transistor for receiving the power supply voltage, a drain of the sixth PMOS transistor is connected to the source of the eighth PMOS transistor,
a gate of the eighth PMOS transistor is connected to a gate of the fourth NMOS transistor for receiving the second signal,
a drain of the eighth PMOS transistor is connected to a drain of the fourth NMOS transistor, the first terminal of the second capacitor, and a gate of the seventh PMOS transistor,
a source of the fourth NMOS transistor is connected to the second terminal of the second capacitor, a source of the fifth NMOS transistor, and ground,
a gate of the fifth NMOS transistor is connected to a gate of the first NMOS transistor,
a drain of the fifth NMOS transistor is connected to a drain of the seventh PMOS transistor and an input terminal of the fifth inverter,
the output end of the fifth inverter is connected to the input end of the sixth inverter, and the output end of the sixth inverter is connected to the first input end of the first nand gate.
5. The circuit of claim 4,
the width-to-length ratios of the third PMOS transistor, the fourth PMOS transistor, the sixth PMOS transistor and the seventh PMOS transistor are the same as the width-to-length ratios of the first PMOS transistor and the second PMOS transistor,
the width-to-length ratios of the first NMOS transistor, the third NMOS transistor and the fifth NMOS transistor are the same.
6. The circuit of claim 4, wherein the first capacitance is the same as the second capacitance.
7. The circuit of claim 5 or 6, wherein the oscillation frequency of the first signal is related to the resistance, the first capacitance, and the second capacitance.
8. An oscillator, characterized in that the oscillator comprises a low frequency oscillating circuit according to any one of claims 1 to 7.
9. A power supply, characterized in that it comprises an oscillator according to claim 8.
10. An electronic device, characterized in that the electronic device comprises a power supply according to claim 9.
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Cited By (1)
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| CN114374362A (en) * | 2022-01-12 | 2022-04-19 | 上海晟矽微电子股份有限公司 | Oscillator, chip and electronic equipment |
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2021
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114374362A (en) * | 2022-01-12 | 2022-04-19 | 上海晟矽微电子股份有限公司 | Oscillator, chip and electronic equipment |
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