CN216210997U

CN216210997U - Transmission module for improving SPI signal quality in circuit

Info

Publication number: CN216210997U
Application number: CN202122423470.7U
Authority: CN
Inventors: 苏俊华; 张显禄; 张浩衡; 冯磊
Original assignee: Intelligent Automation Equipment Zhuhai Co Ltd
Current assignee: Intelligent Automation Equipment Zhuhai Co Ltd
Priority date: 2021-10-09
Filing date: 2021-10-09
Publication date: 2022-04-05
Anticipated expiration: 2031-10-09

Abstract

The utility model aims to provide a transmission module which has better burning performance and smaller parasitic capacitance value and can improve the quality of an SPI signal in a circuit. The single-channel SPI bus system comprises a host and a slave, wherein the host is in communication connection with the slave through an SPI bus, four ports of the SPI bus are respectively connected to corresponding ports of the slave, single-channel analog switches are arranged in four channels of the SPI bus, control ports of the four single-channel analog switches are in communication connection with the host, and the type of the single-channel analog switch is TS5A4594 DBVR. The utility model is applied to the technical field of communication transmission.

Description

Transmission module for improving SPI signal quality in circuit

Technical Field

The utility model is applied to the technical field of communication transmission, and particularly relates to a transmission module for improving the quality of an SPI signal in a circuit.

Background

The SPI bus is a full-duplex synchronous serial bus, is a synchronous serial port through which the MCU directly communicates with various peripherals, and is mainly applied to Flash, RTC (real time clock), ADC, DSP, EEPROM, network controller, digital signal decoder, and the like. The SPI bus typically uses 4 lines, a serial clock line SCK, a master input/slave output data line MISO, a master output/slave input data line MOSI, and an active low slave select line SSEL. In the practical application of the SPI bus, due to the control requirement, the hardware on-off control is often required to be performed through an electronic switch. However, if the parasitic capacitance parameter of the selected electronic switch is too large, the SI (signal integrity) of the SPI signal may be deteriorated, resulting in communication dysfunction or even complete communication interruption. In the current SPI bus application, a four-channel analog switch TS3a4751 (a main device in a backflow) is generally used for performing signal switching control, on or off is controlled by a control bit, but SPI programming performance is found to be unstable, when an oscilloscope is used for detecting a waveform diagram of an SPI bus, it is obviously found that a waveform of DIO1(MISO) is poor, and a situation that a rising edge becomes a peak obviously exists, and through specific analysis, when the switch is on, a parasitic capacitance in a whole loop reaches more than 43pF in combination with a data manual discovery and practical measurement of the four-channel analog switch TS3a4751, and through multiple verification, the parasitic capacitance in the loop is a main factor of MISO signal degradation, so it is necessary to provide a transmission module for improving SPI signal quality in a circuit with good programming performance and small parasitic capacitance value.

SUMMERY OF THE UTILITY MODEL

The utility model aims to overcome the defects of the prior art and provides the transmission module which has better burning performance and smaller parasitic capacitance value and can improve the quality of the SPI signal in the circuit.

The technical scheme adopted by the utility model is as follows: the system comprises a host and a slave, wherein the host is in communication connection with the slave through an SPI bus, four ports of the SPI bus are respectively connected to corresponding ports of the slave, four channels of the SPI bus are respectively provided with a single-channel analog switch, and control ports of the four single-channel analog switches are in communication connection with the host.

As can be seen from the above solution, the chinese name of SPI is the serial peripheral interface. The SPI bus system is a synchronous serial peripheral interface that allows the MCU to communicate with various peripherals in a serial manner to exchange information. The SPI bus system is a high-speed, full-duplex and synchronous communication bus, only four lines are occupied on pins of a chip, pins of the chip are saved, space is saved on the layout of a PCB, and convenience is provided.

Preferably, four channels of the SPI bus are respectively connected to a CLK port, a CS port, a DIO0 port, and a DIO1 port of the slave, the model of the single-channel analog switch is TS5a4594DBVR, COM ports of the four single-channel analog switches are all in communication connection with the slave, NO ports of the four single-channel analog switches are all in communication connection with the host, and control ports of the NO ports of the four single-channel analog switches are simultaneously connected to a control bit of the host.

As can be seen from the above solution, the SPI bus is a 4-wire bus, which is respectively MISO (master data input), MOSI (master data output), SCLK (clock), CS (chip select), the SCLK being the basis of sequential logic and having a fixed clock frequency, the clock frequency being the reciprocal of the clock period, the SCLK being the high and low state between one special signal oscillation of the signal, the SCLK being generated by the host and used for the transmission of the clock signal; the CS is a control signal for determining whether the slave chip is selected by the master chip, that is, only when the chip selection signal is a predetermined enable signal (high or low), the master chip is valid for operating the slave chip, which makes it possible to connect a plurality of SPI devices on the same bus, and the CS transmits the signal of the slave to the master control; the MOSI represents a write data line, and data output by the host computer is transmitted to the slave computer through the MOSI; the MISO is an antenna technology for wireless communication, multiple paths of antennas are used and combined to achieve the minimum error and the optimal data transmission speed, data output by the slave computer is transmitted to the host computer through the MISO, the model of the single-channel analog switch is TS5A4594DBVR, the parasitic capacitance of the single-channel analog switch in a path is 13pF, the improvement is obvious compared with the situation that the parasitic capacitance in a TS3A4751 loop of a four-channel analog switch reaches more than 43pF, the SPI burning function is found to be normal, the signal quality of DIO1(MISO) is greatly improved, although the number of the channel analog switches in a circuit is increased, the material cost has no great difference, the packaging of the single-channel analog switch is small, and more space is not occupied.

Drawings

Fig. 1 is a circuit schematic of the present invention.

Detailed Description

As shown in fig. 1, in this embodiment, the present invention includes a master 1 and a slave 2, where the master 1 is connected to the slave 2 through an SPI bus 3, four ports of the SPI bus 3 are respectively connected to corresponding ports of the slave 2, four channels of the SPI bus 3 are provided with single-channel analog switches, and control ports of the four single-channel analog switches are connected to the master 1 in a communication manner.

In this embodiment, the four channels of the SPI bus 3 are respectively connected to the CLK port, the CS port, the DIO0 port, and the DIO1 port of the slave 2, the model of the single-channel analog switch is TS5a4594DBVR, the COM ports of the four single-channel analog switches are all in communication connection with the slave 2, the NO ports of the four single-channel analog switches are all in communication connection with the host 1, and the control ports of the NO ports of the four single-channel analog switches are simultaneously connected to the control bit of the host 1.

In this embodiment, the master 1 includes a computer, a tablet and other mobile terminals, and the slave 2 is a product.

The working principle of the utility model is as follows: the host computer passes through the SPI bus with from quick-witted communication connection, four ports of SPI bus are connected to respectively the corresponding port of following the machine, four passageways of SPI bus all are provided with single channel analog switch, four single channel analog switch's control port all with host computer communication connection.

Claims

1. The utility model provides a transmission module of SPI signal quality in promotion circuit which characterized in that: it includes host computer (1) and follows machine (2), host computer (1) through SPI bus (3) with follow machine (2) communication connection, four ports of SPI bus (3) are connected to respectively follow the corresponding port of machine (2), four passageways of SPI bus (3) all are provided with single channel analog switch, four single channel analog switch's control port all with host computer (1) communication connection.

2. The transmission module of claim 1, wherein the transmission module is configured to improve the quality of the SPI signal in the circuit: the four channels of the SPI bus (3) are respectively connected with a CLK port, a CS port, a DIO0 port and a DIO1 port of the slave (2), the model of the single-channel analog switch is TS5A4594DBVR, the COM ports of the four single-channel analog switches are all in communication connection with the slave (2), the NO ports of the four single-channel analog switches are all in communication connection with the host (1), and the control ports of the NO ports of the four single-channel analog switches are simultaneously connected to the control bit of the host (1).