CN201590076U - Interface extending circuit and mobile terminal with the circuit - Google Patents
Interface extending circuit and mobile terminal with the circuit Download PDFInfo
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- CN201590076U CN201590076U CN2010201164203U CN201020116420U CN201590076U CN 201590076 U CN201590076 U CN 201590076U CN 2010201164203 U CN2010201164203 U CN 2010201164203U CN 201020116420 U CN201020116420 U CN 201020116420U CN 201590076 U CN201590076 U CN 201590076U
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Abstract
The utility model discloses an interface extending circuit and mobile terminal with the circuit, comprising a main processor and an interface extending module with GPIO ports, wherein the interface extending module is connected with a parallel interface of the main processor by a parallel bus to receive the interface configuration command and data sent from the main processor and connected with a perimeter circuit by the GPIO ports of the interface extending module. The required interface configuration command and data transmission communication are realized between the main processor and the interface configuration command by the parallel communication way and the reading-writing speed is quick and the interface extending circuit and mobile terminal can be flexibly extended according to the requirement of the perimeter circuit for the number of the GPIC interface. When the interface extending circuit and mobile terminal are used in the mobile terminal system such the telephones, not only the required enough GPIC interface resources are provided for continuously increased perimeter circuits, but also the interface extending circuit and mobile terminal respond the operation in good time, such as quick press-key switch performed by the user, thereby improving the work performance of the mobile terminal.
Description
Technical field
The utility model belongs to interface expansion technique field, specifically, and the portable terminal that relates to a kind of circuit structure that can expand the GPIO interface of chip and adopt described interface expanded circuit design.
Background technology
Variation day by day along with cell-phone function, when carrying out the cell phone system circuit design, need be more and more at the peripheral functional circuit that connects of mobile phone primary processor, and most peripheral circuit GPIO interface of often needing to connect primary processor is realized the collaborative work with primary processor.Such as a mobile phone that includes 16 buttons, its keyboard scanning circuit promptly needs to take 8 road GPIO interfaces of primary processor.But the GPIO interface that general mobile phone primary processor can provide is often not enough, and is all the more so when smart mobile phone designs.So just need expansion GPIO interface or keyboard scanning circuit to satisfy the connection needs of increasing peripheral circuit.And the method that can realize the expansion of GPIO interface at present has two kinds: a kind of extended chip that is to use special use, another adopts programmable logic device (PLD) such as CPLD to realize exactly.
But Zhuan Yong GPIO interface extended chip and programmable logic device (PLD) all is based on I basically in the market
2The C bus interface, promptly pass through I
2The C bus realizes the communication that is connected of primary processor and interface extended chip.Owing to be subjected to I
2The restriction of C interface speed at the quick button of cellphone subscriber or when playing games, the slow problem of button reaction will occur.And the proprietary extensions chip uses dumbly, and this design whenever all needs the actual functional capability that will finish according to system, selects different extended chips for use, and this has just caused the not continuity of circuit design.
The utility model content
The utility model is existing based on I in order to solve
2The interface expanded circuit problem of slow response of C bus, provide a kind of based on and the interface expanded circuit of port communications, to improve the reaction velocity of circuit system.
For solving the problems of the technologies described above, the utility model is achieved by the following technical solutions:
A kind of interface expanded circuit, comprise primary processor and interfacing expansion module with multichannel GPIO mouth, described interfacing expansion module connects the parallel interface of primary processor by parallel bus, receive interface configuration command and data that primary processor sends, and connect peripheral circuit by the GPIO mouth of interfacing expansion module.
Further, in described interfacing expansion module, include host interface unit, GPIO function logic unit and GPIO configuration register, GPIO level state register; Described host interface unit writes data according to interface configuration command that receives and data to corresponding GPIO configuration register or GPIO level state register by the parallel interface of parallel bus connection primary processor; Described GPIO function logic unit is according to the state of the corresponding GPIO mouth of data configuration in GPIO configuration register and the GPIO level state register.
Further again, it is parallel from interface that described host interface unit uses the state machine that detects the level mode to create.
Preferably, described primary processor preferably adopts its I8080 interface as the parallel interface that is connected communication with interfacing expansion module.
Further again, in described interfacing expansion module, include keyboard scan logical block and keyboard scancode register, the GPIO mouth that is used for the connection matrix keyboard circuit on the described keyboard scan logical block connecting interface expansion module, when having detected button and pressed, the key scan sign indicating number is transferred to described keyboard scancode register preserve, and produce the interrupt interface that look-at-me transfers to primary processor.
Wherein, described keyboard scan logical block connects the host interface unit, and the look-at-me that produces is transferred to the host interface unit, connects the interrupt interface of primary processor by the host interface unit.
Further, in described keyboard scan logical block, include the line scanning counter module, remove to tremble clock frequency division module, remove to shake logic module and keyboard matrix scan module; Describedly remove to tremble clock frequency division module receiving system clock, carry out transferring to behind the frequency division and describedly go to shake logic module and produce and remove to tremble synchronous clock, and then export described keyboard matrix scan module to; Described line scanning counter module receiving system clock produces counting clock and transfers to described keyboard matrix scan module; Described keyboard matrix scan module connects the GPIO mouth that is used for the connection matrix keyboard circuit on the described interfacing expansion module, key-press status is detected, and when having detected button and pressed, generate the key scan sign indicating number and be saved in described keyboard scancode register, and the generation look-at-me exports described primary processor to.
Preferably, describedly remove to shake the shift register that logic module is made up of 3 groups of synchronizer triggers and form.
Optionally, described interfacing expansion module can adopt programmable logic device (PLD) such as CPLD to realize.
Based on above-mentioned interface expanded circuit structure, the utility model provides a kind of portable terminal that adopts described interface expanded circuit design again, by adopting parallel bus to be connected between primary processor and the interfacing expansion module, realizing the parallel transmission of interface configuration command and data, thereby improved the reaction velocity of circuit system.
Compared with prior art, advantage of the present utility model and good effect are: interface expanded circuit of the present utility model adopts the parallel communications mode to realize the transport communication of required interface configuration command and data between primary processor and the interfacing expansion module, read or write speed is fast, can carry out flexible expansion to the requirement of GPIO interface quantity according to peripheral circuit, thereby improve the versatility of circuit system design.Be applied in the mobile terminal systems such as mobile phone, the GPIO interface resource that connects required capacity not only can be provided for the peripheral circuit of being on the increase, but also can the operations such as quick switching key that the user carries out be responded in time, thereby improved working performance of mobile terminals.
After reading the detailed description of the utility model embodiment in conjunction with the accompanying drawings, other characteristics of the present utility model and advantage will become clearer.
Description of drawings
Fig. 1 is the schematic block circuit diagram of a kind of embodiment of the interface expanded circuit that proposes of the utility model;
Fig. 2 is the theory diagram of a kind of embodiment of keyboard scan logical block internal circuit among Fig. 1.
Embodiment
Below in conjunction with accompanying drawing embodiment of the present utility model is described in detail.
Interface expanded circuit abandoning tradition of the present utility model is based on I
2The circuit design pattern of C bus, between primary processor and interfacing expansion module, adopt parallel bus to be connected communication, utilize the fireballing characteristics of parallel interface reading and writing data to accelerate the transmission speed of interface configuration command and data between primary processor and the interfacing expansion module, thereby satisfied the GPIO of system mouth resource is carried out under the prerequisite of flexible expansion, realized that circuit system is to quick operating rapid response.
Elaborate the concrete establishment structure and the course of work thereof of described interface expanded circuit below by a specific embodiment.
Embodiment one, referring to shown in Figure 1, in the interfacing expansion module of present embodiment, comprise host interface unit, GPIO function logic unit, GPIO configuration register, GPIO level state register and the chief components such as pin multiplexing unit of multichannel GPIO interface can be provided.
The host interface unit is as the communication interface between system's primary processor and the interfacing expansion module, be connected with the I8080 parallel interface of primary processor by parallel bus, receive the configuration order that primary processor sends, such as clock signal of system CLK, chip selection signal CS, address signal RS, read enable signal RE, write enable signal WE and reset signal Reset, and realize the transmitted in both directions of data by 16 bit data bus Data_bus in the parallel bus with primary processor.In the present embodiment, described host interface unit can use the state machine that detects the level mode to realize the design of I8080 from interface, level state according to the configuration order that receives, the configuration data that primary processor is sent writes relevant register, writes the GPIO configuration register such as the pairing address information of GPIO interface that will need to dispose; The concrete state (such as I/O/interruption etc.) that this interface will be configured to writes GPIO level state register or the like.
Adopt state machine to realize from interface I8080, not only safe and reliable, and implement also very simple.Certainly, except state machine, also can select to adopt other multiple interfaces way of realization to design described host interface unit according to the particular type of the parallel interface that primary processor provided, present embodiment be not limited in above giving an example.
GPIO function logic unit is used to realize the concrete configuration function to the GPIO interface, connect described GPIO configuration register, GPIO level state register and GPIO pin multiplexing unit, come the state of the needed GPIO interface of concrete configuration according to the numerical value of being preserved in GPIO configuration register and the GPIO level state register, such as a part of GPIO interface configuration is become input state or output state, other a part of interface configuration is become interruption status or the like.
For the interface expanded circuit that makes present embodiment can realization matrix keyboard scan function, present embodiment has also designed the keyboard scan logical block in described interfacing expansion module, connect keyboard scancode register, host interface unit and GPIO pin multiplexing unit, as shown in Figure 1.Wherein, described keyboard scan logical block scans the level state that is used for the GPIO interface of connection matrix keyboard circuit in the GPIO pin multiplexing unit, detects with the triggering state to keyboard.When button is pressed, the pairing key scan sign indicating number of this button is written to the keyboard scancode register, and generation look-at-me Host_irq transfers to the interrupt interface of system's primary processor by the host interface unit, read the key scan sign indicating number with the notice primary processor, and then can make response in time the operation that the user carries out.
The keyboard scan logical block of present embodiment can adopt the line scanning counter module, remove to tremble clock frequency division module, remove to shake logic module and keyboard matrix scan module etc. partly sets up formation, as shown in Figure 2.At first, system clock CLK one tunnel is used for providing counting clock to the line scanning counter module, and by the line scanning counter module counting clock that produces is offered the keyboard matrix scan module; Carry out system clock CLK after frequency division handles through trembling clock frequency division module in the past on another road, exports to shake logic module and remove to tremble synchronous clock with generation, transfers to described keyboard matrix scan module.Wherein, going to shake logic module can be realized by the shift register design that 3 groups of synchronizer triggers are formed.The capable incoming level state of matrix keyboard can be determined 3 of described shift register output phases " position or " back by the keyboard matrix scan module.The row input of keyboard matrix scan module is then going to tremble under the effect of synchronous clock, matrix keyboard is carried out intermittent scanning obtain.Final key scan sign indicating number is then judged by the capable incoming level state and the column scan output state of matrix keyboard.When the keyboard matrix scan module defines button and presses, the key scan sign indicating number that generates is saved in the keyboard scancode register, and produces look-at-me Host_irq and notify main processor accesses keyboard scancode register, to read key scan sign indicating number wherein.
The GPIO pin multiplexing unit of present embodiment can adopt one group of logic switch design to realize, according to the numerical value of GPIO configuration register, opens corresponding logic switch and realizes keyboard scan or GPIO interface function.
The interfacing expansion module of present embodiment can adopt discrete function module circuit to connect and realize, also can adopt the programmable logic device (PLD) of low-power consumption,, utilize the hardware description language programming to realize such as the CPLD device etc., with the simplified system circuit design, present embodiment does not specifically limit this.
Interface expanded circuit of the present utility model adopts the parallel interface of primary processor to expand GPIO interface and keyboard scan function, reading and writing data speed is fast, be fit to be applied in the circuit system design of portable terminals such as mobile phone, palm PC, so that the user is when quick button, system can make response in time.
Certainly; the above only is a kind of preferred implementation of the present utility model; should be noted that; for those skilled in the art; under the prerequisite that does not break away from the utility model principle; can also make some improvements and modifications, these improvements and modifications also should be considered as protection domain of the present utility model.
Claims (10)
1. interface expanded circuit, it is characterized in that: comprise primary processor and interfacing expansion module with multichannel GPIO mouth, described interfacing expansion module connects the parallel interface of primary processor by parallel bus, receive interface configuration command and data that primary processor sends, and connect peripheral circuit by the GPIO mouth of interfacing expansion module.
2. interface expanded circuit according to claim 1 is characterized in that: include host interface unit, GPIO function logic unit and GPIO configuration register, GPIO level state register in described interfacing expansion module; Described host interface unit writes data according to interface configuration command that receives and data to corresponding GPIO configuration register or GPIO level state register by the parallel interface of parallel bus connection primary processor; Described GPIO function logic unit is according to the state of the corresponding GPIO mouth of data configuration in GPIO configuration register and the GPIO level state register.
3. interface expanded circuit according to claim 2 is characterized in that: it is parallel from interface that described host interface unit uses the state machine that detects the level mode to create.
4. interface expanded circuit according to claim 3 is characterized in that: the parallel interface of described primary processor is the I8080 interface.
5. interface expanded circuit according to claim 1, it is characterized in that: in described interfacing expansion module, include keyboard scan logical block and keyboard scancode register, the GPIO mouth that is used for the connection matrix keyboard circuit on the described keyboard scan logical block connecting interface expansion module, when having detected button and pressed, the key scan sign indicating number is transferred to described keyboard scancode register preserve, and produce the interrupt interface that look-at-me transfers to primary processor.
6. interface expanded circuit according to claim 5, it is characterized in that: described keyboard scan logical block connects the host interface unit, the look-at-me that produces is transferred to the host interface unit, connect the interrupt interface of primary processor by the host interface unit.
7. interface expanded circuit according to claim 5 is characterized in that: include the line scanning counter module in described keyboard scan logical block, remove to tremble clock frequency division module, remove to shake logic module and keyboard matrix scan module; Describedly remove to tremble clock frequency division module receiving system clock, carry out transferring to behind the frequency division and describedly go to shake logic module and produce and remove to tremble synchronous clock, and then export described keyboard matrix scan module to; Described line scanning counter module receiving system clock produces counting clock and transfers to described keyboard matrix scan module; Described keyboard matrix scan module connects the GPIO mouth that is used for the connection matrix keyboard circuit on the described interfacing expansion module, key-press status is detected, and when having detected button and pressed, generate the key scan sign indicating number and be saved in described keyboard scancode register, and the generation look-at-me exports described primary processor to.
8. interface expanded circuit according to claim 7 is characterized in that: describedly remove to shake the shift register that logic module is made up of 3 groups of synchronizer triggers and form.
9. interface expanded circuit according to claim 1 is characterized in that: described interfacing expansion module is a programmable logic device (CPLD).
10. a portable terminal is characterized in that: include as the described interface expanded circuit of each claim in the claim 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010201164203U CN201590076U (en) | 2010-02-10 | 2010-02-10 | Interface extending circuit and mobile terminal with the circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010201164203U CN201590076U (en) | 2010-02-10 | 2010-02-10 | Interface extending circuit and mobile terminal with the circuit |
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| CN201590076U true CN201590076U (en) | 2010-09-22 |
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| CN2010201164203U Expired - Fee Related CN201590076U (en) | 2010-02-10 | 2010-02-10 | Interface extending circuit and mobile terminal with the circuit |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102522976A (en) * | 2011-11-30 | 2012-06-27 | 青岛海信移动通信技术股份有限公司 | Key expansion circuit, expansion method and mobile terminal |
| CN103226537A (en) * | 2013-05-09 | 2013-07-31 | 上海斐讯数据通信技术有限公司 | Programmable logic device for implementing hardware interface of mobile phone |
| CN103268302A (en) * | 2013-04-19 | 2013-08-28 | 华为技术有限公司 | Interface expanding circuit, interface expanding connecting method and embedded system |
| CN104182274A (en) * | 2014-08-19 | 2014-12-03 | Tcl通讯（宁波）有限公司 | Interrupt detection device and interrupt detection method for mobile terminals |
| CN106649159A (en) * | 2016-12-23 | 2017-05-10 | 中国电子科技集团公司第五十四研究所 | Radio-frequency assembly and special SPI data transmission method thereof |
| CN108415863A (en) * | 2018-02-01 | 2018-08-17 | 广东欧珀移动通信有限公司 | The hardware compatibility implementation method and Related product of electronic device |
| CN109491946A (en) * | 2018-11-12 | 2019-03-19 | 郑州云海信息技术有限公司 | A kind of chip and method for I2C bus extension |
| CN110750394A (en) * | 2019-09-25 | 2020-02-04 | 深圳震有科技股份有限公司 | Control method and terminal for realizing main and standby single boards based on GPIO pins |
| WO2020155545A1 (en) * | 2019-01-28 | 2020-08-06 | 山东华芯半导体有限公司 | Programmable gpio device and time sequence implementation method based on the device |
| CN114619425A (en) * | 2020-12-08 | 2022-06-14 | 山东新松工业软件研究院股份有限公司 | Demonstrator main control board and novel clean robot demonstrator |
-
2010
- 2010-02-10 CN CN2010201164203U patent/CN201590076U/en not_active Expired - Fee Related
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102522976A (en) * | 2011-11-30 | 2012-06-27 | 青岛海信移动通信技术股份有限公司 | Key expansion circuit, expansion method and mobile terminal |
| CN103268302A (en) * | 2013-04-19 | 2013-08-28 | 华为技术有限公司 | Interface expanding circuit, interface expanding connecting method and embedded system |
| CN103268302B (en) * | 2013-04-19 | 2016-08-03 | 华为技术有限公司 | A kind of Interface Expanding circuit, Interface Expanding method of attachment and embedded system |
| CN103226537B (en) * | 2013-05-09 | 2017-09-19 | 上海斐讯数据通信技术有限公司 | A kind of PLD for realizing hardware interface of mobile phone |
| CN103226537A (en) * | 2013-05-09 | 2013-07-31 | 上海斐讯数据通信技术有限公司 | Programmable logic device for implementing hardware interface of mobile phone |
| CN104182274A (en) * | 2014-08-19 | 2014-12-03 | Tcl通讯（宁波）有限公司 | Interrupt detection device and interrupt detection method for mobile terminals |
| CN104182274B (en) * | 2014-08-19 | 2018-02-23 | 深圳市Tcl云创科技有限公司 | The interrupt detection apparatus and its method of a kind of mobile terminal |
| CN106649159A (en) * | 2016-12-23 | 2017-05-10 | 中国电子科技集团公司第五十四研究所 | Radio-frequency assembly and special SPI data transmission method thereof |
| CN106649159B (en) * | 2016-12-23 | 2019-03-15 | 中国电子科技集团公司第五十四研究所 | A kind of radio frequency component and its dedicated SPI data transmission method |
| CN108415863A (en) * | 2018-02-01 | 2018-08-17 | 广东欧珀移动通信有限公司 | The hardware compatibility implementation method and Related product of electronic device |
| CN109491946A (en) * | 2018-11-12 | 2019-03-19 | 郑州云海信息技术有限公司 | A kind of chip and method for I2C bus extension |
| WO2020155545A1 (en) * | 2019-01-28 | 2020-08-06 | 山东华芯半导体有限公司 | Programmable gpio device and time sequence implementation method based on the device |
| CN110750394A (en) * | 2019-09-25 | 2020-02-04 | 深圳震有科技股份有限公司 | Control method and terminal for realizing main and standby single boards based on GPIO pins |
| CN114619425A (en) * | 2020-12-08 | 2022-06-14 | 山东新松工业软件研究院股份有限公司 | Demonstrator main control board and novel clean robot demonstrator |
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| C14 | Grant of patent or utility model | ||
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Granted publication date: 20100922 Termination date: 20130210 |