CN216054727U - Solar cell - Google Patents

Abstract

Embodiments of the present disclosure provide a solar cell. The solar cell includes: a silicon substrate; at least one layer pair disposed on a surface of the silicon substrate, wherein each layer pair of the at least one layer pair comprises: the oxide layer is arranged on one side of the layer pair close to the silicon substrate; and the doped silicon film layer is arranged on one side of the oxide layer, which is far away from the silicon substrate, wherein the thickness of the oxide layer, which is closest to the silicon substrate, in the at least one layer pair is greater than the thickness of other oxide layers in the at least one layer pair.

Description

Solar cell

Technical Field

Embodiments of the present disclosure relate to a solar cell.

Background

For the crystalline silicon solar cell, defects exist on the surface of a silicon substrate, so that minority carriers are easily recombined to influence the photoelectric conversion of the crystalline silicon solar cell. It is therefore often necessary to provide a passivation structure between the silicon substrate surface and the electrode to passivate the silicon substrate surface to reduce the recombination rate of minority carriers at the surface of the crystalline silicon substrate.

The laminated passivation structure of the tunneling oxide layer and the doped silicon film layer is adopted to passivate the surface of the silicon substrate, so that an excellent passivation effect can be achieved.

From the passivation effect, the higher the concentration of the doping atoms in the doped silicon film layer, the better. However, the phenomenon that the doping atoms penetrate through the tunneling oxide layer and reach the silicon substrate occurs in the subsequent high-temperature activation process due to the excessively high doping concentration, and the passivation effect is reduced when the doping atoms reach the silicon substrate.

Disclosure of Invention

Embodiments of the present disclosure provide a solar cell having a reduced contact resistance of an electrode and a doped silicon film layer and having an improved fill factor, and a method of manufacturing the same.

In one aspect, embodiments of the present disclosure provide a solar cell, including: a silicon substrate; at least one layer pair disposed on a surface of the silicon substrate, wherein each layer pair of the at least one layer pair comprises: the oxide layer is arranged on one side of the layer pair close to the silicon substrate; and the doped silicon film layer is arranged on one side of the oxide layer, which is far away from the silicon substrate, wherein the thickness of the oxide layer, which is closest to the silicon substrate, in the at least one layer pair is greater than the thickness of other oxide layers in the at least one layer pair.

For example, the thickness of the oxide layer in the at least one layer pair decreases in order in a direction from the surface of the silicon substrate to a direction away from the silicon substrate.

For example, the thickness of the other oxide layers in the at least one layer pair except the oxide layer closest to the silicon substrate is the same.

For example, the thickness of the oxide layer at the outermost layer of the at least one layer pair is less than the thickness of the other oxide layers of the at least one layer pair.

For example, the thickness of the oxide layer closest to the silicon substrate in the at least one layer pair is greater than 1.8nm and less than or equal to 2.5nm, and the thickness of the other oxide layers except the oxide layer closest to the silicon substrate is less than 1.8 nm.

For example, the doped silicon film layer is an n-type doped silicon film layer, and the doping concentration of the n-type dopant in the n-type doped silicon film layer in the at least one layer pair is gradually increased in a direction from the surface of the silicon substrate to a direction away from the silicon substrate.

For example, the doping concentration of the n-type dopant of the n-type doped silicon film layer closest to the silicon substrate in the at least one layer pair is greater than 1 x 10²⁰cm^-3。

For example, the solar cell further includes: and the electrode is arranged on one side of the at least one layer pair far away from the silicon substrate.

For example, the number of the at least one layer pair is 2 to 50.

In another aspect, an embodiment of the present disclosure also provides a method for manufacturing a solar cell according to the first aspect, including: providing a silicon substrate; forming at least one layer pair on a surface of the silicon substrate, wherein forming the at least one layer pair comprises: forming an oxide layer on one side of each layer pair of the at least one layer pair, which is close to the silicon substrate; and forming a doped silicon film layer on one side of the oxide layer far away from the silicon substrate, wherein the thickness of the oxide layer closest to the silicon substrate in the at least one layer pair is larger than the thickness of other oxide layers in the at least one layer pair.

For example, the at least one layer pair comprises 3 or more layer pairs, and forming the at least one layer pair comprises: s1, forming an oxide layer on the surface of the silicon substrate; s2, depositing an in-situ doped silicon film layer on the oxide layer closest to the silicon substrate; s3, forming an oxide layer on the doped silicon film layer; s4, depositing an in-situ doped silicon film layer on the oxide layer; the above steps S3-S4 are repeated until a penultimate layer pair is formed.

For example, the method of manufacturing a solar cell further includes: forming an oxide layer on the in-situ doped silicon film layer of the penultimate layer pair; forming a non-doped silicon film layer on the oxide layer; performing ion implantation on the undoped silicon film to implant a dopant; and performing high-temperature annealing to activate the dopant in the doped silicon film layer.

For example, the method of manufacturing a solar cell further includes: forming an oxide layer on the in-situ doped silicon film layer of the penultimate layer pair; forming a non-doped silicon film layer on the oxide layer; and carrying out high-temperature diffusion of the dopant on the non-doped silicon film and carrying out high-temperature annealing so as to activate the dopant in the doped silicon film layers of all the layer pairs.

For example, the method of manufacturing a solar cell further includes: forming an oxide layer on the in-situ doped silicon film layer of the penultimate layer pair; depositing an in-situ doped silicon film layer on the oxide layer; and carrying out high-temperature annealing to activate the dopant in the doped silicon film layer.

For example, the forming an oxide layer on the surface of the silicon substrate includes: introducing oxygen or mixed gas of oxygen and nitrogen into the chamber at the process temperature of 400-700 ℃ to carry out the oxidation process for 1-90 minutes.

For example, at the process temperature ranging from 400 ℃ to 700 ℃, the oxidation process for 1-90 minutes by introducing oxygen or a mixed gas of oxygen and nitrogen into the chamber comprises: and introducing oxygen with the flow rate of 3000sccm and nitrogen with the flow rate of 11000sccm into the cavity for 15 minutes at the process temperature of 630 ℃ to obtain an oxide layer with the thickness of 1.9 nm.

For example, the silicon substrate is an n-type silicon wafer, the doped silicon film layer is an n-type doped silicon film layer, and the doping concentration of the n-type doped silicon film layer in the at least one layer pair is gradually increased in a direction from the surface of the silicon substrate to a direction away from the silicon substrate.

For example, the forming at least one layer pair in the same deposition chamber, the forming the doped silicon film layer and the oxide layer except for the penultimate layer pair includes: introducing a phosphine gas and a silane gas with a flow ratio of 0.4:100 into an LPCVD deposition chamber; stopping introducing the phosphine gas and the silane gas and vacuumizing; introducing oxygen into the LPCVD deposition chamber to form an in-situ oxide layer; forming the doped silicon film layer of the penultimate layer pair comprises: and (3) introducing a phosphine gas and a silane gas in a flow ratio of 0.6:100 in the LPCVD deposition chamber to form the in-situ doped silicon film layer.

For example, performing a high temperature anneal includes: high temperature annealing was carried out at 880-960 deg.C for 25-90 minutes.

For example, the performing high-temperature diffusion of the dopant and high-temperature annealing on the undoped silicon film includes: introducing a phosphorus source with the flow rate of 1000sccm and oxygen gas with the flow rate of 200sccm into the in-situ deposition chamber at 770-830 ℃; annealing was carried out at 820-880 ℃ for 45 minutes.

For example, providing a silicon substrate includes: providing a monocrystalline N-type silicon wafer; texturing and boron diffusion are carried out on the silicon wafer to prepare P-N sections, the back surface is leveled, and a borosilicate glass layer on the front surface is reserved; cleaning the silicon wafer by using a hydrofluoric acid solution; after forming at least one layer pair on the surface of the silicon substrate, the manufacturing method further includes: cleaning and removing the silicon film wound and plated on the front surface of the silicon wafer; depositing an aluminum oxide film on the front side of the silicon wafer; depositing silicon nitride coating films on the front side and the back side of the silicon wafer; and printing metal slurry on the front side and the back side of the silicon wafer and sintering, wherein the at least one layer pair is formed on the back side of the silicon wafer.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly described below, and it is apparent that the drawings in the following description only relate to some embodiments of the present invention and are not limiting on the present invention.

Fig. 1 shows a schematic structural diagram of a solar cell according to an embodiment of the present disclosure;

FIG. 2 shows another schematic structural diagram of a solar cell according to an embodiment of the present disclosure;

FIG. 3 shows a schematic diagram of a solar cell fabrication method according to an embodiment of the present disclosure;

FIG. 4 is a graph showing the relationship between the depth of a doped silicon film and the concentration of phosphorus atoms obtained in comparative example 1;

FIG. 5 is a graph showing the relationship between the depth of a doped silicon film and the concentration of phosphorus atoms obtained in comparative example 2; and

fig. 6 is a graph showing the relationship between the depth and the phosphorus atom concentration of the doped silicon film obtained in example 1.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the utility model without any inventive step, are within the scope of protection of the utility model.

Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

For the cell with the N-type tunneling oxidation contact structure, the concentration of phosphorus in the silicon film is designed to be sequentially increased from the surface of the silicon wafer to the electrode contact surface, and the energy level of the silicon film in the passivation contact interface is sequentially and gradually reduced from the surface of the silicon wafer to the electrode contact surface. The advantages of such a design are: firstly, a high-dose doped silicon film is beneficial to forming ohmic contact between a metal electrode and the silicon film, reducing the metal-silicon contact resistance and improving the filling factor; secondly, the highly doped silicon film layer far away from the surface end of the silicon wafer can further enhance the electron tunneling to reach the electrode through the oxide layer, which is beneficial to reducing the contact resistance and improving the filling factor; and thirdly, under the condition of meeting the passivation requirement, properly reducing the phosphorus atom concentration of the silicon film at the near end of the surface of the silicon wafer, so that the phenomenon that phosphorus atoms penetrate through a tunneling oxide layer in the subsequent high-temperature activation process to reduce the passivation effect can be avoided.

From the viewpoint of passivation effect, the higher the concentration of activated phosphorus atoms in the silicon thin film, the better. Since a high concentration of phosphorus atoms is doped into the silicon thin film, the degree of band down bending of the silicon thin film is increased. Therefore, the method is beneficial to extracting more electrons from the silicon substrate on the whole interface, repelling more minority carrier holes and improving the passivation effect of the silicon wafer. In practice, increasing the supply of phosphorus atoms (such as increasing the proportion of phosphine gas or increasing the dose of phosphorus ion implantation) can increase the concentration of phosphorus atoms in the silicon thin film. However, when the phosphorus supply is too high, phosphorus atoms penetrate through the silicon wafer surface to tunnel through the oxide layer due to too high concentration in the subsequent high-temperature activation process, and the passivation effect is reduced when the phosphorus atoms reach the silicon substrate. Therefore, for the passivation interface of the silicon wafer surface/the silicon oxide layer/the doped silicon layer, a proper phosphorus atom supply amount needs to be selected, so that the passivation effect can be satisfied, and too many phosphorus atoms cannot penetrate.

During the process of in-situ doping the silicon film by phosphorus, the phosphorus atom concentration in the silicon film can be controlled by controlling the gas flow ratio of phosphine to silane. Furthermore, a silicon film with variable doping amount can be prepared in the deposition stage, for example, the concentration of phosphorus atoms in the silicon film gradually increases from the end near the surface of the silicon wafer to the end far away from the surface of the silicon wafer. Similarly, since the diffusion rate of phosphorus atoms in the silicon thin film is relatively fast, phosphorus atoms with high concentration in the silicon thin film can diffuse to a low concentration region in the subsequent high-temperature activation process, and finally, the concentration distribution of phosphorus atoms in the whole silicon thin film cannot be greatly different. That is, the silicon thin film with different phosphorus atom concentration distributions is obtained only by controlling and changing the deposition conditions, and the concentration distribution difference of phosphorus atoms in the whole silicon thin film is not large after high-temperature activation.

An embodiment of the present disclosure provides a solar cell, including: a silicon substrate; at least one layer pair disposed on a surface of the silicon substrate, wherein each layer pair of the at least one layer pair comprises: the oxide layer is arranged on one side of the layer pair close to the silicon substrate; and the doped silicon film layer is arranged on one side of the oxide layer, which is far away from the silicon substrate, wherein the thickness of the oxide layer, which is closest to the silicon substrate, in the at least one layer pair is greater than the thickness of other oxide layers in the at least one layer pair. By providing an oxide layer, for example, a silicon oxide layer, between the silicon films, the diffusion coefficient of phosphorus atoms in the silicon oxide film under high temperature conditions is smaller than that in the silicon film, so that the silicon oxide layer in the middle of the silicon thin film can serve as a barrier layer for diffusion of phosphorus atoms. Phosphorus elements with different dosages are introduced into the silicon thin films on the two sides of the oxide layer, and the silicon thin films with different phosphorus doping concentration distributions can be obtained after high-temperature annealing. And the doped silicon film layer on the outermost layer of the silicon substrate is contacted with the electrode, and the thickness of the oxide layer on the side far away from the silicon substrate is smaller than that of the oxide layer close to the silicon substrate, so that the tunneling of electrons is facilitated, electrons of the inner layer doped silicon film in the outermost layer doped silicon film can also tunnel the oxide layer to reach the electrode, the contact resistance between the electrode and the doped silicon film layer is further reduced, and the filling factor is improved.

A solar cell and a method of manufacturing the same according to an embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings.

As shown in fig. 1, an embodiment of the present disclosure provides a solar cell 1000 including: a silicon substrate 100; at least one layer pair 200, e.g., a tunneling passivation layer, is disposed on a surface of the silicon substrate, wherein each layer pair 210 of the at least one layer pair comprises: an oxide layer 211 disposed on a side of the pair of layers adjacent to the silicon substrate 100; and a doped silicon film layer 212 disposed on a side of the oxide layer 211 away from the silicon substrate, wherein a thickness of the oxide layer 211 closest to the silicon substrate in the at least one layer pair is greater than thicknesses of the other oxide layers 221 and 231 in the at least one layer pair.

In fig. 1, at least one layer pair 200 is shown to comprise three layer pairs, the layer pair near the silicon substrate 100 being a layer pair 210 comprising an oxide layer 211 and a doped silicon film layer 212, the layer pair 220 sequentially outward comprising an oxide layer 221 and a doped silicon film layer 222, and the layer pair 230 comprising an oxide layer 231 and a doped silicon film layer 232. Fig. 1 is a schematic diagram illustrating a solar cell according to an embodiment of the present disclosure, and the solar cell according to an embodiment of the present disclosure does not include only three layer pairs, for example, the solar cell may include 2-50 layer pairs, and those skilled in the art may select the layer pairs according to actual needs.

In the embodiment of the present disclosure, an electrode, for example, the electrode 710 shown in fig. 2, may be disposed on the outer side of the doped silicon film layer of the outermost pair, and the thickness of the oxide layer 211 on the side closest to the silicon substrate is set to be greater than the thicknesses of the oxide layers 221 and 231 in the other pairs, so that the silicon oxide layer disposed between the doped silicon film layers functions to block diffusion of phosphorus atoms and also blocks tunneling of electrons.

For example, in the solar cell 1000, the thickness of the oxide layer in the at least one layer pair decreases sequentially in a direction from the surface 101 of the silicon substrate to a direction away from the silicon substrate, for example, in a direction indicated by an arrow a in fig. 1, that is, the thickness of the oxide layers 211, 221, 231 decreases gradually.

For example, in the solar cell 1000 of the embodiment of the present disclosure, it may also be: the thickness of the other oxide layers in the at least one layer pair, such as oxide layer 221 and oxide layer 231, is the same except for the oxide layer 211 closest to the surface 101 of the silicon substrate, and can be selected by one skilled in the art as desired.

For example, in the solar cell 1000 of the embodiment of the present disclosure, it may also be: in other layer pairs than the pair 210 closest to the surface 101 of the silicon substrate, the oxide layer at the outermost layer has a thickness smaller than the other oxide layers in the other layer pairs in the direction indicated by the arrow a, for example, the oxide layer 231 has a thickness smaller than the oxide layer 221.

For example, the thickness of the oxide layer closest to the silicon substrate in the at least one layer pair is greater than 1.8nm and equal to or less than 2.5nm, and the thickness of the other oxide layers excluding the oxide layer closest to the silicon substrate is less than 1.8nm, and as shown in fig. 1, the thickness of the oxide layer 211 of the layer pair 210 closest to the surface 101 of the silicon substrate in the at least one layer pair 200 may be greater than 1.8nm and equal to or less than 2.5nm, and the thickness of the other oxide layers, for example, the oxide layers 221 and 231 may be less than 1.8 nm.

For example, in the solar cell 1000 according to the embodiment of the present disclosure, the silicon substrate may be an n-type substrate, the at least one layer pair, for example, a tunneling passivation layer, is disposed on a back surface of the n-type substrate, that is, an opposite surface of the solar light absorption surface, and the doped silicon film layer may be an n-type doped silicon film layer, and a doping concentration of an n-type dopant of the n-type doped silicon film layer in the at least one layer pair is gradually increased in a direction from a surface of the silicon substrate to a direction away from the silicon substrate, for example, the n-type dopant may be antimony, phosphorus, or arsenic. For example, the doping concentration of the n-type dopant, for example, phosphorus, in the n-type doped silicon film layers 212, 222, 232 gradually increases in the direction from the surface 101 close to the silicon substrate to the direction away from the silicon substrate, so that the doping concentration of the doped silicon film layer of the contact electrode is higher, which is beneficial to forming ohmic contact between the metal electrode and the silicon film, reducing the metal-silicon contact resistance, and improving the filling factor. Moreover, under the condition of meeting the passivation requirement, the phosphorus atom concentration of the silicon film at the near end of the surface of the silicon wafer is properly reduced, so that the phenomenon that phosphorus atoms penetrate through a tunneling oxide layer on the surface of the silicon wafer to reduce the passivation effect in the subsequent high-temperature activation process can be avoided, the matching window of the whole process is widened, and the industrial mass production is facilitated. Moreover, the relatively highly doped silicon thin film layer far away from the surface end of the silicon wafer can further promote electrons to reach the electrode after tunneling through the oxide layer from the silicon wafer end, so that the current of the battery is increased, and the filling factor is improved.

Alternatively, in the solar cell according to the embodiment of the present disclosure, the silicon substrate may be a p-type substrate, the solar cell may be a PERC cell, the at least one layer pair, for example, a tunneling passivation layer, is disposed on the front side of the p-type substrate, that is, the sunlight absorption surface, and the side of the n + emitter away from the p-type substrate, and the at least one layer pair may be disposed in a partial region, that is, in a partial structure, for example, may be disposed on the side of the cell front electrode facing the p-type substrate, that is, in a region directly opposite to the front electrode between the p-type substrate and the front electrode. The doped silicon film layer may be an n-type doped silicon film layer, and the doping concentration of an n-type dopant of the n-type doped silicon film layer in the at least one layer pair is gradually increased in a direction from the surface of the silicon substrate to a direction away from the silicon substrate, for example, the n-type dopant may be antimony, phosphorus or arsenic. For example, in the direction from the surface close to the silicon substrate to the direction away from the silicon substrate, the doping concentration of the n-type dopant, for example, phosphorus, of the n-type doped silicon film layer is gradually increased, so that the doping concentration of the doped silicon film layer of the contact electrode is higher, ohmic contact between the metal electrode and the silicon film is favorably formed, the metal-silicon contact resistance is reduced, and the filling factor is improved. Moreover, under the condition of meeting the passivation requirement, the phosphorus atom concentration of the silicon film at the near end of the surface of the silicon wafer is properly reduced, so that the phenomenon that phosphorus atoms penetrate through a tunneling oxide layer on the surface of the silicon wafer to reduce the passivation effect in the subsequent high-temperature activation process can be avoided, the matching window of the whole process is widened, and the industrial mass production is facilitated. Moreover, the relatively highly doped silicon thin film layer far away from the surface end of the silicon wafer can further promote electrons to reach the electrode after tunneling through the oxide layer from the silicon wafer end, so that the current of the battery is increased, and the filling factor is improved.

For example, the n-type dopant doping concentration of the n-type doped silicon film layer closest to the silicon substrate in the at least one layer pair may be greater than 1 x 10²⁰cm^-3。

For example, as shown in fig. 2, the solar cell 1000 according to the embodiment of the present disclosure may further include an electrode 710, where the electrode 710 is disposed on a side of the at least one layer pair away from the silicon substrate 100.

For example, in the solar cell 1000, at least one layer pair 200 is disposed on the back side of a silicon substrate, passivating the solar cell.

Alternatively, in the solar cell 1000, referring to fig. 2, it may further include: an alumina passivation film 400 on the front side of the silicon substrate 100 and silicon nitride plating films 500 on the front and back sides of the cell. The nitride film plating films 500 on the front and back sides of the cell may be deposited using PECVD, the thickness of the silicon nitride plating film 500 on the front side may be about 80 nm, and the thickness of the silicon nitride plating film 500 on the back side may be about 70 nm. The aluminum oxide passivation film 400 on the front side of the cell may be formed using an atomic layer deposition method and may have a thickness of about 4 nm.

Further, the solar cell 1000 may further include metal electrode layers, for example, silver layers, on the front and back sides of the cell as electrodes on the front and back sides of the cell, respectively.

In the solar cell according to the embodiment of the disclosure, the thickness of the oxide layer close to the silicon substrate is larger than that of the oxide layer far away from the silicon substrate, and the oxide layer with a smaller thickness is more favorable for tunneling electrons through, so that electrons of at least one doped silicon film layer of the inner layer in the outermost doped silicon film layer can also tunnel through the oxide layer to reach the electrode, the contact resistance between the metal electrode layer and the outermost doped silicon film layer can be further reduced, and the filling factor is improved. Moreover, the concentration of the dopant in the doped silicon film layer is gradually increased from the surface of the silicon substrate to the direction far away from the silicon substrate, so that the doped silicon film layer on the side close to the electrode has the maximum concentration of the dopant, ohmic contact between the metal electrode and the doped silicon film is favorably formed, the metal-silicon contact resistance is reduced, and the filling factor is improved; and the doped silicon film close to the surface of the silicon substrate has lower dopant concentration, so that phosphorus atoms can be prevented from penetrating through the tunneling oxide layer in the subsequent high-temperature activation process to reduce the passivation effect, and the highly doped silicon film layer far away from the surface end of the silicon wafer can further enhance the electron tunneling to reach the electrode through the oxide layer, thereby being beneficial to reducing the contact resistance and improving the filling factor.

Further, an embodiment of the present disclosure also provides a method for manufacturing a solar cell, as shown in fig. 3, the method including: providing a silicon substrate; and forming at least one layer pair on a surface of the silicon substrate, comprising: forming an oxide layer on one side of each layer pair of the at least one layer pair, which is close to the silicon substrate; and forming a doped silicon film layer on one side of the oxide layer far away from the silicon substrate, wherein the thickness of the oxide layer closest to the silicon substrate in the at least one layer pair is larger than the thickness of other oxide layers in the at least one layer pair.

A schematic diagram of a solar cell formed by the manufacturing method can be seen in fig. 1, which is shown in fig. 1, but the solar cell may include three layer pairs, for example, the solar cell may include 2-50 layer pairs, and those skilled in the art can select the layer pairs according to actual needs.

For example, in the embodiment of the present disclosure, an electrode may be disposed outside the doped silicon film layer of the outermost layer pair, the thickness of the oxide layer 211 on the side closest to the silicon substrate is set to be greater than the thicknesses of the oxide layers 221 and 231 of the other layer pairs, the silicon oxide layer disposed between the doped silicon film layers functions to block diffusion of phosphorus atoms and also blocks tunneling of electrons, and the oxide layer farthest from the silicon wafer is set to have the smallest thickness, so that electrons of at least one inner layer doped silicon film can also tunnel through the oxide layer to reach the electrode, thereby further reducing the contact resistance between the electrode and the outermost layer doped silicon film layer and improving the fill factor.

Alternatively, it may also be: the thickness of the other oxide layers in the at least one layer pair is the same except for the oxide layer closest to the surface of the silicon substrate, and can be selected by one skilled in the art as desired. The method can also be as follows: in the other layer pairs except the one closest to the surface of the silicon substrate, the oxide layer at the outermost layer has a thickness smaller than the thickness of the other oxide layers in the other layer pairs in the direction indicated by the arrow a.

For example, the thickness of the oxide layer closest to the silicon substrate in the at least one layer pair may be greater than 1.8nm and equal to or less than 2.5nm, and the thickness of the other oxide layer excluding the oxide layer closest to the silicon substrate may be less than 1.8 nm.

Alternatively, in an embodiment of the present disclosure, forming the doped silicon film layer requires a dopant doping operation on the silicon film, for example, the doped silicon film layer may be an n-type doped silicon film layer, and forming the n-type doped silicon film layer may be doping the silicon film layer with an n-type dopant, for example, antimony, phosphorus or arsenic, for example, the silicon film layer may be doped by using one or more combinations of a high-temperature diffusion method, an ion implantation method, and an in-situ doping method, for example, a high-temperature diffusion method of phosphorus, a phosphorus ion implantation method, and a phosphorus in-situ doping method.

For example, in the method of manufacturing a solar cell of the embodiment of the present disclosure, the at least one layer pair includes 3 or more layer pairs, and forming the at least one layer pair may include:

s1, forming an oxide layer on the surface of the silicon substrate;

s2, depositing an in-situ doped silicon film layer on the oxide layer closest to the silicon substrate,

s3, forming an oxide layer on the doped silicon film layer;

s4, depositing an in-situ doped silicon film layer on the oxide layer;

the above steps S3-S4 are repeated until a penultimate layer pair is formed, i.e., the layer pair that is inward of the layer pair that is closest to the outer side, i.e., the layer pair 220 shown in FIG. 1 is the penultimate layer pair.

Alternatively, in the method of manufacturing a solar cell according to the embodiment of the present disclosure, the at least one layer pair may include 2 layer pairs, and the forming of the at least one layer pair may include:

s1, forming an oxide layer on the surface of the silicon substrate;

s2, depositing an in-situ doped silicon film layer on the oxide layer closest to the silicon substrate,

s3, forming an oxide layer on the doped silicon film layer;

s4, depositing an in-situ doped silicon film layer on the oxide layer; or forming a non-doped silicon film layer on the oxide layer; performing ion implantation on the undoped silicon film; and

performing high-temperature annealing to activate the dopant in the doped silicon film layer;

alternatively, step S4 may be replaced by: and carrying out high-temperature diffusion of the dopant on the non-doped silicon film and carrying out high-temperature annealing to activate the dopant in the doped silicon film layers of all the layer pairs, so that subsequent high-temperature annealing is not required.

For example, the method of manufacturing a solar cell may further include: forming an oxide layer on the in-situ doped silicon film layer of the penultimate layer pair; forming a non-doped silicon film layer on the oxide layer; performing ion implantation on the undoped silicon film to implant a dopant; and performing high-temperature annealing to activate the dopant in the doped silicon film layer.

As described in connection with fig. 1, an oxide layer 231 is formed on the in-situ doped silicon film 222 of the layer pair 220 on the side away from the silicon substrate, and then an undoped silicon film is formed on the oxide layer, which is subjected to dopant ion implantation, e.g., phosphorous ion implantation, and then high temperature annealing, thereby activating the dopants in the silicon film.

Alternatively, the process conditions for performing dopant ion implantation, such as phosphorous ion implantation, on the undoped silicon film may be: the ion beam dose may be 4.5 x 10¹⁵atoms/cm²The voltage can be 10KV, the power can be 3000W, the phosphine flow can be 10sccm, and the cavity pressure can be 5 x 10^-5Torr。

Compared with a doped silicon film, the growth speed of the non-doped silicon film is generally more than 5 nanometers per minute, and the growth speed of the doped silicon film is generally 1.2 nanometers per minute, so that the outermost silicon film of at least one layer pair is firstly formed into the non-doped silicon film, and compared with the direct formation of the doped silicon film layer, the formation time of the silicon film can be shortened, and the production efficiency can be improved.

Alternatively, the method of manufacturing a solar cell may further include: forming an oxide layer on the in-situ doped silicon film layer of the penultimate layer pair; forming a non-doped silicon film layer on the oxide layer; and carrying out high-temperature diffusion of the dopant on the non-doped silicon film and carrying out high-temperature annealing so as to activate the dopant in the doped silicon film layers of all the layer pairs. The ion implantation step can be omitted as compared to doping an undoped silicon film by ion implantation.

As described in connection with fig. 1, an oxide layer 231 is formed on the in-situ doped silicon film 222 of the layer pair 220 on the side away from the silicon substrate, and then an undoped silicon film is formed on the oxide layer, which is subjected to high temperature diffusion of a dopant, for example, phosphorus, and then to high temperature annealing, thereby activating the dopant in the silicon film.

Alternatively, the method of manufacturing a solar cell may further include: forming an oxide layer on the in-situ doped silicon film layer of the penultimate layer pair; depositing an in-situ doped silicon film layer on the oxide layer; and performing high-temperature annealing to activate the dopant in the doped silicon film layer.

As described in conjunction with fig. 1, an oxide layer 231 is formed on the side of the in-situ doped silicon film 222 of the layer pair 220 away from the silicon substrate, and then the in-situ doped silicon film is deposited on the oxide layer 231, for example, by using a phosphorous in-situ doping method to form the in-situ doped silicon film; then, high temperature annealing is performed to activate the dopants in the doped silicon film layer.

For example, in the method for manufacturing a solar cell, the forming an oxide layer on the surface of the silicon substrate may include: introducing oxygen or mixed gas of oxygen and nitrogen into the chamber at the process temperature of 400-700 ℃ to perform an oxidation process for 1-90 minutes.

For example, the step of introducing oxygen or a mixed gas of oxygen and nitrogen into the chamber at the process temperature ranging from 400 ℃ to 700 ℃ for performing the oxidation process for 1 minute to 90 minutes may include: and introducing oxygen with the flow rate of 3000sccm and nitrogen with the flow rate of 11000sccm into the cavity for 15 minutes at the process temperature of 630 ℃ to obtain an oxide layer with the thickness of 1.9 nm.

For example, the oxide layer formed on the doped silicon film layer may be formed by the same method as the method for forming the oxide layer on the surface of the silicon substrate, for example, at the process temperature ranging from 400 ℃ to 700 ℃, the chamber is introduced with oxygen or a mixed gas of oxygen and nitrogen, and the oxidation process is performed for 1 minute to 90 minutes, and may be, for example: oxygen gas at a flow rate of 3000sccm (Standard Cubic centre per Minute, Standard milliliters per Minute) and nitrogen gas at a flow rate of 11000sccm were introduced into the chamber at a process temperature of 630 c for 15 minutes to obtain an oxide layer with a thickness of 1.9 nm.

Alternatively, the following process conditions may be adopted for forming the oxide layer on the doped silicon film layer: the chamber is purged with oxygen at a flow rate of 0.2 to 20SLM (Standard lithium per Minute) for an oxidation time of 2 minutes to 20 minutes.

Here, the oxide layer is formed, that is, nitrogen is introduced during the process of forming the silicon oxide layer, and mainly carries oxygen and dilutes oxygen, so that a uniform oxide layer is formed on the surface of the silicon wafer, thereby improving the quality of the oxide layer and the performance of the device.

For example, in the method for manufacturing a solar cell according to the embodiment of the present disclosure, the silicon substrate may be an n-type silicon wafer, the doped silicon film layer may be an n-type doped silicon film layer, and the dopant doping concentration of the n-type doped silicon film layer in the at least one layer pair gradually increases in a direction from the surface of the silicon substrate to a direction away from the silicon substrate.

For example, the n-type dopant may be antimony, phosphorus or arsenic, and the doping concentration of phosphorus in the n-type doped silicon film layer closest to the surface of the silicon substrate may be greater than 1 x 10²⁰cm^-3。

For example, in a manufacturing method according to an embodiment of the present disclosure, the forming at least one layer pair is performed in the same deposition chamber, and the in-situ silicon film layer and the oxide layer except for the penultimate layer pair are formed, for example, the forming the doped silicon film layer except for the doped silicon film layer 232 and the oxide layer 231 in the layer pair 230 in fig. 1 may include: introducing a phosphine gas and a silane gas at a flow ratio of 0.4:100, for example, at a flow ratio of 0.4sccm and 100sccm, respectively, in a Deposition chamber of Low Pressure Chemical Vapor Deposition (LPCVD) to form an in-situ deposited phosphorus doped silicon film layer of, for example, 50nm or 100 nm; stopping introducing the phosphine gas and the silane gas and vacuumizing; introducing oxygen into the LPCVD deposition chamber to form an in-situ oxide layer; wherein forming the doped silicon film layer of the penultimate layer pair comprises: in the LPCVD deposition chamber, a phosphine gas and a silane gas are introduced at a flow ratio of 0.6:100 to form an in-situ phosphorus doped silicon film layer with a thickness of, for example, 50nm or 100 nm.

For example, in the embodiments of the present disclosure, the in-situ doped silicon film layer or the undoped silicon film layer may also be formed by Plasma Enhanced Chemical Vapor Deposition (PECVD).

In the method, for forming the in-situ doped silicon film layer or the non-doped silicon film layer by LPCVD, the chamber pressure is reduced and the average free path of molecules is increased due to the low pressure, so that uniform film forming is facilitated and the film forming quality is improved.

For example, in embodiments of the present disclosure, performing a high temperature anneal to activate dopants in a doped silicon film layer may include: high temperature annealing is carried out for 25-90 minutes at 880-960 ℃; for example, a high temperature anneal at 910 ℃ or 920 ℃ is performed for 40 minutes.

In an embodiment of the present disclosure, performing high temperature diffusion of a dopant, for example, high temperature diffusion of phosphorus, on the undoped silicon film, and then performing high temperature annealing, so as to activate the dopant in the silicon film layer may include: introducing a phosphorus source with the flow rate of 1000sccm and oxygen gas with the flow rate of 200sccm into the in-situ deposition chamber at 770-830 ℃; annealing was carried out at 820-880 ℃ for 45 minutes.

In the embodiment of the disclosure, after the doped silicon film layers are annealed at high temperature, because the silicon oxide layers are arranged at intervals between the doped silicon film layers, the interdiffusion of phosphorus atoms is prevented, so that the concentration distribution of different phosphorus atoms in different doped silicon film layers in at least one layer is realized, the passivation effect of the silicon wafer surface can be ensured, and the FF (fill factor) of a battery device can be improved.

For example, in an embodiment of the present disclosure, providing a silicon substrate may include: providing a monocrystalline N-type silicon wafer; texturing and boron diffusion are carried out on the silicon wafer to prepare P-N sections, the back surface is leveled, and a borosilicate glass layer on the front surface is reserved; and cleaning the silicon wafer by using a hydrofluoric acid solution.

Alternatively, in an embodiment of the present disclosure, providing a silicon substrate may include: providing a monocrystalline N-type silicon wafer; preparing a smooth silicon wafer surface; and cleaning the surface of the silicon wafer.

For example, after forming at least one layer pair on the surface of the silicon substrate, the manufacturing method further includes: cleaning and removing the silicon film wound and plated on the front surface of the silicon wafer; depositing an aluminum oxide film on the front side of the silicon wafer; depositing silicon nitride coating films on the front side and the back side of the silicon wafer; and printing metal slurry on the front side and the back side of the silicon wafer and sintering to form the solar cell, wherein the at least one layer pair is formed on the back side of the silicon wafer.

Illustratively, in the steps of printing metal paste on the front and back surfaces of the silicon wafer and sintering, electrode paste is printed on the surface of the silicon nitride film, the front electrode partially burns through the silicon nitride film and the aluminum oxide film to contact the silicon substrate after sintering, and the back electrode partially burns through the silicon nitride film to contact the doped silicon film layer, such as the back electrode 720 and the front electrode 720 in fig. 2.

Illustratively, providing a single crystalline N-type silicon wafer may comprise: providing a monocrystalline N-type silicon wafer with the bulk resistivity of 2.5 omega cm; preparing a smooth silicon wafer surface can comprise selecting a potassium hydroxide alkali solution with the mass fraction of 40% to carry out isotropic corrosion on the silicon wafer to obtain a polished silicon wafer surface, wherein the reflectivity of the polished silicon wafer surface is 50%; cleaning the surface of the silicon wafer may include: the silicon wafer was cleaned with a 10% by mass hydrofluoric acid solution.

Illustratively, texturing the silicon wafer, boron diffusion to prepare P-N junctions, back surface planarization, and leaving a front side borosilicate glass layer may comprise: selecting 5% sodium hydroxide alkali solution by mass fraction to carry out anisotropic corrosion on the silicon wafer to obtain a textured silicon wafer surface, wherein the reflectivity of the textured silicon wafer surface is not more than 13%; preparing P-N sections by using a furnace tube boron diffusion method; and corroding the back surface of the silicon wafer by using a mixed solution of hydrofluoric acid, nitric acid and sulfuric acid, removing the borosilicate glass layer on the back surface, and simultaneously keeping the borosilicate glass layer on the front surface.

Illustratively, in an embodiment of the present disclosure, the cleaning to remove the silicon film around the front side of the silicon wafer may include: removing the front oxide layer by using hydrofluoric acid solution, and reserving the back silicon oxide layer; removing the front gradient phosphorus doped silicon film by using alkaline solution corrosion; and removing the front borosilicate glass layer by using a hydrofluoric acid solution.

Illustratively, depositing an aluminum oxide film on the front side of the silicon wafer may include: and depositing a 4-nanometer aluminum oxide film on the front surface of the silicon wafer by using an atomic layer deposition method.

Illustratively, depositing a silicon nitride coating film on the front and back surfaces of the silicon wafer may include: the silicon nitride film is deposited in a PECVD system, the 80 nm silicon nitride film 500 is deposited on the front side, and the 70 nm silicon nitride film 500 is deposited on the back side, as shown in fig. 2.

Illustratively, printing a metal paste on the front and back surfaces of the silicon wafer and sintering may include: and printing silver paste on the front surface and the back surface of the silicon wafer and sintering to form silver electrodes on the front surface and the back surface of the silicon wafer.

The following describes several examples of the method for manufacturing a solar cell according to the embodiment of the present disclosure, and describes technical effects of the technical solutions of the present disclosure with reference to comparative examples.

Comparative example 1

Comparative example 1 provides the preparation of a single layer in situ phosphorus doped silicon thin film, comprising the steps of:

a1, selecting a silicon wafer. A single crystal N-type silicon wafer was selected, which had a bulk resistivity of 2.5. omega. cm.

And B1, preparing a smooth silicon wafer surface. And (3) selecting a sodium hydroxide alkali solution with the mass fraction of 40% to carry out isotropic corrosion on the silicon wafer to obtain the polished surface of the silicon wafer, wherein the reflectivity of the polished surface of the silicon wafer is 50%.

C1, cleaning the surface of the silicon wafer. The silicon wafer was cleaned with a 10% by mass hydrofluoric acid solution.

D1, oxidizing the surface of the silicon wafer. And preparing an oxide layer by using a thermal oxidation method, wherein the oxidation temperature is set to be 630 ℃, the flow of introduced oxygen is 3000sccm, the flow of introduced nitrogen is 11000sccm, and the oxygen introduction time is 15min, so that the thickness of the obtained oxide layer is about 1.9 nm.

E1, double-sided deposition of the in-situ phosphorus doped silicon film. In an LPCVD deposition system, silane and phosphine gases were used to deposit an in-situ phosphorus doped silicon film with a thickness of 130 nm (as a single layer of phosphorus doped silicon film, i.e., the gas flow ratio was kept constant) on the surface of the silicon wafer. Depositing three silicon films with different phosphorus contents, wherein the gas flow ratios of phosphane and silane are respectively as follows: 0.4:100, 0.6:100 and 1.2: 100.

F1, carrying out high-temperature annealing on the in-situ phosphorus doped silicon film. Phosphorus atoms in the silicon thin film are activated, the annealing temperature is 910 ℃, and the annealing time is 40 minutes.

G1, cleaning the silicon nitride plated film. And depositing a silicon nitride film on the surface of the doped polysilicon film, wherein the thickness of the silicon nitride film is 79 nanometers. After high-temperature annealing, a layer of phosphorus-containing silicon oxide layer is formed on the surface of the doped polycrystalline silicon film, and the layer is cleaned before film coating, wherein the cleaning condition is that an HF solution with the mass concentration of 10% is adopted for cleaning for 2 minutes.

H1, and performance testing. ECV (electrochemical capacitance voltage method) is used for testing the doping concentration and the minority carrier lifetime of the silicon wafer.

FIG. 4 is a graph showing the relationship between the depth of the doped silicon film obtained in comparative example 1 and the concentration of phosphorus atoms, where the depth of the doped silicon film is the distance from the surface of the outermost doped silicon film, and it can be seen from FIG. 4 that increasing the proportion of phosphine gas can indeed increase the active phosphorus atom content in the in-situ phosphorus doped silicon film, which is beneficial for improving the contact performance of the metal doped silicon film and improving the FF of the cell; meanwhile, theoretically, the higher the active phosphorus content in the silicon film is, the better the passivation effect of the silicon film on the surface of the silicon wafer is. However, the sample with the flow ratio of the phosphane being 1.2:100 shows that a large number of phosphorus atoms in the in-situ phosphorus-doped silicon film can penetrate through the tunneling oxide layer on the surface of the silicon wafer after high-temperature annealing and enter the silicon wafer body, and the phosphorus atom penetration can bring adverse effects on the passivation effect of the silicon wafer: firstly, phosphorus atoms diffuse into a silicon wafer substrate, and the minority carrier recombination probability is increased because the phosphorus atoms destroy the integrity of the atomic lattice structure of the silicon substrate; secondly, the distribution of high-concentration phosphorus atoms in the matrix can further enhance the Auger recombination generation in the silicon wafer.

Thus, the gas flow ratio of phosphane to silane was 1.2:100, which was 9mV lower than the pseudo-open circuit voltage of the sample with a flow ratio of 0.4: 100. Therefore, for such a single-layer in-situ phosphorus-doped silicon film, it is difficult to increase the active phosphorus content in the silicon film by simply controlling the flow rate of the phosphine.

Comparative example 2

Comparative example 2 provides the preparation of a multilayer silicon film (including undoped silicon films and in-situ phosphorus doped silicon thin films) by the following steps:

a2, selecting a silicon wafer. A single crystal N-type silicon wafer was selected, which had a bulk resistivity of 2.5. omega. cm.

And B2, preparing a smooth silicon wafer surface. And (3) selecting a potassium hydroxide alkali solution with the mass fraction of 40% to carry out isotropic corrosion on the silicon wafer to obtain the polished surface of the silicon wafer, wherein the reflectivity of the polished surface of the silicon wafer is 50%.

C2, cleaning the surface of the silicon wafer. The silicon wafer was cleaned with a 10% by mass hydrofluoric acid solution.

D2, oxidizing the surface of the silicon wafer. And preparing an oxide layer by using a thermal oxidation method, wherein the oxidation temperature is set to be 630 ℃, the flow of introduced oxygen is 3000sccm, the flow of introduced nitrogen is 11000sccm, and the oxygen introduction time is 15min, so that the thickness of the obtained oxide layer is about 1.9 nm.

E2, double-sided deposition of silicon thin films (undoped silicon film/in-situ phosphorus doped silicon film/undoped silicon film). In an LPCVD deposition system, a 40 nm undoped silicon film is first deposited using silane; depositing an 80 nanometer in-situ phosphorus-doped silicon film on the surface of the non-doped silicon film by using phosphine and silane gas, wherein the flow ratio of the phosphine to the silane of the doped silicon film is 0.6: 100; and finally, depositing a 40 nm non-doped silicon film on the surface of the in-situ phosphorus-doped silicon film by using silane gas.

F2, carrying out high-temperature annealing on the in-situ phosphorus doped silicon film. Phosphorus atoms in the silicon film are activated, the annealing temperature is 920 ℃, and the annealing time is 45 minutes.

G2, performance test. ECV test doping concentration.

As can be seen from fig. 5, after being activated by high-temperature annealing, phosphorus atoms diffuse into the undoped silicon films on both sides from the in-situ phosphorus-doped silicon film, and the concentration distributions of the phosphorus atoms in the three films are substantially the same. Thus, a concentration gradient distribution of phosphorus atoms in a silicon film cannot be achieved by providing multiple layers of silicon films of different phosphorus doping concentrations in the silicon film, because the subsequent high temperature activation process causes phosphorus atoms to diffuse into all of the silicon films.

Example 1

Example 1 of a fabrication method according to an embodiment of the present disclosure provides for the preparation of a graded in-situ phosphorus doped silicon film (including a doped silicon film and an in-situ silicon oxide layer, the in-situ silicon oxide layer meaning that the silicon oxide layer is performed in the same chamber as the immediately preceding process without shifting) by the following steps:

a3, selecting a silicon wafer. A single crystal N-type silicon wafer was selected, which had a bulk resistivity of 2.5. omega. cm.

And B3, preparing a smooth silicon wafer surface. And (3) selecting a potassium hydroxide alkali solution with the mass fraction of 40% to carry out isotropic corrosion on the silicon wafer to obtain the polished surface of the silicon wafer, wherein the reflectivity of the polished surface of the silicon wafer is 50%.

C3, cleaning the surface of the silicon wafer. The silicon wafer was cleaned with a 10% by mass hydrofluoric acid solution.

D3, oxidizing the surface of the silicon wafer. And preparing an oxide layer by using a thermal oxidation method, wherein the oxidation temperature is set to be 630 ℃, the flow of introduced oxygen is 3000sccm, the flow of introduced nitrogen is 11000sccm, and the oxygen introduction time is 15min, so that the thickness of the obtained oxide layer is about 1.9 nm.

E3, double-sided deposition of an in-situ phosphorus-silicon film (in-situ phosphorus-silicon film/oxide layer/in-situ phosphorus-silicon film). In an LPCVD deposition system, a 100 nanometer in-situ phosphorus-doped silicon film is deposited on the surface of a non-doped silicon film by using phosphine and silane gases, wherein the flow ratio of the phosphine to the silane of the doped silicon film is 0.4: 100; closing phosphine and silane gases, vacuumizing, and introducing oxygen into the furnace to form an oxide layer on the surface of the in-situ phosphorus-doped silicon film; and depositing a 100-nanometer in-situ phosphorus-doped silicon film on the surface of the oxide layer, wherein the flow ratio of phosphine to silane of the doped silicon film is 0.6: 100.

F3, carrying out high-temperature annealing on the in-situ phosphorus doped silicon film. Phosphorus atoms in the silicon thin film are activated, the annealing temperature is 910 ℃, and the annealing time is 40 minutes.

G3, performance test. ECV test doping concentration.

As can be seen from fig. 6, after activation by high temperature annealing, interdiffusion of phosphorus atoms is prevented due to the presence of an oxide layer in the film layer, and concentration distribution of different phosphorus atoms in the silicon film is achieved. The effect of this design is: the passivation effect of the surface of the silicon wafer can be ensured, and the FF of a battery device can be improved.

Example 2

Example 2 of a fabrication method according to an embodiment of the present disclosure provides for the preparation of a graded in-situ phosphorus doped silicon film (comprising a doped silicon film and an in-situ silicon oxide layer) by the steps of:

a4, selecting a silicon wafer. A single crystal N-type silicon wafer was selected, which had a bulk resistivity of 2.5. omega. cm.

And B4, preparing a smooth silicon wafer surface. And (3) selecting a potassium hydroxide alkali solution with the mass fraction of 40% to carry out isotropic corrosion on the silicon wafer to obtain the polished surface of the silicon wafer, wherein the reflectivity of the polished surface of the silicon wafer is 50%.

C4, cleaning the surface of the silicon wafer. The silicon wafer was cleaned with a 10% by mass hydrofluoric acid solution.

D4, oxidizing the surface of the silicon wafer. And preparing an oxide layer by using a thermal oxidation method, wherein the oxidation temperature is set to be 630 ℃, the flow of introduced oxygen is 3000sccm, the flow of introduced nitrogen is 11000sccm, and the oxygen introduction time is 15min, so that the thickness of the obtained oxide layer is about 1.9 nm.

E4, double-sided deposition of in-situ phosphorus-silicon film (in-situ phosphorus-silicon film/oxide layer/undoped silicon film). In an LPCVD deposition system, a 100 nanometer in-situ phosphorus-doped silicon film is deposited on the surface of a non-doped silicon film by using phosphine and silane gases, wherein the flow ratio of the phosphine to the silane of the doped silicon film is 0.4: 100; closing phosphine and silane gases, vacuumizing, and introducing oxygen into the furnace to form an oxide layer on the surface of the in-situ phosphorus-doped silicon film; and depositing a 100nm undoped silicon film on the surface of the oxide layer.

F4, ion implantation is carried out on the non-doped silicon film. The implantation dosage is required to be greater than the concentration of phosphorus atoms in the inner doped silicon film.

G4, and annealing the silicon film at high temperature. Phosphorus atoms in the silicon thin film are activated, the annealing temperature is 910 ℃, and the annealing time is 40 minutes.

H4, and performance testing. ECV test doping concentration.

After high-temperature annealing activation, because of the existence of the oxide layer in the film layer, the interdiffusion of phosphorus atoms is prevented, and the concentration distribution of different phosphorus atoms in the silicon film is realized. The faster growth rate of the outer undoped silicon film can shorten the process time compared to example 1.

Example 3

Example 3 of a fabrication method according to an embodiment of the present disclosure provides for the preparation of a graded in-situ phosphorus doped silicon film (comprising a doped silicon film and an in-situ silicon oxide layer) by the steps of:

a5, selecting a silicon wafer. A single crystal N-type silicon wafer was selected, which had a bulk resistivity of 2.5. omega. cm.

And B5, preparing a smooth silicon wafer surface. And (3) selecting a potassium hydroxide alkali solution with the mass fraction of 40% to carry out isotropic corrosion on the silicon wafer to obtain the polished surface of the silicon wafer, wherein the reflectivity of the polished surface of the silicon wafer is 50%.

C5, cleaning the surface of the silicon wafer. The silicon wafer was cleaned with a 10% by mass hydrofluoric acid solution.

D5, oxidizing the surface of the silicon wafer. And preparing an oxide layer by using a thermal oxidation method, wherein the oxidation temperature is set to be 630 ℃, the flow of introduced oxygen is 3000sccm, the flow of introduced nitrogen is 11000sccm, and the oxygen introduction time is 15min, so that the thickness of the obtained oxide layer is about 1.9 nm.

E5, double-sided deposition of in-situ phosphorus-silicon film (in-situ phosphorus-silicon film/oxide layer/undoped silicon film). In an LPCVD deposition system, a 100 nanometer in-situ phosphorus-doped silicon film is deposited on the surface of a non-doped silicon film by using phosphine and silane gases, wherein the flow ratio of the phosphine to the silane of the doped silicon film is 0.4: 100; closing phosphine and silane gases, vacuumizing, and introducing oxygen into the furnace to form an oxide layer on the surface of the in-situ phosphorus-doped silicon film; and depositing a 100nm undoped silicon film on the surface of the oxide layer.

F5, performing high-temperature phosphorus diffusion on the silicon film and annealing. Phosphorus atoms are doped in the non-doped silicon layer through high-temperature diffusion, and meanwhile, the phosphorus atoms in the inner layer doped silicon film are activated.

G5, performance test. ECV test doping concentration.

After high-temperature annealing activation, because of the existence of the oxide layer in the film layer, the interdiffusion of phosphorus atoms is prevented, and the concentration distribution of different phosphorus atoms in the silicon film is realized. This step of ion implantation can be omitted compared to example 2.

Example 4

Example 4 of a fabrication method according to an embodiment of the present disclosure provides a method of fabricating a silicon-based solar cell using a graded in-situ phosphorous doped silicon film, comprising the steps of:

a6, selecting a silicon wafer. A single crystal N-type silicon wafer was selected, which had a bulk resistivity of 2.5. omega. cm.

B6, texturing the surface of the silicon wafer. And selecting 5% sodium hydroxide alkali solution by mass fraction to carry out anisotropic corrosion on the silicon wafer to obtain the textured silicon wafer surface, wherein the reflectivity of the textured silicon wafer surface is not more than 13%.

C6, preparing P-N section by boron diffusion. And preparing the P-N section by using a furnace tube boron diffusion method.

D6, the back surface is flat. And corroding the back surface of the silicon wafer by using a mixed solution of hydrofluoric acid, nitric acid and sulfuric acid, removing the borosilicate glass layer on the back surface, and simultaneously keeping the borosilicate glass layer on the front surface.

E6, oxidizing the surface of the silicon wafer. And preparing an oxide layer by using a thermal oxidation method, wherein the oxidation temperature is set to be 630 ℃, the flow of introduced oxygen is 3000sccm, the flow of introduced nitrogen is 11000sccm, and the oxygen introduction time is 15min, so that the thickness of the obtained oxide layer is about 1.9 nm.

F6, depositing the gradient phosphorus doped silicon film. Depositing a 50-nanometer in-situ phosphorus-doped silicon film on the surface of a silicon wafer by using phosphine and silane gases in an LPCVD deposition system, wherein the flow ratio of the phosphine to the silane of the doped silicon film is 0.4: 100; closing phosphine and silane gases, vacuumizing, and introducing oxygen into the furnace to form an oxide layer on the surface of the in-situ phosphorus-doped silicon film; and depositing a 50-nanometer in-situ phosphorus-doped silicon film on the surface of the oxide layer, wherein the flow ratio of phosphine to silane of the silicon-doped film is 0.6: 100.

G6, carrying out high-temperature annealing on the in-situ phosphorus doped silicon film. Phosphorus atoms in the silicon film are activated, the annealing temperature is 920 ℃, and the annealing time is 40 minutes.

H6, cleaning and removing the front surface silicon-coated film. Removing the front oxide layer by using hydrofluoric acid solution, and reserving the back silicon oxide layer; removing the front gradient phosphorus doped silicon film by using alkaline solution corrosion; and removing the front borosilicate glass layer by using a hydrofluoric acid solution.

I6, depositing an aluminum oxide passivation film on the front surface. And depositing a 4-nanometer aluminum oxide film on the front surface of the silicon wafer by using an atomic layer deposition method.

J6, double-sided silicon nitride coating. A silicon nitride film was deposited in a PECVD system, an 80 nm silicon nitride film was deposited on the front side, and a 70 nm silicon nitride film was deposited on the back side (as shown in figure 2).

K6, printing and sintering. And respectively printing silver paste on the front surface and the back surface, and then sintering.

L6, performance test. And (5) testing the electrical performance.

The battery prepared in the way has the advantages that the phosphorus element in the phosphorus-doped silicon film on the back surface is distributed in a gradient manner, so that the passivation effect of the surface of the silicon wafer can be ensured, and the FF of a battery device can be improved.

In the manufacturing method of the solar cell provided by the embodiment of the disclosure, the thickness of the oxide layer close to the silicon substrate is larger than that of the oxide layer far away from the silicon substrate, and the oxide layer with a smaller thickness is more favorable for tunneling electrons to pass through, so that electrons of the inner layer doped silicon film in the outermost layer doped silicon film layer can also tunnel through the oxide layer to reach the electrode, the contact resistance between the metal electrode layer and the outermost layer doped silicon film layer can be further reduced, and the filling factor is improved. Moreover, the concentration of the dopant in the doped silicon film layer is gradually increased from the surface of the silicon substrate to the direction far away from the silicon substrate, so that the doped silicon film layer on the side close to the electrode has the maximum concentration of the dopant, ohmic contact between the metal electrode and the doped silicon film is favorably formed, the metal-silicon contact resistance is reduced, and the filling factor is improved; and the doped silicon film close to the surface of the silicon substrate has lower dopant concentration, so that phosphorus atoms can be prevented from penetrating through the tunneling oxide layer in the subsequent high-temperature activation process to reduce the passivation effect, and the highly doped silicon film layer far away from the surface end of the silicon wafer can further enhance the electron tunneling to reach the electrode through the oxide layer, thereby being beneficial to reducing the contact resistance and improving the filling factor. And by arranging the oxide layer between the doped silicon film layers, dopants such as n-type dopants, for example, phosphorus can be prevented from diffusing into the adjacent doped silicon film layers during high-temperature annealing, so that a concentration gradient of the dopants is formed, the doped silicon film with a lower dopant concentration is provided at the surface of the silicon substrate to improve the passivation effect of the silicon substrate, and the contact resistance of the electrode and the doped silicon film can be reduced by improving the dopant concentration of the doped silicon film far away from the silicon substrate.

The following points need to be explained:

(1) the drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to the common design.

(2) For purposes of clarity, the thickness of layers or regions in the figures used to describe embodiments of the present disclosure are exaggerated or reduced, i.e., the figures are not drawn on a true scale. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.

(3) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims (8)

1. A solar cell, comprising:

a silicon substrate;

at least one layer pair disposed on a surface of the silicon substrate,

wherein each layer pair of the at least one layer pair comprises:

the oxide layer is arranged on one side of the layer pair close to the silicon substrate;

a doped silicon film layer arranged on one side of the oxide layer far away from the silicon substrate,

wherein the thickness of the oxide layer closest to the silicon substrate in the at least one layer pair is greater than the thickness of the other oxide layers in the at least one layer pair.

2. The solar cell of claim 1, wherein the oxide layer in the at least one layer pair has a thickness that decreases in a direction from the surface of the silicon substrate to a distance away from the silicon substrate.

3. The solar cell of claim 1, wherein the thickness of the other oxide layers in the at least one layer pair, except for the oxide layer closest to the silicon substrate, is the same.

4. The solar cell of claim 2, wherein the oxide layer of the outermost layer of the at least one layer pair has a thickness less than the thickness of the other oxide layers of the at least one layer pair.

5. The solar cell according to any of claims 1-4, wherein the oxide layer of the at least one layer pair closest to the silicon substrate has a thickness greater than 1.8nm and equal to or less than 2.5nm, and the thickness of the other oxide layers removed from the oxide layer closest to the silicon substrate is less than 1.8 nm.

6. The solar cell of claim 5, wherein the silicon substrate is an n-type substrate, the doped silicon film layer is an n-type doped silicon film layer, and the doping concentration of the n-type dopant in the n-type doped silicon film layer in the at least one layer pair gradually increases in a direction from the surface of the silicon substrate to a direction away from the silicon substrate.

7. The solar cell of claim 5, further comprising:

and the electrode is arranged on one side of the at least one layer pair far away from the silicon substrate.

8. The solar cell of claim 5, wherein the number of the at least one layer pair is 2-50.

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