CN215896415U - Different-polarity passivation contact structure, battery, assembly and system - Google Patents
Different-polarity passivation contact structure, battery, assembly and system Download PDFInfo
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Abstract
The utility model discloses a passivation contact structure with different polarities, a battery, a component and a system; the passivation contact structure comprises a silicon substrate, a dielectric layer arranged on at least one surface of the silicon substrate, a first polycrystalline silicon doping layer and a second polycrystalline silicon doping layer which are arranged on the surface of the dielectric layer and have different doping polarities, a polycrystalline silicon layer arranged between the first polycrystalline silicon doping layer and the second polycrystalline silicon doping layer, a third polycrystalline silicon doping layer which is arranged on the surface of the first polycrystalline silicon doping layer, has the same doping polarity and is higher than the first polycrystalline silicon doping layer, and a fourth polycrystalline silicon doping layer which is arranged on the surface of the second polycrystalline silicon doping layer, has the same doping polarity and is higher than the second polycrystalline silicon doping layer; the sum of the thicknesses of the first and third polycrystalline silicon doped layers is greater than that of the polycrystalline silicon layer, and the sum of the thicknesses of the second and fourth polycrystalline silicon doped layers is greater than that of the polycrystalline silicon layer; the dielectric layer has a thickness of 0.9 to 2.9 nm. The passivation contact structure can reduce metal contact recombination and contact resistance, and improve the short-circuit current, the double-sided rate and the photoelectric conversion efficiency of the battery.
Description
Technical Field
The utility model relates to the technical field of solar cells, in particular to a passivation contact structure with different polarities, a cell, a module and a system.
Background
At present, the solar cell technology with the highest mass production efficiency in the photovoltaic industry is a passivation Contact technology, namely a top Oxide Passivated Contact (TOPCon) cell technology. The TOPCon battery technology mainly combines an ultrathin tunneling oxide layer (such as a silicon oxide layer) with a heavily doped polysilicon layer, so that the silicon oxide layer reduces the interface state density between a silicon substrate and Poly-Si through chemical passivation, and meanwhile, most carriers are transported through a tunneling principle, while minority carriers are difficult to tunnel through the silicon oxide layer due to a higher potential barrier and a Poly-Si field effect; therefore, better surface passivation and contact performance can be obtained, and the solar cell has higher open-circuit voltage and lower contact resistance. In addition, the IBC (indirect back contact) battery has no grid line shielding on the front surface, so that the metal electrode structures of the front surface light trapping structure and the back surface can be optimized to the greatest extent, and the IBC battery has higher short-circuit current density and higher filling factor. Therefore, the currently developed high efficiency solar cell adopts POLO-IBC cell technology which combines TOPCon cell technology with high open circuit voltage and low contact resistance with IBC cell technology with high short circuit current density and high fill factor, and the cell technology is applied by ISFH research institute and obtains a solar cell with 26.1% photoelectric conversion efficiency.
However, the photoelectric conversion efficiency of the conventional back junction solar cell is still not high, and no matter the TOPCon cell technology or the POLO-IBC cell technology, the main reason for this is that the metal contact recombination and the high contact resistance are the main reasons for further improving the photoelectric conversion efficiency of the back junction solar cell. Moreover, since a complicated and expensive photolithographic mask technology is required in the preparation process of the interdigital structure on the back surface of the conventional IBC cell, if the interdigital structure is fused with the passivation contact structure, the complexity of the preparation process of the back junction solar cell is increased, the manufacturing cost is greatly increased, and the mass production is difficult to realize. Based on this, utility model CN201910873413.3 discloses a preparation method of local passivation contact structure, although this preparation method need not extra mask, it still carries out oxidation, washing and removes the oxide layer in the undoped region, alkali etching and removes the polysilicon layer in the undoped region and washing and removes the remaining oxide layer in proper order after high temperature annealing, and this local passivation contact structure can be prepared, its preparation method is still relatively complicated, even if apply it to the back junction solar cell, still can lead to the preparation technology of back junction solar cell to be relatively complicated, and its local passivation contact structure's that forms short-circuit current and two-sided rate are low, still can influence the improvement of the photoelectric conversion efficiency of back junction solar cell.
SUMMERY OF THE UTILITY MODEL
One of the objectives of the present invention is to provide a passivation contact structure with different polarities, which can significantly reduce metal contact recombination and contact resistance, and can improve short-circuit current and double-sided rate of a solar cell when applied to the solar cell (e.g., TBC cell), thereby further improving photoelectric conversion efficiency of the solar cell.
It is a further object of the present invention to provide a battery having a passivated contact structure with different polarities.
The utility model also aims to provide a solar cell module.
The fourth objective of the present invention is to provide a solar cell system.
Based on the above, the utility model discloses a passivation contact structure with different polarities, which comprises a silicon substrate, a dielectric layer arranged on at least one surface of the silicon substrate, a first polycrystalline silicon doping layer and a second polycrystalline silicon doping layer which are arranged on the surface of the dielectric layer and have different doping polarities, a polycrystalline silicon layer arranged between the first polycrystalline silicon doping layer and the second polycrystalline silicon doping layer, a third polycrystalline silicon doping layer which is arranged on the surface of the first polycrystalline silicon doping layer, has the same doping polarity and is higher than the first polycrystalline silicon doping layer, and a fourth polycrystalline silicon doping layer which is arranged on the surface of the second polycrystalline silicon doping layer, has the same doping polarity and is higher than the second polycrystalline silicon doping layer; the sum of the thicknesses of the first polycrystalline silicon doped layer and the third polycrystalline silicon doped layer is greater than the thickness of the polycrystalline silicon layer, and the sum of the thicknesses of the second polycrystalline silicon doped layer and the fourth polycrystalline silicon doped layer is greater than the thickness of the polycrystalline silicon layer; the thickness of the dielectric layer is 0.9-2.9 nm.
Preferably, the polysilicon layer is an intrinsic polysilicon structure.
Preferably, the crystallization rate of the polysilicon layer is greater than that of the third polysilicon doping layer, and the crystallization rate of the first polysilicon doping layer is greater than that of the third polysilicon doping layer; the crystallization rate of the polycrystalline silicon layer is greater than that of the fourth polycrystalline silicon doped layer, and the crystallization rate of the second polycrystalline silicon doped layer is greater than that of the fourth polycrystalline silicon doped layer.
Preferably, the silicon substrate is an N-type crystalline silicon substrate.
Preferably, the raw material of the third polysilicon doping layer is silicon slurry doped with phosphorus, and the doping atoms of the first polysilicon doping layer are phosphorus atoms; the raw material of the fourth polycrystalline silicon doped layer is silicon slurry doped with boron, and the doping atoms of the second polycrystalline silicon doped layer are boron atoms.
Preferably, the material of the dielectric layer is one or a combination of more of silicon oxide, aluminum oxide and chromium oxide.
Preferably, the thickness of the dielectric layer is 1-1.4 nm.
The utility model also discloses a battery, which comprises the passivation contact structure with different polarities, a back passivation film arranged on the surface of the passivation contact structure, a first metal electrode arranged on the surface of the third polycrystalline silicon doped layer and extending out of the back passivation film, a second metal electrode arranged on the surface of the fourth polycrystalline silicon doped layer and extending out of the back passivation film, an n + front field arranged on the front surface of the silicon substrate and a front passivation film arranged on the surface of the n + front field.
Preferably, the front surface of the silicon substrate is a pyramid-shaped light trapping structure, and the n + front field is arranged on the surface of the light trapping structure; the back surface of the silicon substrate is of a planar structure.
The preparation process of the battery comprises the following preparation steps:
step 1, pretreating the silicon substrate to obtain a pretreated silicon substrate;
and 8, then, carrying out metallization treatment on the third polycrystalline silicon doping layer and the fourth polycrystalline silicon doping layer to form a first metal electrode on the third polycrystalline silicon doping layer and a second metal electrode on the fourth polycrystalline silicon doping layer, so as to obtain the battery with the passivation contact structures with different polarities.
Preferably, in step 1, the pretreatment method is alkali treatment or acid treatment; after pretreatment, the front surface of the silicon substrate is a pyramid-shaped light trapping structure, and the back surface of the silicon substrate is a plane structure;
in step 2, after the pretreatment, a front surface PSG film is formed on the n + front field surface;
in step 6, after the heat treatment, a back surface PSG film is further formed on the surface of the third polysilicon doping layer, and a back surface BSG film is formed on the surface of the fourth polysilicon doping layer.
Further preferably, after the step 6, a step of performing a chemical cleaning process to remove the front mask, the front PSG film, the back PSG film and the back BSG film is further included; the chemical cleaning treatment is performed using an acid solution.
Preferably, in step 2, the n + front field is prepared by ion implantation, spin coating or diffusion;
in step 3, the preparation method of the front mask is a chemical vapor deposition method, a thermal oxidation method or a normal pressure chemical vapor deposition method;
in step 5, the preparation method of the amorphous silicon layer is a physical vapor deposition method, a low-pressure chemical vapor deposition method, a plasma chemical vapor deposition method or a normal-pressure chemical vapor deposition method;
in the step 6, the silicon slurry containing doping atoms is selectively doped by a screen printing method or an ink-jet method; the two silicon slurries containing doping atoms with different doping polarities are respectively silicon slurry containing phosphorus doping atoms and silicon slurry containing boron doping atoms;
in step 7, the passivation treatment method is an atomic layer deposition method, a chemical vapor deposition method or an atmospheric pressure chemical vapor deposition method;
in step 8, the metallization treatment step is: and the third polycrystalline silicon doping layer is sintered after being printed with silver paste to form the first metal electrode, and the fourth polycrystalline silicon doping layer is sintered at high temperature after being printed with silver-aluminum paste to form the second metal electrode.
The utility model also discloses a solar cell module which comprises a front material layer, a front packaging layer, a cell, a back packaging layer and a back material layer which are sequentially arranged from top to bottom, wherein the cell is the cell with the passivation contact structure with different polarities.
The utility model also discloses a solar cell system which comprises one or more than one solar cell module, wherein the solar cell module is the solar cell module.
Compared with the prior art, the utility model at least comprises the following beneficial effects:
1. the passivation contact structure with different polarities can be applied to a solar cell, the heavily doped third polycrystalline silicon doping layer on the outer layer is in contact with the first metal electrode, and the heavily doped fourth polycrystalline silicon doping layer on the outer layer is in contact with the second metal electrode; thus, the metal contact recombination can be remarkably reduced, and the contact resistance can also be reduced.
2. The sum of the thicknesses of the first polycrystalline silicon doped layer and the third polycrystalline silicon doped layer is greater than the thickness of the polycrystalline silicon layer, and the sum of the thicknesses of the second polycrystalline silicon doped layer and the fourth polycrystalline silicon doped layer is greater than the thickness of the polycrystalline silicon layer; the thickness of the polycrystalline silicon layer is smaller, so that after the passivation contact structure with different polarities is applied to a solar cell (such as a TBC cell), the thickness of the polycrystalline silicon layer in a back non-contact area can be reduced, on one hand, the parasitic absorption of carriers can be reduced, the short-circuit current can be improved, and on the other hand, the double-sided rate can be improved; thus, the photoelectric conversion efficiency of the solar cell can be further improved.
3. When the doping concentration of the first polycrystalline silicon doping layer is smaller than that of the third polycrystalline silicon doping layer, the first polycrystalline silicon doping layer and the second polycrystalline silicon doping layer with smaller doping concentrations and the dielectric layer can jointly play a field passivation role, and therefore the field passivation effect of the passivation contact structure is enhanced.
4. The thickness of the polycrystalline silicon layer is smaller, so that the consumption of raw materials of the polycrystalline silicon layer can be reduced by reducing the thickness of the polycrystalline silicon layer in the back non-contact area, and the production cost is further reduced.
Drawings
Fig. 1 is a schematic structural diagram of a passivation contact structure with different polarities according to this embodiment.
Fig. 2 is a schematic structural diagram of a battery of the present embodiment.
Fig. 3 is a schematic structural diagram of a silicon substrate after step 2 in the battery manufacturing process of this embodiment.
Fig. 4 is a schematic structural diagram of the silicon substrate after step 3 in the battery manufacturing process of this embodiment.
Fig. 5 is a schematic structural diagram of the silicon substrate after step 4 in the battery manufacturing process of this embodiment.
Fig. 6 is a schematic structural diagram of the silicon substrate after the step 5 in the process for manufacturing the battery of the embodiment.
Fig. 7 is a schematic structural diagram of the silicon substrate after step 6 in the process for manufacturing a battery according to this embodiment.
Fig. 8 is a schematic structural diagram of the silicon substrate after step 7 in the battery manufacturing process of this embodiment.
The reference numbers illustrate: a front-side passivation film 1; a front mask 2; front side PSG film 3; n + top field 4; a silicon substrate 5; a dielectric layer 6; an amorphous silicon layer 7; a polysilicon layer 8; a first polysilicon doping layer 9; a second polysilicon doping layer 10; a third polysilicon doping layer 11; a fourth polysilicon doping layer 12; a back surface PSG film 13; a back BSG film 14; a back surface passivation film 15; a first metal electrode 16; and a second metal electrode 17.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Examples
A passivation contact structure with different polarities in the present embodiment, referring to fig. 1, includes a silicon substrate 5, a dielectric layer 6, a polysilicon layer 8, a first polysilicon doped layer 9, a second polysilicon doped layer 10, a third polysilicon doped layer 11, and a fourth polysilicon doped layer 12. The dielectric layer 6 is disposed on the front and/or back of the silicon substrate 5, and the first polysilicon doping layer 9, the polysilicon layer 8 and the second polysilicon doping layer 10 are alternately disposed on the surface of the dielectric layer 6.
Wherein, the silicon substrate 5 is an N-type crystalline silicon substrate. The material of the dielectric layer 6 is one or a combination of more of silicon oxide, aluminum oxide and chromium oxide; the dielectric layer 6 mainly serves for interface passivation and tunneling. Specifically, the thickness of the dielectric layer 6 is 0.9-2.9 nm; preferably, the thickness of the dielectric layer 6 is 1 to 1.4nm, and more preferably 1.2 nm.
The doping concentration of the third polycrystalline silicon doping layer 11 is greater than that of the first polycrystalline silicon doping layer 9, and the doping polarities of the first polycrystalline silicon doping layer 9 and the third polycrystalline silicon doping layer 11 are the same; the doping concentration of the fourth polycrystalline silicon doping layer 12 is greater than that of the second polycrystalline silicon doping layer 10, and the doping polarity of the second polycrystalline silicon doping layer 10 is the same as that of the fourth polycrystalline silicon doping layer 12; the doping polarities of the first polycrystalline silicon doping layer 9 and the second polycrystalline silicon doping layer 10 are different, specifically, the raw material of the third polycrystalline silicon doping layer 11 is silicon slurry doped with phosphorus, and the doping atoms of the first polycrystalline silicon doping layer 9 are phosphorus atoms, so that the first polycrystalline silicon doping layer 9 and the third polycrystalline silicon doping layer 11 are both doped with phosphorus and have the same doping polarity; the raw material of the fourth polysilicon doping layer 12 is silicon slurry doped with boron, and the doping atoms of the second polysilicon doping layer 10 are boron atoms, so that the second polysilicon doping layer 10 and the fourth polysilicon doping layer 12 are both doped with boron, the doping polarities are the same, and the doping polarities of the first polysilicon doping layer 9 and the second polysilicon doping layer 10 are doped with phosphorus and boron respectively, so that the doping polarities are different. In addition, the first polysilicon doping layer 9 and the second polysilicon doping layer 10 with smaller doping concentration can play a role of field passivation together with the dielectric layer 6, thereby further enhancing the field passivation function of the passivation contact structure.
The sum of the thicknesses of the first polycrystalline silicon doped layer 9 and the third polycrystalline silicon doped layer 11 is greater than the thickness of the polycrystalline silicon layer 8, and the sum of the thicknesses of the second polycrystalline silicon doped layer 10 and the fourth polycrystalline silicon doped layer 12 is also greater than the thickness of the polycrystalline silicon layer 8; that is, the thickness of the polysilicon layer 8 is small, so that the consumption of raw materials of the polysilicon layer 8 can be reduced by reducing the thickness of the polysilicon layer 8 in the non-contact region, thereby reducing the production cost.
It should be noted that the polysilicon layer 8 is an intrinsic polysilicon structure, that is, an undoped polysilicon structure, and the undoped polysilicon layer 8 is located between the first polysilicon doping layer 9 of the n + doping region and the second polysilicon doping layer 10 of the p + doping region, so the polysilicon layer 8 can perform a better p-n isolation function, and reduce the risk of leakage.
Referring to fig. 2, the battery of the present embodiment includes a front passivation film 1, an n + front field 4, a silicon substrate 5, a dielectric layer 6, a polysilicon layer 8, a first polysilicon doping layer 9, a second polysilicon doping layer 10, a third polysilicon doping layer 11, a fourth polysilicon doping layer 12, a back passivation film 15, a first metal electrode 16, and a second metal electrode 17.
The n + front field 4 is arranged on the front surface of the silicon substrate 5, and the front passivation film 1 is arranged on the surface of the n + front field 4; the arrangement of the dielectric layer 6, the polysilicon layer 8, the first polysilicon doping layer 9, the second polysilicon doping layer 10, the third polysilicon doping layer 11 and the fourth polysilicon doping layer 12 refers to a passivation contact structure with different polarities shown in fig. 1; the back passivation film 15 is arranged on the surface of the passivation contact structure, namely the back passivation film 15 covers the back of the whole cell; the first metal electrode 16 is disposed on the third polysilicon doped layer 11 and extends out of the rear passivation film 15, and the second metal electrode 17 is disposed on the fourth polysilicon doped layer 12 and extends out of the rear passivation film 15.
After the passivation contact structure with different polarities shown in fig. 1 is applied to a battery (e.g., a TBC battery), the outer heavily doped third polysilicon doped layer 11 contacts the first metal electrode 16, and the outer heavily doped fourth polysilicon doped layer 12 contacts the second metal electrode 17, so that the metal contact recombination can be significantly reduced, the contact resistance can be reduced, and the photoelectric conversion efficiency of the battery with the passivation contact structure with different polarities can be improved. Moreover, the thickness of the polycrystalline silicon layer 8 in the non-contact area on the back of the cell can be reduced, so that not only can the consumption of raw materials be reduced, but also the parasitic absorption of current carriers can be reduced, the short-circuit current of the solar cell can be improved, meanwhile, the light reflection can also be reduced, the light utilization rate of the solar cell can be improved, and further the double-sided rate of the solar cell can be improved; this can further improve the photoelectric conversion efficiency of the cell having the passivated contact structure with different polarities.
The structural change of the battery manufacturing process of this embodiment is shown in fig. 3 to 8, and the manufacturing process includes: firstly, preprocessing a silicon substrate 5, preparing an n + front field 4 on the front surface of the preprocessed silicon substrate 5, then preparing a front mask 2 on the front surface of the n + front field 4, preparing a dielectric layer 6 on the back surface of the preprocessed silicon substrate 5, then preparing an amorphous silicon layer 7 on the back surface of the whole dielectric layer 6, then selectively doping the back surface of the amorphous silicon layer 7 to locally prepare two silicon slurries containing doping atoms with different doping polarities on the back surface of the amorphous silicon layer 7 respectively, then performing heat treatment to selectively diffuse the parts of the two doping atoms to different areas in the amorphous silicon layer 7 respectively, simultaneously, under the action of high temperature, the amorphous structure of the amorphous silicon layer 7 is changed and converted into a polycrystalline silicon structure, namely, the polycrystalline silicon structure can form a first polycrystalline silicon doping layer 9, a polycrystalline silicon layer 8 and a second polycrystalline silicon doping layer 10 which are alternately arranged on the surface of the dielectric layer 6, meanwhile, one of the slurries containing the doping atoms forms a third polysilicon doping layer 11 with a doping concentration greater than that of the first polysilicon doping layer 9 on the surface of the first polysilicon doping layer 9, meanwhile, another silicon slurry containing doping atoms forms a fourth polysilicon doping layer 12 with a doping concentration greater than that of the second polysilicon doping layer 10 on the surface of the second polysilicon doping layer 10, then the surfaces of the n + front field 4 and the passivation contact structure are passivated to form a front passivation film 1 on the front side of the n + front field 4 and a back passivation film 15 on the back side of the passivation contact structure, and finally, metallizing the third polysilicon doping layer 11 and the fourth polysilicon doping layer 12 to form a first metal electrode 16 on the third polysilicon doping layer 11, and forming a second metal electrode 17 on the fourth polysilicon doping layer 12, so as to obtain the battery with the passivation contact structure with different polarities.
The preparation process of the battery in this embodiment includes the following specific steps:
step 1, selecting a proper silicon substrate 5, and preprocessing the silicon substrate 5 to enable the front surface of the silicon substrate 5 to be a pyramid-shaped light trapping structure and the back surface of the silicon substrate 5 to be a plane structure. The pretreatment method is alkali treatment or acid treatment, but not limited to these two pretreatment methods. Wherein, during the alkali treatment, an additive can be added to promote the pretreatment process.
And 2, preparing a lightly doped n + front field 4 on the front surface of the pretreated silicon substrate 5, wherein the preparation method of the n + front field 4 is an ion implantation method, a spin coating method or a diffusion method, but the preparation method is not limited to the above method. The method for preparing the n + front field 4 by adopting the ion implantation method comprises the following steps: and (2) performing ion implantation on the front surface of the silicon substrate 5 under the conditions of a traction voltage of 10-15 KeV and a beam current of 30-60 mA, and performing annealing treatment after the ion implantation is completed, wherein the sheet resistance after the annealing is 300-600 omega/sqr, namely an n + front field 4 and a front surface PSG film 3 are formed on the front surface of the silicon substrate 5, and the structure of the front surface PSG film is shown in FIG. 3.
And 3, preparing a front mask 2 on the surface of the front PSG film 3. Among the methods for preparing the front mask 2, there are a chemical vapor deposition method (PECVD), a thermal oxidation method, or an atmospheric pressure chemical vapor deposition method (APCVD).
In an example of this embodiment, the step of preparing the front mask 2 by using the PECVD method includes: at a pressure of 1300-1500 mTorr and a power of 7000-9000W, SiH4:N2Preparing a front side PSG film 3 on the surface thereof at a temperature of 400-500 ℃ for 25-35 min at a ratio of 1:10 to prepare a front side mask 2 made of silicon oxide,the thickness of the front mask 2 is 150 to 250 nm. Of course, other materials of the front mask, such as a silicon nitride front mask and a silicon oxynitride front mask, may also be prepared by other methods. The resulting structure after step 3 is shown in FIG. 4.
And 4, preparing a dielectric layer 6 on the back of the pretreated silicon substrate 5. In an example of this embodiment, when the material of the dielectric layer 6 is silicon oxide, the method for preparing the dielectric layer 6 is nitric acid oxidation, high temperature thermal oxidation or ozone oxidation, but is not limited to the above method for preparing the dielectric layer 6.
Specifically, the steps of preparing the silicon oxide by a nitric acid oxidation method are as follows: and (3) placing the pretreated silicon substrate 5 in a nitric acid solution with the mass fraction of 45-80% to react for 4-8 min at the reaction temperature of 90-100 ℃, and after the reaction is finished, quickly drying the silicon substrate 5 by using a nitrogen gun to obtain silicon oxide with the thickness of 0.9-2.9 nm on the back surface of the silicon substrate 5, wherein the structure of the silicon oxide is shown in fig. 5.
In an example of this embodiment, the preparation process of the LPCVD method is as follows: under vacuum of less than 7X 10-3Introducing SiH under the condition of Torr and the temperature of 550-700 DEG C4Then the preparation reaction is carried out for 10-40 min, and then the vacuum pumping is carried out to confirm the dangerous gas SiH4After being pumped out, nitrogen is introduced to normal pressure, and after being cooled and taken out, a layer of amorphous silicon layer 7 can be prepared on the surface of the dielectric layer 6, and the structure of the amorphous silicon layer is shown in fig. 6.
The method for carrying out selective doping treatment by adopting a screen printing method comprises the following steps: respectively printing boron-doped silicon slurry and phosphorus-doped silicon slurry with different doped polarities, drying at the temperature of 100-400 ℃ for 5-20 min after printing, and performing heat treatment at the temperature of 700-1000 ℃ for 10-30 min after drying; thus, after the heat treatment is completed, a first polysilicon doping layer 9, a third polysilicon doping layer 11 with a doping concentration greater than that of the first polysilicon doping layer 9 and arranged on the surface of the first polysilicon doping layer 9, and a back PSG film 13 arranged on the third polysilicon doping layer 11 are formed in the n + doping region on the surface of the dielectric layer 6, and a polysilicon layer 8 located on the side surface of the first polysilicon doping layer 9 is formed on the surface of the dielectric layer 6; preferably, the doping concentration of the third polysilicon doping layer 11 is 1 to 50 times of the doping concentration of the first polysilicon doping layer 9. Similarly, after the thermal treatment is completed, a second polysilicon doping layer 10, a fourth polysilicon doping layer 12 with a doping concentration greater than that of the second polysilicon doping layer 10 and disposed on the surface of the second polysilicon doping layer 10, and a back BSG film 14 disposed on the surface of the fourth polysilicon doping layer 12 are simultaneously formed in the p + doping region on the surface of the dielectric layer 6, and the polysilicon layer 8 is located between the first polysilicon doping layer 9 and the second polysilicon doping layer 10. Preferably, the doping concentration of the fourth polysilicon doping layer 12 is 1 to 50 times of the doping concentration of the second polysilicon doping layer 10. After step 6, the structure is shown in FIG. 7.
In step S6, the method of screen printing is used to print the silicon slurry containing phosphorus dopant atoms and the silicon slurry containing boron dopant atoms locally onto a specific region of the amorphous silicon layer 7, so that the first polysilicon doping layer 9, the second polysilicon doping layer 10, the third polysilicon doping layer 11 and the fourth polysilicon doping layer 12 can be synchronously prepared by only one heat treatment without photolithography and multi-step masking, which can greatly simplify the process flow of passivating the contact structure and improve the production efficiency. Moreover, the area without printing the silicon slurry containing phosphorus doping atoms and the area without printing the silicon slurry containing boron doping atoms can not be doped, and the polysilicon layer 8 positioned between the first polysilicon doping layer 9 and the second polysilicon doping layer 10 can be formed, so that the doped area and the non-doped area in the interdigital structure of the cell can be accurately controlled to prevent electric leakage.
And 7, after local doping treatment, carrying out chemical cleaning treatment to remove the front mask 2, the front PSG film 3, the back PSG film 13 and the back BSG film 14. Wherein, the chemical cleaning treatment adopts acid solution. After the chemical cleaning process, the structure is shown in fig. 8.
And 8, after the chemical cleaning treatment, passivating the n + front field 4 and the surface of the passivation contact structure to form a front passivation film 1 on the surface of the n + front field 4 and a back passivation film 15 on the surface of the passivation contact structure. The passivation treatment method is Atomic Layer Deposition (ALD), chemical vapor deposition (PECVD) or Atmospheric Pressure Chemical Vapor Deposition (APCVD). Preferably, the surfaces of the n + front field 4 and the passivation contact structure are passivated synchronously, so that the preparation process flow of the battery is further simplified, and the production efficiency is improved.
And 9, after the passivation treatment is finished, performing metallization treatment on the third polycrystalline silicon doping layer 11 and the fourth polycrystalline silicon doping layer 12 to form a first metal electrode 16 on the third polycrystalline silicon doping layer 11 and a second metal electrode 17 on the fourth polycrystalline silicon doping layer 12. The metallization treatment may be metal electrode printing treatment, specifically, silver paste is screen-printed on the third polysilicon doping layer 11 in the n + doping region and sintered to form the first metal electrode 16; the fourth polysilicon doped layer 12 of the p + doped region is screen printed with a silver aluminum paste electrode and sintered at high temperature to form the second metal electrode 17. Specifically, the sintering temperature is 800-900 ℃, the number of p + grid lines is 130, and the number of n + fine grid lines is 131. After the metallization treatment, the preparation of the battery with the passivated contact structure with different polarities is completed, and the structure is shown in fig. 2. In the step 9, the metal electrode is prepared by screen printing, and the metal electrode and the doped layer can be accurately aligned by overprint alignment, so that the leakage risk is further reduced.
The first metal electrode 16 in the obtained cell is in contact with the heavily doped third polycrystalline silicon doped layer 11 in the n + doped region, so that the metal contact recombination can be effectively reduced, and the contact resistance can be reduced; similarly, the second metal electrode 17 is in contact with the heavily doped fourth polysilicon doped layer 12 in the p + doped region, so that metal contact recombination can be effectively reduced, contact resistance can be reduced, the first polysilicon doped layer 9 and the second polysilicon doped layer 10 with the sub-doping concentration can play a better field passivation role, and meanwhile, the undoped polysilicon layer 8 between p and n can play a better p-n isolation role, so that the leakage risk is reduced; the crystallization rate of the polycrystalline silicon layer 8 in the prepared battery is greater than that of the third polycrystalline silicon doping layer 11, the crystallization rate of the first polycrystalline silicon doping layer 9 is also greater than that of the third polycrystalline silicon doping layer 11, the crystallization rate of the polycrystalline silicon layer 8 is greater than that of the fourth polycrystalline silicon doping layer 12, and the crystallization rate of the second polycrystalline silicon doping layer 10 is also greater than that of the fourth polycrystalline silicon doping layer 12; thus, atoms playing a role in generating power in the silicon substrate 5 can be effectively prevented from being recombined by defects in the polycrystalline silicon layer 8 with a low crystallization rate, the first polycrystalline silicon doped layer 9 and the second polycrystalline silicon doped layer 10, and the power generation efficiency of the battery can be further improved. In addition, the preparation process of the battery does not need complex laser doping and back photoetching mask process, is compatible with the existing production line, has lower cost and is easy for mass production.
The embodiment also provides a solar cell module, which comprises a front material layer, a front packaging layer, a solar cell, a back packaging layer and a back material layer which are sequentially arranged from top to bottom, wherein the solar cell is the cell with the passivation contact structure with different polarities.
The embodiment also provides a solar cell system, which comprises one or more than one solar cell module, wherein the solar cell module is the solar cell module.
While preferred embodiments of the present invention have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the embodiments of the utility model.
The technical solutions provided by the present invention are described in detail above, and the principle and the implementation of the present invention are explained in this document by applying specific examples, and the descriptions of the above examples are only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (10)
1. A passivation contact structure with different polarities is characterized by comprising a silicon substrate, a dielectric layer arranged on at least one surface of the silicon substrate, a first polycrystalline silicon doping layer and a second polycrystalline silicon doping layer which are arranged on the surface of the dielectric layer and have different doping polarities, a polycrystalline silicon layer arranged between the first polycrystalline silicon doping layer and the second polycrystalline silicon doping layer, a third polycrystalline silicon doping layer which is arranged on the surface of the first polycrystalline silicon doping layer, has the same doping polarity and is higher than the first polycrystalline silicon doping layer, and a fourth polycrystalline silicon doping layer which is arranged on the surface of the second polycrystalline silicon doping layer, has the same doping polarity and is higher than the second polycrystalline silicon doping layer; the sum of the thicknesses of the first polycrystalline silicon doped layer and the third polycrystalline silicon doped layer is greater than the thickness of the polycrystalline silicon layer, and the sum of the thicknesses of the second polycrystalline silicon doped layer and the fourth polycrystalline silicon doped layer is greater than the thickness of the polycrystalline silicon layer; the thickness of the dielectric layer is 0.9-2.9 nm.
2. The passivated contact structure with different polarities according to claim 1, wherein the polysilicon layer is an intrinsic polysilicon structure.
3. The structure of claim 1, wherein the crystallization rate of the polysilicon layer is greater than the crystallization rate of the third polysilicon doped layer, and the crystallization rate of the first polysilicon doped layer is greater than the crystallization rate of the third polysilicon doped layer; the crystallization rate of the polycrystalline silicon layer is greater than that of the fourth polycrystalline silicon doped layer, and the crystallization rate of the second polycrystalline silicon doped layer is greater than that of the fourth polycrystalline silicon doped layer.
4. The passivated contact structure of claim 1 wherein the silicon substrate is an N-type crystalline silicon substrate.
5. The passivated contact structure with different polarities according to claim 1 wherein said dielectric layer is made of one of silicon oxide, aluminum oxide and chromium oxide.
6. The passivated contact structure with different polarities according to claim 1, wherein the thickness of the dielectric layer is 1 to 1.4 nm.
7. A battery, comprising the passivation contact structure with different polarities as claimed in any one of claims 1 to 5, a back passivation film disposed on the back surface of the passivation contact structure, a first metal electrode disposed on the surface of the third doped polysilicon layer and extending to the outside of the back passivation film, a second metal electrode disposed on the surface of the fourth doped polysilicon layer and extending to the outside of the back passivation film, and an n + front field disposed on the front surface of the silicon substrate and a front passivation film disposed on the surface of the n + front field.
8. The cell of claim 7, wherein the front surface of the silicon substrate is a pyramid-shaped light trapping structure, and the n + front field is disposed on the surface of the light trapping structure; the back surface of the silicon substrate is of a planar structure.
9. The utility model provides a solar module, includes front material layer, front packaging layer, battery, back packaging layer and the back material layer that from top to bottom sets gradually, its characterized in that: the battery is a battery according to any one of claims 7 to 8.
10. A solar cell system comprising one or more solar cell modules, characterized in that: the solar cell module is the solar cell module of claim 9.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115172478A (en) * | 2022-07-28 | 2022-10-11 | 浙江晶科能源有限公司 | Solar cell and photovoltaic module |
| AU2022205182B1 (en) * | 2022-04-27 | 2023-07-27 | Jinko Solar Co., Ltd. | Solar cell and production method thereof, photovoltaic module |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| AU2022205182B1 (en) * | 2022-04-27 | 2023-07-27 | Jinko Solar Co., Ltd. | Solar cell and production method thereof, photovoltaic module |
| CN115172478A (en) * | 2022-07-28 | 2022-10-11 | 浙江晶科能源有限公司 | Solar cell and photovoltaic module |
| CN115172478B (en) * | 2022-07-28 | 2024-01-23 | 浙江晶科能源有限公司 | Solar cell and photovoltaic module |
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