CN215578555U - Intelligent power device and frequency conversion equipment - Google Patents

Intelligent power device and frequency conversion equipment Download PDF

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Publication number
CN215578555U
CN215578555U CN202121180861.4U CN202121180861U CN215578555U CN 215578555 U CN215578555 U CN 215578555U CN 202121180861 U CN202121180861 U CN 202121180861U CN 215578555 U CN215578555 U CN 215578555U
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pin
chip
power
power device
lead
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CN202121180861.4U
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黄玲
史波
江伟
杨景城
秦明柳谦
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Gree Electric Appliances Inc of Zhuhai
Zhuhai Zero Boundary Integrated Circuit Co Ltd
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Gree Electric Appliances Inc of Zhuhai
Zhuhai Zero Boundary Integrated Circuit Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H01L2224/48096—Kinked the kinked part being in proximity to the bonding area on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4901—Structure
    • H01L2224/4903—Connectors having different sizes, e.g. different diameters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

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Abstract

The application belongs to the technical field of circuits and relates to an intelligent power device and frequency conversion equipment. The intelligent power device comprises a substrate and a power chip arranged on the substrate; the substrate is provided with a first pin and a second pin, the first pin is electrically connected with an external circuit, and the second pin is separated from a source line on the load side; the power chip is provided with a source electrode, and the source electrode of the power chip is connected to a first pin on the substrate through a first lead; the source of the power chip is connected to a second pin on the substrate through a second lead. By utilizing the intelligent power device provided by the embodiment of the application, the first pin and the second pin are arranged on the substrate, the first pin is electrically connected with an external circuit, and the second pin is separated from the source line of the load side, so that the source electrode connection inductance of the power chip can be reduced, the influence of driving voltage is not easily caused, and the power chip can realize high switching speed. The intelligent power device is applied to frequency conversion equipment, and the efficiency of the medium-sized to large-sized power switching power supply is improved.

Description

Intelligent power device and frequency conversion equipment
Technical Field
The application relates to the technical field of circuits, in particular to an intelligent power device and frequency conversion equipment.
Background
An Intelligent Power device (IPM) is an advanced Power switch device, and has the advantages of a large Power Transistor (GTR) such as high current, low saturation voltage and high withstand voltage, and the advantages of a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) such as high input impedance, high switching frequency and low driving Power. And logic, control, detection and protection circuits are integrated in the IPM, so that the IPM is more convenient to use, the volume of the system is reduced, the development time is shortened, the reliability of the system is enhanced, the IPM is suitable for the development direction of the current power device, and the IPM is more and more widely applied to the field of power electronics.
By modifying corresponding parameters in the chip design, the switching speed and the current capacity of the chip are improved. Along with the research and development upgrading of chip technology, after being applied to intelligent power device with the chip, along with the promotion of electric current, the lower bridge power chip just produces the shock more easily to the stray inductance that produces is just bigger.
Stray inductance means that the inductance is not intentionally designed for circuit design, but is additive or parasitic to something. The formula for the effect of stray inductance is Ls × dI/dt. According to the above formula, only the loop generating the current variation needs to consider the stray inductance Ls in the loop.
Referring to fig. 1 and 2, taking a MOSFET chip as an example, after the switching speed and the current capability of the MOSFET chip are increased, the source wire inductance packaged in the MOSFET chip starts to adversely affect the switching performance of the MOSFET chip.
In the conventional IPM package, the gate-source voltage (V)GS) After being applied to the MOSFET chip, a counter potential (V) is generatedLS＝LS×dIDDt), which are the source lead inductance (LSource) and the drain current slope (dI)DDt). The voltage drop caused by the back-emf voltage actually acts on the MOSFET chip, reducing the switching speed, especially the turn-on speed.
In the current IPM package, only three pins NU, NV, NW are respectively led out from the MOSFET chip to connect the external circuit. Therefore, when the IPM is applied to an external circuit, the MOSFET chip generates a large stray inductance, which causes a reduction in the switching speed of the MOSFET chip and gate oscillation.
SUMMERY OF THE UTILITY MODEL
The utility model provides an intelligent power device and frequency conversion equipment, aiming at solving the technical problem that a power chip is easy to generate larger stray inductance in the related technology.
In a first aspect, the present application provides a smart power device, comprising: the power chip comprises a substrate and a power chip mounted on the substrate;
the substrate is provided with a first pin and a second pin, the first pin is electrically connected with an external circuit, and the second pin is separated from a source line on the load side;
the power chip is provided with a source electrode, and the source electrode of the power chip is connected to a first pin on the substrate through the first lead; the source of the power chip is connected to a second pin on the substrate through the second lead.
Optionally, the wire diameter of the first lead is larger than the wire diameter of the second lead.
Optionally, the wire diameter of the first lead is L1, and the value range of L1 is 8mil < L1 ≤ 15 mil.
Optionally, the wire diameter of the second lead is L2, and the value range of L2 is 3mil or less and L2 or less and 8mil or less.
Optionally, the first pin and the second pin are both disposed close to the source of the corresponding power chip.
Optionally, the power chip includes at least one of an IGBT chip, an FRD chip, or a mosfet it chip.
Optionally, the number of the first pins and the number of the second pins are respectively equal to the number of the power chips; each power chip is connected with one first pin and one second pin respectively.
Optionally, the first pins include at least one of the following types of pins: NU pin, NV pin, and NW pin.
Optionally, the packaging structure of the smart power device comprises a copper-clad ceramic board packaging structure.
In a second aspect, the present application provides a frequency conversion device, which includes the above-mentioned intelligent power device.
Compared with the prior art, the technical scheme provided by the embodiment of the application has the following advantages:
through research, the main reason for generating stray inductance is the lead wire influence of the emitter or the source of the lower bridge power chip. Therefore, the intelligent power device provided by the embodiment of the application comprises a substrate and a power chip mounted on the substrate. The first pin is electrically connected with an external circuit, and the second pin is separated from a source line at the load side; the power chip is provided with a source electrode, and the source electrode of the power chip is connected to a first pin on the substrate through a first lead; the source of the power chip is connected to a second pin on the substrate through a second lead. Therefore, the source electrode connecting inductance of the power chip can be reduced, the influence of driving voltage is not easy to be caused, and the power chip can achieve high switching speed.
The frequency conversion equipment provided by the embodiment of the application comprises the intelligent power device. The intelligent power device is applied to frequency conversion equipment, can realize high switching speed, is beneficial to further improving the switching efficiency and improving the efficiency of medium-sized to large-sized power switching power supplies.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the utility model and together with the description, serve to explain the principles of the utility model.
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.
FIG. 1 is a circuit block diagram of an intelligent power device;
FIG. 2 is a schematic diagram of a smart power device;
fig. 3 is a circuit structure diagram of an intelligent power device according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of an intelligent power device according to an embodiment of the present application.
Reference numerals:
100. an intelligent power device; 110. a substrate; 120. a pad; 130. a power chip; 140. a first pin; 150. a second pin; 160. a first lead; 170. a second lead; 180. and a driving chip.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 3 and 4, a smart power device 100 provided by an embodiment of the present application includes: a substrate 110 and a power chip 130 mounted on the substrate 110.
A first pin 140 and a second pin 150 are arranged on the substrate 110, the first pin 140 is used for electrically connecting with an external circuit, and the second pin 150 is used for separating from a source line on a load side; the power chip 130 has a source, and the source of the power chip 130 is connected to the first pin 140 on the substrate 110 through the first lead 160; the source of the power chip 130 is connected to the second lead 150 on the substrate 110 through the second lead 170.
By using the intelligent power device 100 provided by the embodiment of the present application, the first pin 140 and the second pin 150 are disposed on the substrate 110, the first pin 140 is electrically connected to an external circuit, and the second pin 150 is separated from the source line of the load side, so that the source connection inductance of the power chip 130 can be reduced, the stray inductance in the loop is reduced, the switching speed of the power chip 130 is increased, the purpose of reducing loss and gate oscillation is achieved, and the efficiency of the switching power supply of the medium-sized to large-sized power device is further improved.
The smart power device 100 includes a driving chip 180, a first pin 140 connected to an external circuit, and a second pin 150 connected to a ground terminal of the driving chip 180. The external circuit is the load side. Through the second pin 150 and the second lead 170, external wiring can be directly performed from the second pin 150 without passing through the first lead 160, and the influence of the original reaction electromotive force on the gate voltage is reduced. The gate driving chip 180 built in the smart power device 100 greatly reduces the number of peripheral components, reduces failures caused by component failures, reduces the size of the smart power device 100 due to high integration level, and greatly improves reliability and space utilization rate.
The source of the power chip 130 is connected to the first pin 140 through the first lead 160, the source of the power chip 130 is connected to the second pin 150 through the second lead 170, and the first pin 140 is used for being connected to an external circuit, that is, may be connected to an external load side, and may also be grounded. The second pin 150 is connected to a functional pin of the driver chip 180 from outside the power chip 130. In this way, the second lead 170 is connected to the second pin 150, so that the second pin 150 is separated from the load side, thereby reducing the generation of stray inductance, increasing the switching speed of the power chip 130, and reducing loss and oscillation.
The wire diameter of the first lead 160 is larger than that of the second lead 170. The wire diameter of the second lead 170 needs to be smaller than that of the first lead 160, and the second lead 170 with a smaller wire diameter can limit the current passing through the second lead 170, so as to further reduce the stray inductance of the loop, thereby reducing the stray inductance of the power chip 130, improving the switching speed of the power chip 130, and achieving the purposes of reducing loss and gate oscillation.
The wire diameter of the first lead wire 160 is L1, and the value range of L1 is 8mil < L1 < 15 mil. The first lead 160 may have a wire diameter set at 9 mils, 10 mils, 12 mils, or 15 mils. The larger the wire diameter of the first lead 160, the larger the current allowed to pass. The wire diameter of the second lead wire 170 is L2, and the value range of L2 is 3mil or more and L2 or more and 8mil or less. The wire diameter range of the second lead wire 170 can be selected according to the magnitude of the current, the second lead wire 170 with the smaller wire diameter is adopted, and the second lead wire 170 is separated from a source wire on the load side, so that the current flowing through the second lead wire 170 is smaller, the purpose of passing the small current can be realized, and the generation of the larger stray inductance in the loop can be inhibited. When the current flowing through the second lead 170 is about 50A, a wire diameter of 6mil or 8mil may be selected. Of course, if the encapsulation layer is too small, a 3mil or 5mil gauge may be used.
The first pin 140 and the second pin 150 are both disposed near the source of the corresponding power chip 130. The first pin 140 and the second pin 150 are respectively led out from the position, close to the source electrode, of the power chip 130, and the second lead 170 is connected with the second pin 150, so that the power chip is separated from the source line on the load side, and the influence of driving voltage is not easily caused, so that the source electrode connection inductance of the power chip 130 is reduced, and the power chip 130 achieves high switching speed.
The power chip 130 includes at least one of an IGBT chip, an FRD chip, or a mosfet it chip.
An Insulated Gate Bipolar Transistor (IGBT for short) is a composite semiconductor device composed of a Transistor and a MOS Transistor. The IGBT chip is used as a novel electronic semiconductor device, has the characteristics of high input impedance, low voltage control power consumption, simple control circuit, high voltage resistance, large current bearing capacity and the like, and is widely applied to various electronic circuits.
In practical application, the switching speed of the IGBT chip is required to be as high as possible, and meanwhile, the switching time is reduced, and the switching loss is reduced. However, considering the influence of the parameters of the IGBT chip, the actual switching speed of the IGBT chip is still limited. The current change rate dI/dt means a change in current per unit time. In the turn-on and turn-off processes of the IGBT chip, the increase of the current change rate is beneficial to reducing the switching loss. Thus, the IGBT chip can realize a very fast turn-on speed. At the same time, however, the source lead inductance packaged in the IGBT chip also begins to adversely affect the switching performance of the IGBT chip.
The smart power device 100 provided by the embodiment of the present application includes a substrate 110 and an IGBT chip mounted on the substrate 110. A first pin 140 and a second pin 150 are arranged on the substrate 110, the first pin 140 is electrically connected with an external circuit, and the second pin 150 is separated from a source line on the load side; the power chip 130 has a source, and the source of the power chip 130 is connected to the first pin 140 on the substrate 110 through the first lead 160; the source of the power chip 130 is connected to the second lead 150 on the substrate 110 through the second lead 170.
In this way, the second pin 150 is led out from the source of the IGBT chip, and the second lead 170 is used to connect the source of the IGBT chip with the second pin 150, so that the source of the IGBT chip is separated from the source line on the load side, and thus the IGBT chip is not easily affected by the driving voltage of the driving chip 180, and the source connection inductance of the IGBT chip is reduced.
The intelligent power device 100 adopts an IC driving and protecting technology, a low saturation voltage drop IGBT chip technology and an advanced packaging technology, the power range of the intelligent power device can meet the requirement of a motor with the power of 0.75 kW-5.0 kW on the driving power, and the intelligent power device is particularly suitable for an inverter system for a variable frequency air conditioner. The IPM system can make the application apparatus smaller in size and higher in reliability.
The FRD chip is a Fast Recovery Diode (FRD) and can be used to cooperate with the switching of the IGBT chip.
MOSFET chips are field effect transistors that are widely used in analog and digital circuits. The field effect transistor is often used as an electronic switch for controlling the on/off of a load in a control loop, and can also be used as a controllable rectifier to realize ac to dc conversion.
The power chip 130 includes a lower bridge power chip. In the smart power device 100, the upper bridge power chip generates less stray inductance, so the generation of the stray inductance is basically concentrated in the lower bridge power chip.
The number of the first pins 140 and the number of the second pins 150 are respectively equal to the number of the power chips 130; each power chip 130 is connected to a first pin 140 and a second pin 150, respectively. The number of the power chips 130 arranged on the substrate 110 is greater than or equal to two, and the number of the first pins 140 and the second pins 150 is equal to the number of the power chips 130; each power chip 130 corresponds to one first pin 140 and one second pin 150, and the source of the power chip 130 is connected to the first pin 140 and the second pin 150 through a first lead 160 and a second lead 170, respectively.
When the number of the power chips 130 is multiple, the first pins 140 respectively disposed on the power chips 130 are independent from each other, and the number of the second pins 150 needs to correspond to the number of the first pins 140 in order to achieve the effect of reducing the stray inductance. For example, the number of the first pins 140 is three, the number of the second pins 150 is also three, and the three first pins 140 correspond to the three second pins 150 one to one. Of course, the first and second leads 160 and 170 also correspond to the first and second leads 140 and 150, respectively, in a one-to-one correspondence. Of course, the number of the first pins 140 and the second pins 150 may also be other values, for example, when the number of the power chips 130 is two or four, the number of the first pins 140 and the number of the second pins 150 are also two or four. In practical applications, the number of the power chips 130 is set to two, and the power chips can be applied to two-phase alternating current. The number of the power chips 130 is set to three, and may be applied to three-phase alternating current.
The first pins 140 include at least one of the following types of pins: NU pin, NV pin, and NW pin. In practice, the number of the first pins 140 is three, and the three first pins 140 include a NU pin, an NV pin, and an NW pin. The three first pins 140 are all lead-out pins of the source electrode of the lower bridge power chip, the three first pins 140 have the same function, but have different phases, and are respectively the lead-out pins of the source electrode of the U, V, W-phase lower bridge power chip, and can be used for inputting or outputting three-phase alternating current. Accordingly, the number of the second pins 150 is also three, and the three second pins 150 include an E1 pin, an E2 pin, and an E3 pin. The pin E1, the pin E2, and the pin E3 correspond to the pin NU, the pin NV, and the pin NW, respectively. By separately leading out the pin E1, the pin E2 and the pin E3, the functions of the original pin NU, pin NV and pin NW can be kept unchanged, and the external circuit can be used for separately detecting and sampling values such as voltage and the like of the three-phase power chip 130 of the lower bridge, so that the external operability is strong.
The package structure of the smart power device 100 includes a copper-clad ceramic board package structure. The Copper clad ceramic plate in the packaging structure of the Copper clad ceramic plate (DBC for short) is an electronic basic material which is made by directly sintering Copper foil on the surface of ceramic. The copper-clad ceramic plate has the advantages of good thermal conductivity, strong insulation, high reliability and the like, and is widely applied to packaging of an IGBT, a Laser Diode (LD) and a focusing photovoltaic (CPV). CPV converts concentrated sunlight directly into electrical energy through the photovoltaic effect. And because the copper foil is thicker, the thickness of the copper foil can reach 100-600 mu m, so that the copper-clad ceramic plate has obvious advantages in the field of IGBT and LD packaging.
The package structure of the smart power device 100 may also employ a hybrid package of a DBC and a Printed Circuit Board (PCB for short). The DBC technology is combined with the PCB, the upper surface of the chip is connected to the PCB through the metal bonding wire, the current conversion loop is controlled between layers of the PCB, the area of the current loop is greatly reduced, and then stray inductance parameters are reduced. Of course, the smart power device 100 includes but is not limited to a DBC package structure, and other structures capable of realizing the package of the smart power device 100 are all possible.
The smart power device 100 further includes a pad 120, the pad 120 being mounted on the substrate 110, and a power chip 130 being mounted on the pad 120.
The second pin 150 is electrically connected with the second lead 170, the second pin 150 is separated from the source line on the load side, external wiring can be directly performed from a port close to the power chip 130 without passing through the first lead 160, and the influence of the original reaction electromotive force on the gate voltage is reduced.
In summary, the smart power device 100 provided by the embodiment of the present invention includes a substrate 110 and a power chip 130 mounted on the substrate 110. A first pin 140 and a second pin 150 are arranged on the substrate 110, the first pin 140 is used for electrically connecting with an external circuit, and the second pin 150 is used for separating from a source line on a load side; the power chip 130 has a source, and the source of the power chip 130 is connected to the first pin 140 on the substrate 110 through the first lead 160; the source of the power chip 130 is connected to the second lead 150 on the substrate 110 through the second lead 170. Therefore, the source connection inductance of the power chip 130 can be reduced, so that the stray inductance in a loop is reduced, the switching speed of the power chip 130 is increased, the purposes of reducing loss and gate oscillation are achieved, and the efficiency of the switching power supply of the medium-sized to large-sized power device is further improved.
The fabrication process of the smart power device 100 is described in detail below:
first, the power chip 130 is designed. The power chip 130 of a reasonable specification is designed according to the performance and function of the product.
Second, the substrate 110 is designed. The substrate 110, the shape of the island, and the length, width, and height of the substrate 110 are designed according to circuit characteristics and the realization of product performance.
And thirdly, designing the appearance of the product. According to the shape and size of the substrate 110 and the layout design of the power chips 130 on the substrate 110, the length, width and height of the product and the bonding pads 120 are determined, and finally the appearance of the output product is determined.
And fourthly, designing a lead frame. The lead frame of the product is designed according to the internal structural layout of the product, and the pad 120 and the lead frame of the second lead 150 are designed according to the leads.
And fifthly, designing a mold. And designing a mold required by the product plastic package according to the plastic package mode of the product and the appearance of the product.
And sixthly, assembling. First, the power chip 130 is assembled with the substrate 110, and the power chip 130 is fixed. The power chip 130 and the pad 120 are then bonded by wire bonding.
And seventhly, packaging the product. And (3) carrying out embedding plastic packaging by using an injection molding press, a mold and a plastic packaging material. The embedding and packaging of the assembled substrate 110 are completed. And after the injection molding is finished, carrying out curing molding to finish the packaging. And finally, cutting ribs on the pins, and bending and forming the pins into products required by design.
The embodiment of the application also provides frequency conversion equipment, and the frequency conversion equipment comprises an intelligent power device 100. The intelligent power device 100 is applied to the frequency conversion equipment, so that high switching speed can be realized, further improvement of switching efficiency is facilitated, and the switching power supply efficiency of the medium-sized to large-sized power device is improved.
The intelligent power device 100 is composed of a high-speed IGBT chip and an optimized gate drive and protection circuit, plays an important role in various power conversion, the intelligent power device 100 is a key component of a power conversion part of a frequency conversion technology, is widely adopted in household appliances such as frequency conversion air conditioners, washing machines, refrigerators, microwave ovens and induction cookers besides being widely adopted in high-voltage, low-voltage and large-capacity frequency converters used in various industries, and has considerable application and market prospect in products such as various power supplies, electric locomotives and the like.
It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The foregoing are merely exemplary embodiments of the present invention, which enable those skilled in the art to understand or practice the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the utility model. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A smart power device, comprising: the power chip comprises a substrate and a power chip mounted on the substrate;
the substrate is provided with a first pin and a second pin, the first pin is electrically connected with an external circuit, and the second pin is separated from a source line on the load side;
the power chip is provided with a source electrode, and the source electrode of the power chip is connected to a first pin on the substrate through the first lead; the source of the power chip is connected to a second pin on the substrate through the second lead.
2. The smart power device of claim 1, wherein a wire diameter of the first lead is greater than a wire diameter of the second lead.
3. The intelligent power device as claimed in claim 2, wherein the wire diameter of the first lead is L1, and the value range of L1 is 8mil < L1 ≤ 15 mil.
4. The intelligent power device as claimed in claim 2, wherein the second lead has a wire diameter of L2, and the value range of L2 is 3mil or less and L2 or less and 8mil or less.
5. The smart power device according to any one of claims 1 to 4, wherein the first pin and the second pin are each disposed near a source of the corresponding power chip.
6. The smart power device of claim 1, wherein the power chip comprises at least one of an IGBT chip, an FRD chip, or a mosfet chip.
7. The smart power device according to claim 1, wherein the number of the first pins and the number of the second pins are respectively equal to the number of the power chips; each power chip is connected with one first pin and one second pin respectively.
8. The smart power device of claim 1 or 7, wherein the first pin comprises at least one of: NU pin, NV pin, and NW pin.
9. The smart power device of claim 1 wherein the package structure of the smart power device comprises a copper-clad ceramic board package structure.
10. Frequency conversion device, characterized in that it comprises a smart power device according to any of claims 1 to 9.
CN202121180861.4U 2021-05-28 2021-05-28 Intelligent power device and frequency conversion equipment Active CN215578555U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202121180861.4U CN215578555U (en) 2021-05-28 2021-05-28 Intelligent power device and frequency conversion equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202121180861.4U CN215578555U (en) 2021-05-28 2021-05-28 Intelligent power device and frequency conversion equipment

Publications (1)

Publication Number Publication Date
CN215578555U true CN215578555U (en) 2022-01-18

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Country Link
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