CN215577633U

CN215577633U - Display driving circuit and display panel

Info

Publication number: CN215577633U
Application number: CN202122034995.1U
Authority: CN
Inventors: 朱正勇; 张元波; 高琳华; 李志明; 马志丽
Original assignee: Kunshan Govisionox Optoelectronics Co Ltd
Current assignee: Kunshan Govisionox Optoelectronics Co Ltd
Priority date: 2021-08-26
Filing date: 2021-08-26
Publication date: 2022-01-18
Anticipated expiration: 2031-08-26

Abstract

The embodiment of the utility model discloses a display driving circuit and a display panel. The display drive circuit includes: a pixel circuit, a light emission control circuit, a first scanning circuit, a second scanning circuit, and a third scanning circuit. The first scanning circuit is electrically connected with a first scanning signal end of the pixel circuit and is used for generating a first scanning signal; the second scanning circuit is electrically connected with a second scanning signal end of the pixel circuit and used for generating a second scanning signal; the third scanning circuit is electrically connected with a third scanning signal end of the pixel circuit and used for generating a third scanning signal; the structure of the first scanning circuit and/or the structure of the third scanning circuit are the same as the structure of the light-emitting control circuit; the effective time of the first scanning signal and/or the third scanning signal is longer than that of the second scanning signal. Compared with the prior art, the utility model is beneficial to realizing the sufficient reset of the driving transistor and/or the light-emitting device in the pixel circuit.

Description

Display driving circuit and display panel

Technical Field

The embodiment of the utility model relates to the technical field of display, in particular to a display driving circuit and a display panel.

Background

Organic Light Emitting Diode (OLED) Display panels, especially Active-Matrix Organic Light Emitting Diode (AMOLED) panels, have advantages over Liquid Crystal Displays (LCDs) in terms of Display color saturation, power consumption, and foldability, and thus gradually occupy the market of Display panels.

In the prior art, a scanning driving circuit, a light emitting control circuit, and the like are required to be disposed in a frame region of a display panel to drive a pixel circuit in the display panel, and further drive a light emitting device to perform light emitting display. However, as the resolution and refresh rate of the display panel are increased, the display panel has the problem of display non-uniformity, which affects the quality improvement of the display panel.

SUMMERY OF THE UTILITY MODEL

Embodiments of the present invention provide a display driving circuit and a display panel, so as to achieve sufficient reset of a driving transistor and/or a light emitting device in a pixel circuit, and improve a display effect of the display panel.

In order to achieve the technical purpose, the embodiment of the utility model provides the following technical scheme:

a display driving circuit comprising:

a pixel circuit;

the light-emitting control circuit is electrically connected with the light-emitting control end of the pixel circuit; the light-emitting control circuit is used for outputting the light-emitting control signal;

a first scanning circuit electrically connected to a first scanning signal terminal of the pixel circuit; the first scanning circuit is used for generating the first scanning signal;

a second scanning circuit electrically connected to a second scanning signal terminal of the pixel circuit; the second scanning circuit is used for generating the second scanning signal;

a third scanning circuit electrically connected to a third scanning signal terminal of the pixel circuit; the third scanning circuit is used for generating the third scanning signal;

wherein a circuit structure of the first scanning circuit and/or the third scanning circuit is the same as a circuit structure of the light emission control circuit; the effective time of the first scanning signal and/or the third scanning signal is longer than that of the second scanning signal.

Optionally, the first scanning circuit is multiplexed into the third scanning circuit;

the number of the pixel circuits is multiple, and the pixel circuits are arranged in an array;

the first scanning circuit comprises at least two stages of first shift register circuits which are connected in cascade, and the first shift register circuit at one stage is electrically connected with the first scanning signal ends of the pixel circuits at the adjacent N rows and is electrically connected with the third scanning signal ends of the pixel circuits at the upper N rows; wherein N is a positive integer.

the first scanning circuit comprises at least two stages of first shift register circuits which are connected in cascade, and the first shift register circuit at one stage is electrically connected with the first scanning signal ends of the adjacent N rows of pixel circuits and is electrically connected with the third scanning signal ends of the N rows of pixel circuits; wherein N is a positive integer.

Optionally, the second scan circuit includes at least two stages of second shift register circuits connected in cascade, and the second shift register circuit of one stage is electrically connected to the second scan signal terminals of the pixel circuits of one row.

Optionally, N is equal to 1, and the number of the first shift register circuits is equal to the number of the second shift register circuits;

or, N is 2, and the number of the first shift register circuits is half of the number of the second shift register circuits.

Optionally, the first scan circuit includes at least two stages of first shift register circuits connected in cascade; the third scanning circuit comprises at least two stages of third shift register circuits which are connected in cascade; the light-emitting control circuit comprises at least two stages of fourth shift register circuits which are connected in cascade;

the first shift register circuit, the third shift register circuit, or the fourth shift register circuit includes:

the first input module is connected with a first clock signal end, a first input signal end and a first node, and is used for responding to the effective level of a first clock signal and transmitting a first input signal to the first node;

the first control module is connected with the first clock signal end, the first level signal end and the second node, and is used for responding to the effective level of the first clock signal and transmitting the first level signal to the second node;

the second control module is connected with the second node, a second clock signal end and a third node, responds to the effective level of the second node and responds to the effective level of a second clock signal and transmits the second clock signal to the third node;

a first node mutual control module, connected to the first node, the second node, the first clock signal terminal, the second clock signal terminal, and a second level signal terminal, the first node mutual control module being configured to transmit the first clock signal to the second node in response to an active level of the first node, and transmit a second level signal to the first node in response to an active level of the second node and a second clock signal;

the second node mutual control module is connected with the first node, the third node and the second level signal end, and the second node mutual control module is used for responding to the effective level of the first node and transmitting the second level signal to the third node;

the first output module is connected with the first node, the second clock signal end, the first level signal end and the first shift output end; the first output module is configured to couple the second clock signal to the first node, and transmit the first level signal to the first shift output terminal in response to an active level of the first node;

and the second output module is connected with the third node, the second level signal end and the first shift output end, and is used for responding to the effective level of the third node and transmitting the second level signal to the first shift output end.

Optionally, the second node is split into a first child node and a second child node; the first node mutual control module is used for responding to the effective level of the first node, transmitting the first clock signal to the first sub-node, and responding to the effective levels of the second sub-node and the second clock signal, and transmitting a second level signal to the first node; the first shift register circuit, the third shift register circuit, or the fourth shift register circuit further includes:

the third control module is connected with the first sub-node, the second sub-node, the first control signal end and the second control signal end; the third control module is used for responding to the active level of the first control signal and transmitting the signal of the first sub-node to the second sub-node; and transmitting the first control signal to the second child node in response to a second control signal;

preferably, the first node is divided into a third sub-node and a fourth sub-node, and the first shift register circuit, the third shift register circuit, or the fourth shift register circuit further includes:

the first voltage division protection module is connected with the third sub-node, the fourth sub-node and the first level signal end; the first voltage division protection module is used for responding to the first level signal and conducting the third sub-node and the fourth sub-node.

Optionally, the second scan circuit includes at least two stages of second shift register circuits;

the second shift register circuit includes:

the second input module is connected with the second input end, the third clock signal end and the fourth node; the second input module is used for responding to the effective level of a third clock signal and transmitting a second input signal to the fourth node;

the fourth control module is connected with the third clock signal end, the first level signal end and the fifth node; the fourth control module is used for responding to the effective level of the third clock signal and transmitting a first level signal to the fifth node;

the third node mutual control module is connected with the fourth node, the fifth node and the third clock signal end; the third node mutual control module is used for responding to the effective level of the fourth node and transmitting the third clock signal to the fifth node;

the fourth node mutual control module is connected with the fourth node, the fifth node, a fourth clock signal end and a second level signal end; the fourth node mutual control module is used for responding to the effective level of the fifth node and the effective level of a fourth clock signal and transmitting a second level signal to the fourth node;

the second voltage division protection module is connected with the fourth node, the sixth node and the first level signal end; the second voltage division protection module is used for responding to the first level signal and conducting the fourth node and the sixth node;

a third output module, connected to the sixth node, the fourth clock signal terminal and a second shift output terminal; the third output module is configured to transmit the fourth clock signal to the second shift output terminal in response to the active level of the sixth node;

a fourth output module, connected to the fifth node, the second level signal terminal and the second shift output terminal; the fourth output module is configured to transmit the second level signal to the second shift output terminal in response to the active level of the fifth node.

Optionally, the pixel circuit includes:

the first initialization module is connected with the first scanning signal end and the reference voltage signal end; the first initialization module is used for responding to the effective level of the first scanning signal end and initializing the grid of the driving transistor by adopting a reference voltage signal;

the data writing module is connected with the second scanning signal end, the data signal end, the first pole, the second pole and the grid of the driving transistor; the data writing module is used for responding to the second scanning signal of the second scanning signal end and sequentially transmitting the data signal to the first pole, the second pole and the grid of the driving transistor;

the storage module is connected with a first power signal end and the grid electrode of the driving transistor; the storage module is used for storing the grid potential of the driving transistor;

the second initialization module is connected with a third scanning signal end, the reference voltage signal end and the light-emitting device; the second initialization module is used for responding to the third scanning signal of the third scanning signal end and initializing the light-emitting device by adopting the reference voltage signal;

the light-emitting control module is connected with a light-emitting control signal end, the first power signal end, the first pole and the second pole of the driving transistor and the light-emitting device; the light-emitting control module is used for responding to the light-emitting control signal of the light-emitting control signal end and conducting a path between the first power signal end and the light-emitting device so as to enable the driving transistor to generate driving current.

Accordingly, the present invention also provides a display panel comprising: a display driver circuit as provided in any of the embodiments of the present invention.

In the display driving circuit provided in the embodiment of the present invention, a light emission control circuit, a first scanning circuit, a second scanning circuit, and a third scanning circuit are provided to supply a light emission control signal, a first scanning signal, a second scanning signal, and a third scanning signal to the pixel circuit, respectively, and a circuit structure in which the first scanning circuit and/or the third scanning circuit is provided is the same as a circuit structure of the light emission control circuit. The arrangement is that the first scanning signal and/or the third scanning signal are not limited to the pulse width of the clock signal, the effective time of the first scanning signal and/or the third scanning signal is prolonged, and the effective time of the first scanning signal and/or the third scanning signal is larger than that of the second scanning signal. Since the first scan signal controls the initialization of the driving transistor and the third scan signal controls the initialization of the light emitting device, the initialization time for the driving transistor and/or the light emitting device is increased. Therefore, compared with the prior art, the embodiment of the utility model can realize the sufficient reset of the driving transistor and/or the light-emitting device in the pixel circuit, improve the problems of display unevenness and the like caused by insufficient initialization time, and improve the display effect of the display panel.

Drawings

Fig. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a driving timing sequence of a pixel circuit according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a shift register circuit according to an embodiment of the present invention;

FIG. 4 is a schematic diagram illustrating a control timing sequence of a shift register circuit according to an embodiment of the present invention;

FIG. 5 is a diagram illustrating another shift register circuit according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a shift register circuit according to another embodiment of the present invention;

FIG. 7 is a schematic diagram illustrating a control timing of another shift register circuit according to an embodiment of the present invention;

fig. 8 is a schematic diagram illustrating a connection relationship between a second scan circuit and a pixel circuit according to an embodiment of the utility model;

fig. 9 is a schematic diagram illustrating a connection relationship between a first scan circuit and a pixel circuit according to an embodiment of the utility model;

fig. 10 is a schematic diagram illustrating a connection relationship between a first scan circuit and a pixel circuit according to another embodiment of the utility model;

fig. 11 is a schematic diagram illustrating a connection relationship between a light-emitting control circuit and a pixel circuit according to an embodiment of the present invention;

fig. 12 is a schematic diagram illustrating a connection relationship between a first scan circuit and a pixel circuit according to another embodiment of the present invention;

FIG. 13 is a schematic diagram of a driving timing sequence of another pixel circuit according to an embodiment of the present invention;

fig. 14 is a schematic diagram illustrating a connection relationship between another light-emission control circuit and a pixel circuit according to an embodiment of the present invention;

fig. 15 is a schematic diagram illustrating a connection relationship between a first scan circuit and a pixel circuit according to another embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the utility model and are not limiting of the utility model. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

As described in the background art, the conventional display panel has the problem of non-uniform display with the increase of the resolution and the refresh frequency of the screen, which affects the display quality of the display panel. The inventor researches and finds that the reason of the problem is as follows:

in the prior art, the pixel circuit usually adopts a driving method of lighting row by row, and the driving method is realized by outputting a shift signal by a scanning driving circuit and a light-emitting control circuit. As the resolution of the screen increases, the time to scan a line of pixels decreases; as the refresh frequency increases, the time for one frame display decreases, thereby allowing the time for scanning one row of pixels to be further reduced. In order to achieve high resolution and high refresh frequency, the time of the active level of the scan signal output by each scan drive circuit is reduced, that is, the pulse width is reduced. This causes a problem that the initialization time of the pixel circuit is reduced, and the initialization is insufficient, resulting in display unevenness.

Based on the above research, an embodiment of the present invention provides a display driving circuit. The display driving circuit is suitable for a self-luminous device display panel such as an Organic Light Emitting Diode (OLED) display panel. The display drive circuit includes: a pixel circuit, a light emission control circuit, a first scanning circuit, a second scanning circuit, and a third scanning circuit. The light-emitting control circuit, the first scanning circuit, the second scanning circuit and the third scanning circuit are all positioned in the non-display area; the pixel circuit is located in the display area. The specific structure of the pixel circuit can refer to any one of the pixel circuits in the prior art. Fig. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention. Referring to fig. 1, the pixel circuit 11 illustratively includes: a first initialization module 110, a second initialization module 120, a data writing module 130, a light emitting control module 140, and a storage module 150.

The first initialization module 110 is connected to the first scan signal terminal and the reference voltage signal terminal; the first initialization module 110 is configured to initialize the gate of the driving transistor DTFT with the reference voltage signal Vref in response to an active level of the first Scan signal Scan1 at the first Scan signal terminal. The data writing module 130 is connected to the second scan signal terminal, the data signal terminal, the first pole, the second pole and the gate of the driving transistor DTFT; the data writing module 130 is configured to sequentially transmit the data signal Vdata to the first pole, the second pole and the gate of the driving transistor DTFT in response to the second Scan signal Scan2 at the second Scan signal terminal. The storage module 150 is connected to the first power signal terminal VDD and the gate of the driving transistor DTFT; the storage module 150 is used for storing the gate potential of the driving transistor DTFT. The second initialization module 120 is connected to the third scan signal terminal, the reference voltage signal terminal, and the light emitting device OLED; the second initialization module 120 is configured to initialize the light emitting device OLED with the reference voltage signal Vref in response to the third Scan signal Scan3 at the third Scan signal terminal. The light emitting control module 140 is connected to the light emitting control signal terminal, the first power signal terminal, the first and second poles of the driving transistor DTFT, and the light emitting device OLED; the light emitting control module 140 is configured to respond to the light emitting control signal EM at the light emitting control signal terminal to turn on a path between the first power signal terminal and the light emitting device OLED, so that the driving transistor DTFT generates a driving current.

As can be seen, the pixel circuit 11 is configured to initialize the driving transistor DTFT in the pixel circuit 11 in response to the first Scan signal Scan1, write the data signal Vdata into the gate of the driving transistor DTFT in response to the second Scan signal Scan2, initialize the light emitting device OLED in response to the third Scan signal Scan3, and turn on a current path between the first power voltage terminal, the driving transistor DTFT, and the light emitting device OLED in response to the light emission control signal EM.

In the display driving circuit, the light emission control circuit is electrically connected to the light emission control terminal of the pixel circuit 11, and outputs a light emission control signal EM. The first Scan circuit is electrically connected to the first Scan signal terminal of the pixel circuit 11, and is configured to generate a first Scan signal Scan 1. The second Scan circuit is electrically connected to the second Scan signal terminal of the pixel circuit 11, and is configured to generate a second Scan signal Scan 2. The third scanning circuit is electrically connected to the third scanning signal terminal of the pixel circuit 11, and is configured to generate a third scanning signal Scan 3. The circuit structure of the first scanning circuit and/or the circuit structure of the third scanning circuit are/is the same as the circuit structure of the light-emitting control circuit; the effective time of the first Scan signal Scan1 and/or the third Scan signal Scan3 is longer than the effective time of the second Scan signal Scan 2.

Wherein, the effective time of the signal can be understood as: the time during which the transistor is on is under the influence of this signal. For example: for the P-type transistor, when the grid is switched into a low potential, the P-type transistor is conducted, and the low potential time of the control signal is effective time; for an N-type transistor, when the grid is connected with high potential, the N-type transistor is conducted, and then the high potential time of the control signal is effective time. The active time of a signal constitutes a pulse of the signal, the pulse width of which is determined by the corresponding circuit. In the prior art, the pulse width of the scanning circuit is determined by the pulse width of the clock signal, so that the pulse width of the clock signal is narrowed with the increase of the screen resolution and the refresh frequency, and accordingly, the pulse widths of the first scanning signal, the second scanning signal and the third scanning signal are all narrowed, and the effective time is short. However, the pulse width of the light emission control signal is not limited by the pulse width of the clock signal, and thus, the effective time of the light emission control signal is long.

In the display driving circuit provided in the embodiment of the present invention, a circuit structure of the first scanning circuit and/or the third scanning circuit is the same as a circuit structure of the light emission control circuit. By this arrangement, the first Scan signal Scan1 and/or the third Scan signal Scan3 are not limited to the pulse width of the clock signal, and the effective time of the first Scan signal Scan1 and/or the third Scan signal Scan3 is extended, so that the effective time of the first Scan signal Scan1 and/or the third Scan signal Scan3 is longer than the effective time of the second Scan signal Scan 2. Since the first Scan signal Scan1 controls the initialization of the driving transistor DTFT and the third Scan signal Scan3 controls the initialization of the light emitting device OLED, the initialization time of the driving transistor DTFT and/or the light emitting device OLED is increased. Therefore, compared with the prior art, the embodiment of the utility model can realize the sufficient reset of the driving transistor DTFT and/or the light emitting device OLED in the pixel circuit, improve the problems of display unevenness and the like caused by insufficient initialization time, and improve the display effect of the display panel.

Continuing to refer to fig. 1, taking the 7T1C pixel circuit structure as an example for explanation, the first initialization module 110 includes: a twentieth transistor M22; the gate of the twentieth transistor M22 is connected to the first Scan signal Scan1, the first pole is connected to the initialization voltage signal Vref, and the second pole is electrically connected to the gate of the driving transistor DTFT. The second initialization module 120 includes: a twenty-third transistor M23; the gate of the twenty-third transistor M23 is connected to the third Scan signal Scan3, the first pole is connected to the initialization voltage signal Vref, and the second pole is electrically connected to the anode of the light emitting device OLED. The data writing module 130 includes: a twenty-fourth transistor M24 and a twenty-fifth transistor M25; the gate of the twenty-fourth transistor M24 is connected to the second Scan signal Scan2, the first pole is connected to the data signal Vdata, and the second pole is electrically connected to the first pole of the driving transistor DTFT; the gate of the twenty-fifth transistor M25 is connected to the second Scan signal Scan2, the first pole is electrically connected to the second pole of the driving transistor DTFT, and the second pole is electrically connected to the gate of the driving transistor DTFT. The light emission control module 140 includes: a twenty-sixth transistor M26 and a twenty-seventh transistor M27; a gate of the twenty-sixth transistor M26 is connected to the emission control signal EM, a first pole is connected to the first power signal VDD, and a second pole is electrically connected to the first pole of the driving transistor DTFT; a gate of the twenty-seventh transistor M27 is connected to the emission control signal EM, and a first electrode thereof is electrically connected to a second electrode of the driving transistor DTFT, and the second electrode thereof is electrically connected to an anode of the light emitting device OLED. The cathode of the light emitting device OLED is connected to a second power signal VSS. The storage module 150 includes: a sixth capacitance C6; a first end of the sixth capacitor C6 is connected to the first power signal VDD, and a second end is electrically connected to the gate of the driving transistor DTFT.

Fig. 2 is a schematic diagram of a driving timing sequence of a pixel circuit according to an embodiment of the utility model. Referring to fig. 2, the driving process of the pixel circuit includes: an initialization phase T11, a data writing phase T12 and a light emitting phase T13. The initialization stage T11 specifically includes: a driving transistor initialization stage T111 and a light emitting device initialization stage T112. Exemplarily, with reference to fig. 1 and fig. 2, taking an example that each transistor is a P-type transistor and the gate is turned on at a low level, the driving process of the pixel circuit includes:

in the driving transistor initialization period T111, the first Scan signal Scan1 is at a low level, and the emission control signal EM is at a high level. The twentieth transistor M22 is turned on, and both the twenty-sixth transistor M26 and the twenty-seventh transistor M27 are turned off. The first initialization voltage signal Vref1 is transmitted to the gate of the driving transistor DTFT through the twenty-second transistor M22, and initializes the gate of the driving transistor DTFT, so that the gate of the driving transistor DTFT in a different operation state in the previous frame is forcibly reset. The low level of the initialization voltage signal Vref is maintained by the sixth capacitor C6, thereby ensuring that the driving transistor DTFT is turned on during the data writing period T12.

In the light emitting device initialization period T112, the third Scan signal Scan3 is at a low level, and the emission control signal EM is at a high level. The twenty-third transistor M23 is turned on, and both the twenty-sixth transistor M26 and the twenty-seventh transistor M27 are turned off. The initialization voltage signal Vref is transmitted to the anode of the light emitting device OLED through the twenty-third transistor M23 to initialize the anode of the light emitting device OLED.

In the data writing period T12, the second Scan signal Scan2 is at a low level, and the emission control signal EM is at a high level. The twenty-fourth transistor M24 and the twenty-fifth transistor M25 are both turned on, and the twenty-sixth transistor M26 and the twenty-seventh transistor M27 are both turned off. The data signal Vdata is transmitted to the gate of the driving transistor DTFT via the twenty-fourth transistor M24, the driving transistor DTFT, and the twenty-fifth transistor M25 until the gate voltage of the driving transistor DTFT reaches Vdata + Vth, and the driving transistor DTFT is turned off.

In the emission period T13, the emission control signal EM is at a low level, and the first Scan signal Scan1, the third Scan signal Scan3, and the second Scan signal Scan2 are all at a high level. The twenty-sixth transistor M26 and the twenty-seventh transistor M27 are both turned on, and the twenty-second transistor M22, the twenty-third transistor M23, the twenty-fourth transistor M24, and the twenty-fifth transistor M25 are all turned off. The first power signal VDD is applied to the first electrode of the driving transistor DTFT through the twenty-sixth transistor M26, so that the driving transistor DTFT generates a driving current, and the driving current flows into the anode of the light emitting device OLED through the twenty-seventh transistor M27, so as to drive the light emitting device OLED to emit light.

Then, in the light emitting period T13, the driving current Id generated by the driving transistor DTFT is: id ═ (W/2L) μ Cox (Vdata + Vth-VDD-Vth)²＝(W/2L)μCox(VDD-Vdata)²Where W is the channel width, L is the channel length, μ is the electron mobility, and Cox is the unit area channel capacitance. The channel width W, channel length L, electron mobility μ, and channel capacitance Cox per unit area can all be considered constant. Therefore, the pixel circuit eliminates the influence of the threshold voltage Vth on the drive current Id, and threshold compensation is realized.

It should be noted that the effective time of the first Scan signal Scan1 is before the effective time of the second Scan signal Scan 2; the effective times of the third Scan signal Scan3 and the second Scan signal Scan2 may overlap or not overlap as long as the effective times of the first Scan signal Scan1 and the third Scan signal Scan3 are within the non-effective time of the emission control signal EM.

On the basis of the above embodiments, optionally, the number of the pixel circuits 11 is multiple, and the multiple pixel circuits 11 are arranged in an array in the display area. The first scanning circuit comprises at least two stages of first shift register circuits which are connected in cascade; the second scanning circuit comprises at least two stages of second shift register circuits which are connected in cascade; the third scanning circuit comprises at least two stages of third shift register circuits which are connected in cascade; the light-emitting control circuit comprises at least two stages of fourth shift register circuits which are connected in cascade. Wherein, cascade connection means: the output end of the shift register circuit of the current stage is electrically connected with the input end of the shift register circuit of the next stage. Optionally, the first shift register circuit and the third shift register circuit have the same structure as the fourth shift register circuit.

Fig. 3 is a schematic structural diagram of a shift register circuit according to an embodiment of the present invention. The shift register circuit can be used as a first shift register circuit, a third shift register circuit or a fourth shift register circuit. Referring to fig. 3, the shift register circuit illustratively includes: a first input module 310, a first control module 320, a second control module 330, a first node interconnect module 340, a second node interconnect module 350, a first output module 360, and a second output module 370.

The first input module 310 is coupled to the first clock signal terminal, the first input signal terminal, and the first node N1, and the first input module 310 is configured to transmit the first input signal IN1 to the first node N1 IN response to the active level of the first clock signal CK 1. The first control module 320 is coupled to the first clock signal terminal, the first level signal terminal, and the second node N2, and the first control module 320 is configured to transmit the first level signal VGL to the second node N2 in response to the active level of the first clock signal CK 1. The second control module 330 connects the second node N2, the second clock signal terminal, and the third node N3, and the second control module 330 transmits the second clock signal CK2 to the third node N3 in response to the active level of the second node N2 and in response to the active level of the second clock signal CK 2. The first node mutual control module 340 is connected to the first node N1, the second node N2, the first clock signal terminal, the second clock signal terminal, and the second level signal terminal, and the first node mutual control module 340 is configured to transmit the first clock signal CK1 to the second node N2 in response to the active level of the first node N1, and transmit the second level signal VGH to the first node N1 in response to the active levels of the second node N2 and the second clock signal CK 2. The second node interoperability module 350 is connected to the first node N1, the third node N3 and the second level signal terminal, and the second node interoperability module 350 is configured to transmit the second level signal VGH to the third node N3 in response to the active level of the first node N1. The first output module 360 is connected to the first node N1, the second clock signal terminal, the first level signal terminal and the first shift output terminal; the first output module 360 is configured to couple the second clock signal CK2 to the first node N1, and transmit the first level signal VGH to the first shift output terminal in response to the active level of the first node N1. The second output module 370 is connected to the third node N3, the second level signal terminal and the first shift output terminal, and the second output module 370 is configured to transmit the second level signal VGH to the first shift output terminal in response to the active level of the third node N3.

For example, a shift register circuit structure of 10T3C is described as an example. The first input module 310 includes: a first transistor M1; the gate of the first transistor M1 is connected to the first clock signal CK1, the first pole is connected to the first input signal IN1, and the second pole is electrically connected to the first node N1. The first control module 320 includes: a third transistor M3; the gate of the third transistor M3 is connected to the first clock signal CK1, the first pole is connected to the first level signal VGL, and the second pole is electrically connected to the second node N2. The first node mutual control module 340 includes: a second transistor M2, a fourth transistor M4, and a fifth transistor M5; the gate of the second transistor M2 is electrically connected to the first node N1, the first pole is connected to the first clock signal CK1, and the second pole is electrically connected to the second node N2; a gate of the fourth transistor M4 is electrically connected to the second node N2, a first pole of the fourth transistor M4 is connected to the second level signal VGH, and a second pole of the fourth transistor M4 is electrically connected to the first pole of the fifth transistor M5; the gate of the fifth transistor M5 is connected to the second clock signal CK2, and the second pole is electrically connected to the first node N1.

The second control module 330 includes: a sixth transistor M6, a seventh transistor M7, and a second capacitor C2; a gate of the sixth transistor M6 is electrically connected to the second node N2 and the first end of the second capacitor C2, respectively, a first pole is connected to the second clock signal CK2, and a second pole is electrically connected to the second end of the second capacitor C2 and the first pole of the seventh transistor M7, respectively; the gate of the seventh transistor M7 is connected to the second clock signal CK2, and the second pole is electrically connected to the third node N3. The second node mutual control module 350 includes: an eighth transistor M8; the gate of the eighth transistor M8 is electrically connected to the first node N1, the first pole is connected to the second level signal VGH, and the second pole is electrically connected to the third node N3.

The first output module 360 includes: a tenth transistor M10 and a first capacitor C1; a gate of the tenth transistor M10 is electrically connected to the first node N1, a first pole is electrically connected to the first shift output terminal, and a second pole is connected to the first level signal VGL; the first end of the first capacitor C1 is connected to the second clock signal CK2, and the second end is electrically connected to the first node N1. The second output module 370 includes: a ninth transistor M9 and a third capacitor C3; a gate of the ninth transistor M9 is electrically connected to the third node N3, a first pole of the ninth transistor is connected to the second level signal VGH, and a second pole of the ninth transistor is electrically connected to the first shift output terminal; the first end of the third capacitor C3 is connected to the second level signal VGH, and the second end is electrically connected to the third node N3.

Fig. 4 is a schematic diagram of a control timing sequence of a shift register circuit according to an embodiment of the present invention. With reference to fig. 3 and 4, taking the case that each transistor is a P-type transistor and the gate is connected to the low level for conduction as an example, the driving process of the shift register circuit includes the following 6 stages:

IN the first phase T21, the first clock signal CK1 is at a low level, and the second clock signal CK2 and the first input signal IN1 are at a high level. The first transistor M1 and the third transistor M3 are turned on, and the fifth transistor M5 and the seventh transistor M7 are turned off; the high level of the first input signal IN1 is transmitted to the first node N1 through the first transistor M1, so that the second, eighth, and tenth transistors M2, M8, and M10 are turned off. The low level of the first level signal VGL is transmitted to the second node N2 through the third transistor M3, so that the fourth transistor M4 and the sixth transistor M6 are turned on. Due to the storage effect of the third capacitor C3, the third node N3 maintains the high level of the previous stage, so that the ninth transistor M9 is turned off. Therefore, in the first stage T21, the ninth transistor M9 and the tenth transistor M10 are both turned off, and the output signal OUT1 maintains the low level of the previous stage.

IN the second phase T22, the second clock signal CK2 is at a low level, and the first clock signal CK1 and the first input signal IN1 are at a high level. The fifth transistor M5 and the seventh transistor M7 are turned on, and the first transistor M1 and the third transistor M3 are turned off. Due to the storage function of the second capacitor C2, the second node N2 maintains the low level of the upper stage, so that the fourth transistor M4 and the sixth transistor M6 are turned on. The high level of the second level signal VGH is transmitted to the first node N1 through the fourth transistor M4 and the fifth transistor M5, so that the second transistor M2, the eighth transistor M8, and the tenth transistor M10 maintain an off-state. The low level of the second clock signal CK2 is transmitted to the third node N3 through the sixth transistor M6 and the seventh transistor M7 such that the ninth transistor M9 is turned on, the second level signal VGH is transmitted to the first shift output terminal through the ninth transistor M9, and the output signal OUT1 becomes the high level.

IN the third stage T23, the first clock signal CK1 is at a low level, and the second clock signal CK2 and the first input signal IN1 are at a high level. The first transistor M1 and the third transistor M3 are turned on, and the fifth transistor M5 and the seventh transistor M7 are turned off. Due to the storage effect of the third capacitor C3, the third node N3 maintains the low level of the previous stage, so that the ninth transistor M9 maintains the turn-on and the output signal OUT1 maintains the high level.

IN the fourth phase T24, the first clock signal CK1 is at a high level, and the second clock signal CK2 and the first input signal IN1 are at a low level. The first transistor M1 and the third transistor M3 are turned off, and the fifth transistor M5 and the seventh transistor M7 are turned on. Due to the storage effect of the second capacitor C2, the second node N2 maintains the low level of the previous stage, so that the fourth transistor M4 and the sixth transistor M6 are turned on. The high level of the second level signal VGH is transmitted to the first node N1 through the fourth transistor M4 and the fifth transistor M5, so that the second transistor M2, the eighth transistor M8, and the tenth transistor M10 maintain an off-state. The low level of the second clock signal CK2 is transmitted to the third node N3 through the sixth transistor M6 and the seventh transistor M7 such that the ninth transistor M9 is turned on, the high level of the second level signal VGH is transmitted to the first shift output terminal through the ninth transistor M9, and the output signal OUT1 maintains the high level.

IN the fifth phase T25, the second clock signal CK2 is at a high level, and the first clock signal CK1 and the first input signal IN1 are at a low level. The first transistor M1 and the third transistor M3 are turned on, and the fifth transistor M5 and the seventh transistor M7 are turned off. The low level of the first input signal IN1 is transmitted to the first node N1 through the first transistor M1, so that the second, eighth, and tenth transistors M2, M8, and M10 are turned on. The low level of the first clock signal CK1 is transmitted to the second node N2 through the second transistor M2, such that the fourth transistor M4 and the sixth transistor M6 are turned on, however, since the seventh transistor M7 is turned off, the low level of the second node N2 cannot be transmitted to the third node N3. The high level of the second level signal VGH is transmitted to the third node N3 through the eighth transistor M8, so that the ninth transistor M9 is turned off. The low level of the first level signal VGL is transmitted to the first shift output terminal through the tenth transistor M10, and the output signal OUT1 becomes a low level.

IN the sixth phase T26, the first clock signal CK1 is at a high level, and the second clock signal CK2 and the first input signal IN1 are at a low level. The fifth transistor M5 and the seventh transistor M7 are turned on. Due to the bootstrap effect of the first capacitor C1, as the second clock signal CK2 goes to a low level, the level of the first node N1 goes to a lower low level than that at the fifth stage 25, so that the second transistor M2, the eighth transistor M8 and the tenth transistor M10 maintain a turned-on state; the high level of the first clock signal CK1 is transmitted to the second node N2 through the second transistor M2, so that the second node N2 changes from the low level to the high level; the high level of the second level signal VGH is transmitted to the third node N3 through the eighth transistor M8 such that the ninth transistor M9 remains turned off. Compared to the previous stage, although the seventh transistor M7 is turned on in this stage, the third node N3 can remain high because the potential of the second node N2 has become high and does not pull down the potential of the third node N3. The low level of the first level signal VGL is transmitted to the first shift output terminal through the tenth transistor M10, and the output signal OUT1 maintains the low level.

The fifth stage T25 and the sixth stage T26 are repeated, and the shift register circuit continues to output a low level. As can be seen from the above analysis, the pulse widths of the high level and the low level of the output signal OUT1 of the shift register circuit are not limited by the pulse width of the clock signal, and the pulse width is wider than the pulse width of the clock signal.

Fig. 5 is a schematic structural diagram of another shift register circuit according to an embodiment of the present invention. Referring to fig. 5, on the basis of the foregoing embodiments, optionally, the second node is split into a first sub-node NS1 and a second sub-node NS 2; the first node mutual control module 340 is configured to transmit the first clock signal CK1 to the first sub-node NS1 in response to the active level of the first node N1, and transmit the second level signal VGH to the first node N1 in response to the active levels of the second sub-node NS2 and the second clock signal CK 2. The shift register circuit further includes: a third control module 380; the third control module 380 is connected to the first sub-node NS1, the second sub-node NS2, the first control signal terminal PC1 and the second control signal terminal PC 2; the third control module 380 is used for responding to the active level of the first control signal PC1 and transmitting the signal of the first sub-node NS1 to the second sub-node NS 2; and transmits the first control signal PC1 to the second sub-node NS2 in response to the second control signal PC 2.

Illustratively, the third control module 380 includes: an eleventh transistor M11 and a twelfth transistor M12; a gate of the eleventh transistor M11 is connected to the first control signal PC1, a first pole is electrically connected to the first sub-node NS1, and a second pole is electrically connected to the second sub-node NS 2; the gate of the twelfth transistor M12 is connected to the second control signal PC2, the first pole is connected to the first control signal PC1, and the second pole is electrically connected to the second sub-node NS 2. The first control signal PC1 is set to keep high when the shift register circuit needs to continuously output a valid signal, and the second control signal PC2 is set complementary to the first control signal PC1 to ensure stable output at the first shift output terminal. For example, the shift register circuit is a fourth shift register circuit in the light-emitting control circuit, and when the shift register circuit outputs a low level, the first control signal PC1 is set to a high level, and the second control signal PC2 is set to a low level; the arrangement is such that the low level of the second control signal PC2 controls the twelfth transistor M12 to be maintained in a turned-on state, the high level of the first control signal PC1 is transmitted to the second sub-node NS2 through the twelfth transistor M12, and the level of the second sub-node NS2 is stabilized at the high level; thereby ensuring that the fourth transistor M4 is turned off, preventing the high level of the second level signal VGH from being transmitted to the first node; the first node is kept at a low level, so that the first shift output terminal stably outputs a low level.

With continued reference to fig. 5, based on the foregoing embodiments, optionally, the first node is divided into a third sub-node NS3 and a fourth sub-node NS4, and the shift register circuit further includes: a first voltage division protection module 390; the first voltage division protection module 390 is connected to the third sub-node NS3, the fourth sub-node NS4 and the first level signal terminal; the first voltage division protection module 390 is configured to turn on the third sub-node NS3 and the fourth sub-node NS4 in response to the first level signal VGL.

Specifically, the first voltage division protection module 390 includes: a thirteenth transistor M13; the gate of the thirteenth transistor M13 is connected to the first level signal VGL, and has a first pole electrically connected to the third sub-node NS3 and a second pole electrically connected to the fourth sub-node NS 4. When the potential of the second clock signal CK2 changes from high level to low level, the potential of the fourth sub-node NS4 changes to low level due to the coupling effect of the first capacitor C1. The thirteenth transistor M13 is connected between the third sub-node NS3 and the fourth sub-node NS4, and prevents the low level of the fourth sub-node NS4 from being transmitted to the third sub-node NS 3. This is because, for the thirteenth transistor M13 provided as a P-type transistor, the high potential point is the source (i.e., the left side is the source) and the low potential point is the drain (i.e., the right side is the drain), and when the thirteenth transistor M13 is turned on, it is required that the gate voltage of the thirteenth transistor M13 be smaller than the source voltage and Vgs-_M13＜Vth-_M13. Thus, when the source voltage is lowered, Vgs-_M13Raised, does not satisfy Vgs-_M13＜Vth-_M13Under this condition, the thirteenth transistor M13 is turned off, so that the potential of the third sub-node NS3 is not too low.When the potential of the third sub-node NS3 is too low, the high level of the first input signal IN1 cannot be completely written into the third sub-node NS 3. Therefore, the present embodiment prevents the potential of the third sub-node NS3 from being too low by providing the thirteenth transistor M13, which is beneficial to the stability of the shift register circuit.

Fig. 6 is a schematic structural diagram of another shift register circuit according to an embodiment of the present invention. The shift register circuit can be used as a second shift register circuit so as to output a second scanning signal for controlling the writing of the data signal. Referring to fig. 6, the shift register circuit illustratively includes: a second input module 410, a fourth control module 420, a third node mutual control module 430, a fourth node mutual control module 440, a second voltage division protection module 450, a third output module 460, and a fourth output module 470.

The second input module 410 is connected to the second input terminal, the third clock signal terminal and the fourth node N4; the second input module 410 is used for transmitting the second input signal IN2 to the fourth node N4 IN response to the active level of the third clock signal CK 3. The fourth control module 420 is connected to the third clock signal terminal, the first level signal terminal and the fifth node N5, and the fourth control module 420 is configured to transmit the first level signal VGL to the fifth node N5 in response to the active level of the third clock signal CK 3. The third node mutual control module 430 is connected to the fourth node N4, the fifth node N5 and the third clock signal terminal, and the third node mutual control module 430 is configured to transmit the third clock signal CK3 to the fifth node N5 in response to the active level of the fourth node N4. The fourth node mutual control module 440 is connected to the fourth node N4, the fifth node N5, the fourth clock signal terminal, and the second level signal terminal, and the fourth node mutual control module 440 is configured to transmit the second level signal VGH to the fourth node N4 in response to the active level of the fifth node N5 and the active level of the fourth clock signal CK 4. The second voltage division protection module 450 is connected to the fourth node N4, the sixth node N6 and the first level signal terminal; the second voltage division protection module 450 is configured to turn on the fourth node N4 and the sixth node N6 in response to the first level signal VGL. The third output module 460 is connected to the sixth node N6, the fourth clock signal terminal and the second shift output terminal; the third output module 460 is used for transmitting the fourth clock signal CK4 to the second shift output terminal in response to the active level of the sixth node N6. The fourth output module 470 is connected to the fifth node N5, the second level signal terminal, and the second shift output terminal, and the fourth output module 470 is configured to transmit the second level signal VGH to the second shift output terminal in response to the active level of the fifth node N5.

Illustratively, the shift register circuit structure of 8T2C is explained. The second input module 410 includes: a fourteenth transistor M14; the gate of the fourteenth transistor M14 is connected to the third clock signal CK3, the first pole is connected to the second input signal IN2, and the second pole is electrically connected to the fourth node N4. The fourth control module 420 includes: a fifteenth transistor M15; the gate of the fifteenth transistor M15 is connected to the third clock signal CK3, the first pole is connected to the first level signal VGL, and the second pole is electrically connected to the fifth node N5. The third node mutual control module 430 includes: a sixteenth transistor M16; the gate of the sixteenth transistor M16 is electrically connected to the fifth node N5, the first pole is electrically connected to the fourth node N4, and the second pole is connected to the third clock signal CK 3. The fourth node mutual control module 440 includes: a seventeenth transistor M17 and an eighteenth transistor M18; a gate of the seventeenth transistor M17 is electrically connected to the fifth node N5, a first pole of the seventeenth transistor M17 is connected to the second level signal VGH, and a second pole of the seventeenth transistor M17 is electrically connected to the first pole of the eighteenth transistor M18; the gate of the eighteenth transistor M18 is connected to the fourth clock signal CK4, and the second pole is electrically connected to the fourth node N4. The second partial pressure protection module 450 includes: a nineteenth transistor M19; the gate of the nineteenth transistor M19 is connected to the first level signal VGL, and has a first pole electrically connected to the fourth node N4 and a second pole electrically connected to the sixth node N6. The third output module 460 includes: a twenty-first transistor M21 and a fifth capacitor C5; the gate of the twenty-first transistor M21 is electrically connected to the sixth node N6 and the second end of the fifth capacitor C5, respectively, the first pole of the twenty-first transistor M21 is electrically connected to the first end of the fifth capacitor C5 and the second shift output terminal, respectively, and the second pole of the twenty-first transistor M21 is connected to the fourth clock signal CK 4. The fourth output module 470 includes: a twentieth transistor M20 and a fourth capacitor C4; the gates of the twentieth transistor M20 are electrically connected to the fifth node N5 and the second end of the fourth capacitor C4, respectively, the first pole of the twentieth transistor M20 and the first end of the fourth capacitor C4 are both connected to the second level signal VGH, and the second pole of the twentieth transistor M20 is electrically connected to the second shift output terminal.

Fig. 7 is a schematic diagram of a control timing diagram of another shift register circuit according to an embodiment of the present invention. With reference to fig. 6 and 7, taking the example that each transistor is a P-type transistor and the gate is connected to the low level conduction, the driving process of the shift register circuit includes 4 stages:

IN the first phase T31, the third clock signal CK3 and the second input signal IN2 are low, and the fourth clock signal CK4 is high. The fourteenth transistor M14 and the fifteenth transistor M15 are turned on, and the eighteenth transistor M18 is turned off; the nineteenth transistor M19 is turned on by the first level signal VGL; the low level of the second input signal IN2 is transmitted to the fourth node N4 through the fourteenth transistor M14, so that the sixteenth transistor M16 is turned on; the low level of the third clock signal CK3 is transmitted to the fifth node N5 through the sixteenth transistor M16, and the low level of the first level signal VGL is transmitted to the fifth node N5 through the fifteenth transistor M15, so that the twentieth transistor M20 is turned on; the high level of the second level signal VGH is transmitted to the second shift output terminal through the twentieth transistor M20; the low level of the fourth node N4 is transmitted to the sixth node N6 through the nineteenth transistor M19, so that the twenty-first transistor M21 is turned on; the high level of the fourth clock signal CK4 is transmitted to the second shift output terminal through the twenty-first transistor M21. Therefore, in the first stage T31, the twentieth transistor M20 and the twenty-first transistor M21 are both turned on, and the output signal OUT2 is at a high level.

IN the second stage T32, the fourth clock signal CK4 is low, and the third clock signal CK3 and the second input signal IN2 are both high. The fourteenth transistor M14 and the fifteenth transistor M15 are turned off, and the eighteenth transistor M18 is turned on; the nineteenth transistor M19 is turned on by the first level signal VGL. Due to the storage function of the fifth capacitor C5, the sixth node N6 maintains the low level of the previous stage, so that the twenty-first transistor M21 is turned on; the low level of the sixth node N6 is transmitted to the fourth node N4 through the nineteenth transistor M19, so that the sixteenth transistor M16 is turned on. The high level of the third clock signal CK3 is transmitted to the fifth node N5 through the sixteenth transistor M16, so that the twentieth transistor M20 is turned off. The low level of the fourth clock signal CK4 is output through the twenty-first transistor M21, and the output signal OUT2 is low. The output signal OUT2 changes from high level to low level, and due to the coupling effect of the fifth capacitor C5, the potential of the sixth node N6 further decreases, so that the output signal OUT2 is stably output at low level.

IN the third stage T33, the third clock signal CK3 is at a low level, and the fourth clock signal CK4 and the second input signal IN2 are both at a high level. The fourteenth transistor M14 and the fifteenth transistor M15 are turned on, and the eighteenth transistor M18 is turned off; the nineteenth transistor M19 is turned on by the first level signal VGL. The high level of the second input signal IN2 is transmitted to the fourth node N4 through the fourteenth transistor M14, so that the sixteenth transistor M16 is turned off; the high level of the fourth node N4 is transmitted to the sixth node N6 through the nineteenth transistor M19, so that the twenty-first transistor M21 is turned off. The low level of the first level signal VGL is transmitted to the fifth node N5 through the fifteenth transistor M15, so that the twentieth transistor M20 is turned on; the high level of the second level signal VGH is output through the twentieth transistor M20, and the output signal OUT2 is high level.

IN the fourth stage T34, the fourth clock signal CK4 is low, and the third clock signal CK3 and the second input signal IN2 are both high. The fourteenth transistor M14 and the fifteenth transistor M15 are turned off, and the eighteenth transistor M18 is turned on; the nineteenth transistor M19 is turned on by the first level signal VGL. Due to the storage function of the fourth capacitor C4, the fifth node N5 maintains the low level of the previous stage, so that the seventeenth transistor M17 and the twentieth transistor M20 are turned on. The high level of the second level signal VGH is transmitted to the sixth node N6 through the seventeenth transistor M17, the eighteenth transistor M18, and the nineteenth transistor M19, so that the twenty-first transistor M21 is turned off. The high level of the second level signal VGH is output through the twentieth transistor M20, and the output signal OUT2 maintains the high level.

The third stage T33 and the fourth stage T34 are repeated, and the output signal OUT2 maintains a high level. As can be seen from the above analysis, the low-level pulse width of the output signal OUT2 of the shift register circuit is equal to the pulse width of the clock signal, and is limited by the pulse width.

The above embodiments exemplarily show the pixel circuit and the shift register circuit structure and the operation process. The following describes several connection relationships among the pixel circuit, the scanning circuit, and the light emission control circuit, but the present invention is not limited thereto. In order to clearly show the connection relationship of the first scanning circuit, the second scanning circuit, the third scanning circuit, and the light emission control circuit to the pixel circuit, in the following drawings, each drawing shows only one kind of connection relationship of the circuit to the pixel circuit.

Fig. 8 is a schematic diagram illustrating a connection relationship between a second scan circuit and a pixel circuit according to an embodiment of the utility model. Referring to fig. 8, in an embodiment, the second scan circuits 23 are optionally disposed on two sides of the display panel respectively, and a dual-edge driving method is adopted. Each stage of the second shift register circuit 230 is electrically connected to the second scan signal terminal of the pixel circuit 11 of the corresponding row.

Specifically, as shown in fig. 8, the output terminal of the m-1 th stage second shift register circuit 230 is electrically connected to the m-1 th row of pixel circuits 11; the output end of the mth stage second shift register circuit 230 is electrically connected to the mth row pixel circuit 11; the output terminal of the (m + 1) th stage second shift register circuit 230 is electrically connected to the (m + 1) th row pixel circuit 11. Wherein m is more than or equal to 2 and is a positive integer. Each stage of the second shift register circuits 230 shifts and outputs, i.e., each row of the second Scan signal Scan2 shifts and outputs.

Fig. 9 is a schematic diagram illustrating a connection relationship between a first scan circuit and a pixel circuit according to an embodiment of the utility model. Referring to fig. 9, in an embodiment, optionally, the first scan circuit 22 is multiplexed into a third scan circuit, so that only the first scan circuit 22 is disposed in the display driving circuit, and the third scan circuit is not required to be disposed, so as to reduce the area of the non-display area of the display panel occupied by the whole scan circuit, which is beneficial to implementing a narrow bezel of the display panel.

With continued reference to fig. 9, in one embodiment, optionally, the waveform of the first Scan signal Scan1 received by the m +1 th row of pixel circuits 11 is the same as the waveform of the third Scan signal Scan3 received by the m +1 th row of pixel circuits 11. The third Scan signal Scan3 received by the pixel circuits 11 in the same row is shifted backward by one row period from the active time of the first Scan signal Scan 1.

Fig. 10 is a schematic diagram illustrating a connection relationship between a first scan circuit and a pixel circuit according to another embodiment of the utility model. Referring to fig. 10, in one embodiment, the first shift register circuit 220 of one stage optionally provides the first Scan signal Scan1 and the third Scan signal Scan3 to the pixel circuits 11 of the same row. That is, the first Scan signal Scan1 and the third Scan signal Scan3 of the pixel circuits 11 in the same row overlap, and the driving transistor initialization period T111 starts at the same time as the light emitting device initialization period T112.

Fig. 11 is a schematic diagram illustrating a connection relationship between a light-emitting control circuit and a pixel circuit according to an embodiment of the present invention. Referring to fig. 11, in an embodiment, the light emitting control circuits 21 are optionally respectively disposed on two sides of the display panel, and a dual-side driving method is adopted. Each stage of the fourth shift register circuits 210 is electrically connected to the light-emitting control signal end of the pixel circuit 11 in the corresponding row.

Specifically, as shown in fig. 11, the output terminal of the m-1 th stage fourth shift register circuit 210 is electrically connected to the m-1 th row of pixel circuits 11; the output end of the mth stage fourth shift register circuit 210 is electrically connected to the mth row pixel circuit 11; the output terminal of the (m + 1) th stage fourth shift register circuit 210 is electrically connected to the (m + 1) th row pixel circuit 11. Each stage of the fourth shift register circuit 210 shifts and outputs, that is, each row of the emission control signal EM.

It should be noted that, although the above embodiments have been described by way of example, the first scanning circuit 22 outputs the first scanning signal Scan1 corresponding to one row of the pixel circuits 11 at one stage, the first scanning circuit 22 outputs the third scanning signal Scan3 corresponding to one row of the pixel circuits 11 at one stage, the second scanning circuit 23 outputs the second scanning signal Scan2 corresponding to one row of the pixel circuits 11 at one stage, and the emission control circuit 21 outputs the emission control signal EM corresponding to one row of the pixel circuits 11 at one stage, the present invention is not limited thereto, and in other embodiments, the first scanning circuit 22 may drive at least two rows of the pixel circuits 11 at one stage, or the emission control circuit 21 may drive at least two rows of the pixel circuits 11 at one stage.

Fig. 12 is a schematic diagram illustrating a connection relationship between a first scan circuit and a pixel circuit according to another embodiment of the present invention. Referring to fig. 12, in one embodiment, the number of the first shift register circuits 220 is optionally half of the number of the second shift register circuits. Illustratively, the output terminal of the i +1 th stage first shift register circuit 220 is electrically connected to the first scan signal terminal of the 2i +2 th row of pixel circuits 11, the first scan signal terminal of the 2i +1 th row of pixel circuits 11, the third scan signal terminal of the 2i th row of pixel circuits 11, and the third scan signal terminal of the 2i-1 th row of pixel circuits 11, respectively. Wherein i is more than or equal to 2, and i is a positive integer. By such arrangement, the number of the first shift register circuits 220 is effectively reduced, the area of the first scan circuit 22 occupying the frame of the display panel can be effectively reduced, the occupation ratio of the non-display area is reduced, and the realization of a narrow frame is facilitated.

Illustratively, in the connection relationship of the first scan circuit 22 and the pixel circuit 11 as shown in fig. 12, the driving timing of the pixel circuit 11 can be seen in fig. 13. Unlike the driving timing of the pixel circuits 11 shown in fig. 2, in fig. 13, the third Scan signal Scan3 received by the pixel circuits 11 in the same row is shifted backward by two row periods from the effective time of the first Scan signal Scan 1. However, in the pixel circuit 11, the initialization of the driving transistor DTFT is completed before the data writing stage, and the initialization of the light emitting device OLED is completed before the light emitting stage, so that the first shift register circuit 220 is provided in the embodiment of the present invention to initialize the pixel circuits 11 in two rows at the same time, and the data writing to the pixel circuits 11 is not adversely affected. The embodiment of the utility model reduces the frame of the display panel on the basis of ensuring that the display effect of the display panel is not changed.

Fig. 14 is a schematic diagram illustrating a connection relationship between another light-emission control circuit and a pixel circuit according to an embodiment of the present invention. Referring to fig. 14, in an embodiment, optionally, the fourth shift register circuits 210 in each stage of the light emission control circuit 21 are respectively electrically connected to the light emission control signal terminals of the two adjacent rows of pixel circuits 11. Then, the timing of the emission control signal EM every two rows is the same. Specifically, the output end of the (i + 1) th stage fourth shift register circuit 210 is electrically connected to the light emission control signal end of the 2i +2 th row pixel circuit 11 and the light emission control signal end of the 2i +1 th row pixel circuit 11, respectively. With such an arrangement, the number of the fourth shift register circuits 210 can be effectively reduced, which is beneficial to the realization of the narrow frame of the display panel. And, in one frame, the light emitting period of the pixel circuits 11 is long, and the first-stage fourth shift register circuit 210 is arranged to control the light emitting of the two rows of pixel circuits 11 at the same time, so that the display time of one clock period of the previous row of pixel circuits 11 is only reduced, the display time is only one thousandth of the whole light emitting period, even shorter, and the negative influence on the light emitting of the pixel circuits 11 can be ignored. The embodiment of the utility model can reduce the frame of the display panel on the basis of ensuring that the display effect of the display panel is almost unchanged.

In the display driving circuit, referring to fig. 12 and 14, the first scanning circuit 22 and the light emission control circuit 21 both adopt a scheme of driving two rows of pixel circuits 11 by outputting in one stage, and the sum of the number of the first shift register circuits 220 and the number of the fourth shift register circuits 210 is equal to the number of the second shift register circuits 230. Compared with the prior art in which all the Scan signals are provided by the Scan driving circuit, one-stage output of the Scan driving circuit drives one row of pixel circuits, and one-stage output of the light-emitting control circuit drives one row of pixel circuits, the present embodiment can effectively prolong the effective time of the first Scan signal Scan1 and the third Scan signal Scan3 without increasing the number of shift register circuits, and is beneficial to the realization of a narrow frame.

Fig. 15 is a schematic diagram illustrating a connection relationship between a first scan circuit and a pixel circuit according to another embodiment of the present invention. Referring to fig. 15, in one embodiment, the first shift register circuit 220 of one stage optionally supplies the first Scan signal Scan1 and the third Scan signal Scan3 to the pixel circuits 11 of two rows. Illustratively, the output terminal of the i +1 th stage first shift register circuit 220 is electrically connected to the first scan signal terminal of the 2i +2 th row of pixel circuits 11, the third scan signal terminal of the 2i +2 th row of pixel circuits 11, the first scan signal terminal of the 2i +1 th row of pixel circuits 11, and the third scan signal terminal of the 2i +1 th row of pixel circuits 11, respectively. The first Scan signal Scan1 of the pixel circuits 11 in the same row overlaps the third Scan signal Scan 3.

It should be noted that the number of the first shift register circuits shown in the above embodiments is not limited to the present invention, and in other embodiments, the number of the first shift register circuits may be 1/N of the number of the second shift register circuits, where N > 2; and the first shift register circuit at one stage is electrically connected with the first scanning signal end and the third scanning signal end of the pixel circuit at the adjacent N rows.

In the above embodiments, the manner in which the light emission control circuit, the first scanning circuit, the second scanning circuit, and the third scanning circuit are driven in the double-edge driving mode is shown by way of example, and the present invention is not limited thereto. In other embodiments, a single-side drive may be further provided, which may be specifically selected according to actual requirements.

The embodiment of the utility model also provides a display panel, and the display panel can be a self-luminous device display panel such as an organic light emitting diode display panel. The display panel includes: the display driving circuit provided by any embodiment of the utility model has corresponding beneficial effects.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the utility model. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display driving circuit, comprising:

a pixel circuit;

the light-emitting control circuit is electrically connected with the light-emitting control end of the pixel circuit; the light-emitting control circuit is used for outputting a light-emitting control signal;

a first scanning circuit electrically connected to a first scanning signal terminal of the pixel circuit; the first scanning circuit is used for generating a first scanning signal;

a second scanning circuit electrically connected to a second scanning signal terminal of the pixel circuit; the second scanning circuit is used for generating a second scanning signal;

a third scanning circuit electrically connected to a third scanning signal terminal of the pixel circuit; the third scanning circuit is used for generating a third scanning signal;

2. The display driver circuit according to claim 1, wherein the first scan circuit is multiplexed into the third scan circuit;

3. The display driver circuit according to claim 1, wherein the first scan circuit is multiplexed into the third scan circuit;

4. The display driver circuit according to claim 2 or 3, wherein the second scan circuit includes at least two stages of second shift register circuits connected in cascade, one stage of the second shift register circuits being electrically connected to the second scan signal terminals of one row of the pixel circuits.

5. The display driving circuit according to claim 4, wherein N is 1, and the number of the first shift register circuits is equal to the number of the second shift register circuits;

6. The display driver circuit according to claim 1, wherein the first scan circuit comprises at least two stages of first shift register circuits connected in cascade; the third scanning circuit comprises at least two stages of third shift register circuits which are connected in cascade; the light-emitting control circuit comprises at least two stages of fourth shift register circuits which are connected in cascade;

7. The display driver circuit according to claim 6, wherein the second node is split into a first sub-node and a second sub-node; the first node mutual control module is used for responding to the effective level of the first node, transmitting the first clock signal to the first sub-node, and responding to the effective levels of the second sub-node and the second clock signal, and transmitting a second level signal to the first node; the first shift register circuit, the third shift register circuit, or the fourth shift register circuit further includes:

the third control module is connected with the first sub-node, the second sub-node, the first control signal end and the second control signal end; the third control module is used for responding to the active level of the first control signal and transmitting the signal of the first sub-node to the second sub-node; and transmitting the first control signal to the second child node in response to a second control signal.

8. The display driver circuit according to claim 6, wherein the first node is divided into a third sub-node and a fourth sub-node, and the first shift register circuit, the third shift register circuit, or the fourth shift register circuit further comprises:

9. The display driver circuit according to claim 1, wherein the second scan circuit comprises at least two stages of second shift register circuits;

the second shift register circuit includes:

10. The display driver circuit according to claim 1, wherein the pixel circuit comprises:

a drive transistor;

11. A display panel, comprising: a display driver circuit as claimed in any one of claims 1 to 10.