CN215420202U

CN215420202U - Operational amplifier circuit

Info

Publication number: CN215420202U
Application number: CN202122064845.5U
Authority: CN
Inventors: 陆熙良; 曾奕恩
Original assignee: Beijing Beidou Huada Technology Co ltd
Current assignee: Beijing Beidou Huada Technology Co ltd
Priority date: 2021-08-30
Filing date: 2021-08-30
Publication date: 2022-01-04
Anticipated expiration: 2031-08-30

Abstract

The utility model discloses an operational amplifier circuit, which comprises two differential signal input ends, two differential signal output ends, a bias circuit, a fully differential operational amplifier main circuit and a common mode feedback circuit, wherein the fully differential operational amplifier main circuit comprises a first differential amplification circuit as a first stage and a forward amplification compensation and push-pull driving circuit as a second stage, and the forward amplification compensation and push-pull driving circuit comprises two groups of switchable switch tube arrays participating in forward amplification compensation and push-pull driving. The operational amplifier circuit can realize larger bandwidth and lower power consumption.

Description

Operational amplifier circuit

[ technical field ]

The present invention relates to integrated circuits, and more particularly, to an operational amplifier circuit.

[ background art ]

The operational amplifier is an electronic integrated circuit containing a multistage amplifying circuit, and the utility model with the application number of CN201310123747.1 discloses an operational amplifier circuit with adjustable bandwidth, which comprises a bias circuit, a fully differential operational amplifier main circuit and a common mode feedback circuit, wherein: the bias circuit is used for providing stable bias current irrelevant to temperature and process for the main circuit of the fully differential operational amplifier and the common-mode feedback circuit; the fully differential operational amplifier main circuit is a two-stage amplified full-swing output structure and is used for providing gain and required bandwidth under the action of bias current and outputting a common-mode level to a common-mode feedback circuit; and the common-mode feedback circuit is used for stabilizing the common-mode level output by the main circuit of the fully differential operational amplifier to a constant voltage. The operational amplifier circuit with the adjustable bandwidth is required to obtain larger bandwidth. It is necessary to trade by increasing power consumption.

[ summary of the utility model ]

The utility model aims to provide an operational amplifier circuit with larger bandwidth and lower power consumption.

In order to solve the technical problems, the technical scheme adopted by the utility model is that the operational amplifier circuit comprises two differential signal input ends, two differential signal output ends, a bias circuit, a fully differential operational amplifier main circuit and a common mode feedback circuit, wherein the fully differential operational amplifier main circuit comprises a first differential amplification circuit serving as a first stage and a forward amplification compensation and push-pull driving circuit serving as a second stage, and the forward amplification compensation and push-pull driving circuit comprises two groups of switchable switching tube arrays participating in forward amplification compensation and push-pull driving.

In the operational amplifier circuit, the first differential amplification circuit comprises a first NMOS transistor, a second NMOS transistor, a third PMOS transistor and a fourth PMOS transistor, and the forward amplification compensation and push-pull driving circuit comprises a fifth PMOS transistor, a sixth PMOS transistor and the two switchable switch transistor arrays; the drain electrode of the first NMOS tube is connected with the positive electrode of the power supply through a third PMOS tube, and the drain electrode of the second NMOS tube is connected with the positive electrode of the power supply through a fourth PMOS tube; the source electrode of the first NMOS tube is connected with the source electrode of the second NMOS tube and then connected with the biasing circuit, the grid electrode of the first NMOS tube is connected with the first differential signal input end, and the grid electrode of the second NMOS tube is connected with the second differential signal input end; each group of switchable switch tube arrays comprises a plurality of switchable NMOS tubes connected in parallel, the grid electrode of the fifth PMOS tube is connected with the drain electrode of the first NMOS tube, and the grid electrode of the sixth PMOS tube is connected with the drain electrode of the second NMOS tube; and the source electrode of the fifth PMOS tube and the source electrode of the sixth PMOS tube are connected with the positive electrode of the power supply, and the drain electrode of the fifth PMOS tube is connected with the first differential signal output end. The NMOS tubes of the first group of switchable switching tube arrays are grounded; the drain electrode of the sixth PMOS tube is connected with the second differential signal output end and is grounded through the NMOS tube of the second group of switchable switching tube arrays; the grid electrodes of the NMOS tubes connected in parallel with the first group of switchable switch tube arrays are connected with the grid electrode of the second NMOS tube through a first alternating current coupling capacitor, and the grid electrodes of the NMOS tubes connected in parallel with the second group of switchable switch tube arrays are connected with the grid electrode of the first NMOS tube through a second alternating current coupling capacitor.

In the operational amplifier circuit, the common mode feedback circuit includes the second differential amplifying circuit and the common mode sampling circuit; the second differential amplification circuit comprises a fifth NMOS tube, a sixth NMOS tube, two groups of switchable parallel PMOS tubes and a common mode sampling circuit, wherein the drain electrode of the fifth NMOS tube is connected with the anode of the power supply through the first group of switchable parallel PMOS tubes, and the drain electrode of the sixth NMOS tube is connected with the anode of the power supply through the second group of switchable parallel PMOS tubes; the source electrode of the fifth NMOS tube is connected with the source electrode of the sixth NMOS tube and then connected with the bias circuit, the grid electrode of the fifth NMOS tube is connected with the output end of the common mode sampling circuit, and the grid electrode of the sixth NMOS tube is connected with the reference voltage signal input end; the common mode sampling circuit comprises two sampling resistors which are connected in series, and the connection point of the two sampling resistors is the output end of the common mode sampling circuit; two ends of the common mode sampling circuit are respectively connected with the first differential signal output end and the second differential signal output end.

In the operational amplifier circuit, the common mode feedback circuit includes a common mode feedback compensation circuit, and the common mode feedback compensation circuit includes a first RC delay compensation circuit and a second RC delay compensation circuit; the source electrode of the first group of the switchable parallel PMOS tubes and the source electrode of the second group of the switchable parallel PMOS tubes are connected with the positive electrode of the power supply, the drain electrode and the grid electrode of the first group of the switchable parallel PMOS tubes are connected with the drain electrode of the fifth NMOS tube, and the drain electrode and the grid electrode of the second group of the switchable parallel PMOS tubes are connected with the drain electrode of the sixth NMOS tube; the grid electrodes of the first group of switchable parallel PMOS tubes are connected with the positive electrode of the power supply through a second RC lag compensation circuit and are connected with the grid electrode of a third PMOS tube and the grid electrode of a fourth PMOS tube; the grid electrode of the fifth NMOS tube is grounded through the first RC hysteresis compensation circuit.

In the operational amplifier circuit, the forward amplification compensation and push-pull driving circuit comprises two miller compensation capacitors, the first miller compensation capacitor is connected between the gate and the drain of the fifth PMOS transistor, and the second miller compensation capacitor is connected between the gate and the drain of the sixth PMOS transistor.

In the operational amplifier circuit, the bias circuit comprises a reference current source, a first NMOS transistor of the bias circuit, a second NMOS transistor of the bias circuit, and a switchable switch transistor array of the bias circuit, wherein the switchable switch transistor array of the bias circuit comprises a plurality of switchable parallel-connected NMOS transistors; the input end of the reference current source is connected with the positive electrode of the power supply, the output end of the reference current source is connected with the drain electrode of the first NMOS tube of the bias circuit, the drain electrode of the first NMOS tube of the bias circuit is connected with the grid electrode, and the source electrode of the first NMOS tube of the bias circuit is grounded; the grid electrode of the second NMOS tube of the bias circuit is connected with the grid electrode of the first NMOS tube of the bias circuit, the source electrode of the second NMOS tube of the bias circuit is grounded, and the drain electrode of the second NMOS tube of the bias circuit is connected with the source electrode of the first NMOS tube of the first differential amplification circuit and the source electrode of the second NMOS tube; the grid electrode of the NMOS tube of the switchable switch tube array of the bias circuit is connected with the grid electrode of the first NMOS tube of the bias circuit, the source electrode of the NMOS tube of the switchable switch tube array of the bias circuit is grounded, and the drain electrode of the switchable switch tube array of the bias circuit is connected with the source electrode of the fifth NMOS tube of the second differential amplification circuit and the source electrode of the sixth NMOS tube.

In the operational amplifier circuit, the grid electrodes of the NMOS tubes connected in parallel with the first group of switchable switching tube arrays are connected with the grid electrode of the first NMOS tube of the biasing circuit through the first biasing resistor, and the grid electrodes of the NMOS tubes connected in parallel with the second group of switchable switching tube arrays are connected with the grid electrode of the first NMOS tube of the biasing circuit through the second biasing resistor; the drain electrodes of the NMOS tubes connected in parallel with the first group of switchable switching tube arrays are connected with the drain electrode of the fifth PMOS tube, and the source electrodes of the NMOS tubes connected in parallel with the first group of switchable switching tube arrays are grounded; the drain electrodes of the NMOS tubes connected in parallel in the second group of switchable switch tube arrays are connected with the drain electrode of the sixth PMOS tube, and the source electrodes of the NMOS tubes connected in parallel in the second group of switchable switch tube arrays are grounded.

The operational amplifier circuit of the utility model can realize larger bandwidth and lower power consumption,

[ description of the drawings ]

The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.

Fig. 1 is a schematic block diagram of an operational amplifier circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of an operational amplifier circuit according to an embodiment of the present invention.

FIG. 3 is a diagram of an NMOS switch array according to an embodiment of the utility model.

FIG. 4 is a schematic diagram of a PMOS switch array according to an embodiment of the utility model.

[ detailed description of the utility model ]

The structure and principle of the operational amplifier circuit of the embodiment of the utility model are shown in fig. 1 to 4, and the operational amplifier circuit comprises a power supply positive electrode input end VDD and a differential signal input end V_IP、V_INTwo differential signal output ends V_0P、V_0NThe circuit comprises a bias circuit, a fully differential operational amplifier main circuit and a common mode feedback circuit.

The bias circuit is used for providing stable bias current independent of temperature and process for the main circuit of the fully differential operational amplifier and the common-mode feedback circuit. The main circuit of the fully differential operational amplifier adopts a two-stage amplified full-swing output structure, is used for providing gain and required bandwidth under the action of bias current, and outputs a common mode level to a common mode feedback circuit. The common-mode feedback circuit is used for stabilizing the common-mode level output by the main circuit of the fully differential operational amplifier to a constant voltage.

As shown in fig. 1, the fully differential operational amplifier main circuit includes a first differential amplification circuit as a first stage and a forward amplification compensation and push-pull drive circuit as a second stage.

As shown in fig. 2, the first differential amplifier circuit includes a first NMOS transistor M_N1A second NMOS transistor M_N2And the third PMOS transistor M_P3And the fourth PMOS transistor M_P4The forward amplification compensation and push-pull driving circuit comprises a fifth PMOS tube M_P5Sixth PMOS transistor M_P6The device comprises two groups of switchable switch tube arrays and two Miller compensation capacitors. First NMOS transistor M_N1The drain electrode of the transistor passes through a third PMOS tube M_P3The drain electrode of the second NMOS transistor MN2 is connected with the positive electrode VDD of the power supply through a fourth PMOS transistor MP 4. First NMOS transistor M_N1Source electrode of and the second NMOS transistor M_N2The source electrode of the NMOS transistor is connected with a back bias circuit, and a first NMOS transistor M_N1The grid of the first differential signal input end V is connected with the first differential signal input end V_IPSecond NMOS transistor M_N2The grid of the first differential signal input terminal is connected with the second differential signal input terminal V_IN. Each group of switchable switch tube array M_N3And M_N4Each comprising a plurality of switchable, parallel-connected NMOS transistors.

Fifth PMOS transistor M_P5The grid electrode of the NMOS transistor is connected with the first NMOS transistor M_N1The sixth PMOS transistor M_P6Grid of the NMOS transistor is connected with a second NMOS transistor M_N2Of the substrate. Fifth PMOS transistor M_P5Source electrode and sixth PMOS transistor M_P6The source electrodes of the first and second electrode are respectively connected with a power supply anode VDD and a first Miller compensation capacitor C_M1Is connected to a fifth PMOS transistor M_P5Between the gate and the drain of the first transistor, a second Miller compensation capacitor C_M2Is connected to a sixth PMOS tube M_P6Between the gate and the drain. Fifth PMOS transistor M_P5Drain electrode of the first differential signal output end V is connected with the first differential signal output end V_OP. And through the first group of switchable switching tube arrays M_N3The NMOS tube of (1) is grounded. Sixth PMOS transistor M_P6Drain electrode of the first differential signal output terminal is connected with the second differential signal output terminal V_ONAnd through a second group of switchable switching tube arrays M_N4The NMOS tube of (1) is grounded. I.e. a first set of switchable switching tube arrays M_N3The drain electrode of the NMOS tube connected in parallel is connected with the fifth PMOS tube M_P5The first group of switchable switching tube arrays M_N3The source electrode of the NMOS tube connected in parallel is grounded. Second group of switchable switch tube array M_N4The drain electrode of the NMOS tube connected in parallel is connected with a sixth PMOS tube M_P6A second group of switchable switching tube arrays M_N4The source electrode of the NMOS tube connected in parallel is grounded. First group of switchable switch tube array M_N3The grid of the NMOS tubes connected in parallel passes through a first alternating current coupling capacitor C_F1Is connected with a second NMOS tube M_N2A second group of switchable switching tube arrays M_N4The grid of the NMOS tubes connected in parallel passes through a second alternating current coupling capacitor C_F2Is connected with a first NMOS tube M_N1A gate electrode of (1).

The common-mode feedback circuit comprises a second differential amplifying circuit and a common-mode sampling circuit. The second differential amplifying circuit comprises a fifth NMOS tube M_N5And a sixth NMOS transistor M_N6Two groups of switchable parallel PMOS (P-channel metal oxide semiconductor) tubes M_P1、M_P2And a common mode sampling circuit, a fifth NMOS transistor M_N5The drain electrode of the PMOS transistor is connected with a first group of switchable parallel PMOS tubes M_P1The drain electrode of the sixth NMOS transistor MN6 is connected with the anode VDD of the power supply through a second group of switchable parallel PMOS transistors M_P2Connected with the positive electrode VDD of the power supply. The source of the fifth NMOS transistor MN5 and the sixth NMOS transistor M_N6The source electrode of the NMOS transistor is connected with a back-end bias circuit, and a fifth NMOS transistor M_N5The grid of the NMOS transistor is connected with the output end of the common-mode sampling circuit, and a sixth NMOS transistor M_N6Is connected with a reference voltage signal V_REFTo the input terminal of (1).

The common mode sampling circuit comprises two sampling resistors R connected in series_S1And R_S2Two sampling resistors R_S1And R_S2The connection point of the common mode sampling circuit and the fifth NMOS tube M_N5Is connected to the gate of (a). Two ends of the common mode sampling circuit are respectively connected with a first differential signal output end V_OPAnd a second differential signal output terminal V_ON。

The common mode feedback circuit also comprises a common mode feedback compensation circuit which comprises a resistor R_C1And a capacitor C_C1A first RC hysteresis compensation circuit composed of series connection and a resistor R_C2And a capacitor C_C2A second RC lag compensation circuit formed in series. First group of switchable parallel PMOS (P-channel Metal oxide semiconductor) tubes M_P1And a second group of switchable parallel PMOS transistors M_P2The source electrodes of the PMOS transistors are respectively connected with the positive electrode VDD of the power supply, and the first group of switchable parallel PMOS tubes M_P1The drain electrode and the grid electrode of the transistor are connected and then connected with a fifth NMOS transistor M_N5A second group of switchable parallel PMOS transistors M_P2The drain electrode and the grid electrode are connected and then connected with a sixth NMOS tube M_N6Of the substrate. First group of switchable parallel PMOS (P-channel Metal oxide semiconductor) tubes M_P1The grid of the PMOS transistor is connected with a positive electrode VDD of a power supply through a second RC lag compensation circuit and is connected with a third PMOS transistor M_P3Grid and fourth PMOS tube M_P4A gate electrode of (1). Fifth NMOS transistor M_N5Gate pass ofThe first RC hysteresis compensation circuit is connected to ground.

The bias circuit comprises a reference current source I_BThe first NMOS transistor M of the bias circuit_CM0And a second NMOS transistor M of the bias circuit_CM2And a bias circuit switchable switching tube array M_CM1Reference current source I_BThe first NMOS transistor M of the bias circuit_CM0And a second NMOS transistor M of the bias circuit_CM2And a bias circuit switchable switching tube array M_CM1The current mirror structure is used for providing bias current for the main circuit of the fully differential operational amplifier and the common mode feedback circuit.

Switchable switch tube array M of bias circuit_CM1Comprises a plurality of switchable NMOS tubes connected in parallel. Reference current source I_BThe input end of the biasing circuit is connected with a power supply anode VDD, and the output end of the biasing circuit is connected with a first NMOS tube M of the biasing circuit_CM0The drain electrode of the bias circuit is the first NMOS tube M_CM0The drain electrode of the bias circuit is connected with the grid electrode, and a first NMOS tube M of the bias circuit_CM0Is grounded. Second NMOS transistor M of bias circuit_CM2The grid electrode of the transistor is connected with a first NMOS transistor M of a bias circuit_CM0The grid of the bias circuit and the second NMOS tube M_CM2The source electrode of the first differential amplifier circuit is grounded, and the drain electrode of the first differential amplifier circuit is connected with the first NMOS tube M_N1Source electrode of and second NMOS transistor M_N2Of the substrate. Switchable switch tube array M of bias circuit_CM1The grid of the middle NMOS tube is connected with a first NMOS tube M of the bias circuit_CM0Grid electrode and bias circuit switchable switch tube array M_CM1The source electrode of the middle NMOS tube is grounded, and the drain electrode of the middle NMOS tube is connected with a fifth NMOS tube M of the second differential amplification circuit_N5Source electrode of (1) and sixth NMOS transistor M_N6Of the substrate.

First group of switchable switch tube array M_N3The grid of the NMOS tubes connected in parallel is also connected with a first bias resistor R_F1A first NMOS transistor M of a bias circuit is connected_CM0A second group of switchable switching tube arrays M_N4The grid of the NMOS tubes connected in parallel is also connected with a second bias resistor R_F2A first NMOS transistor M of a bias circuit is connected_CM0A gate electrode of (1).

The first differential amplifying circuit of the operational amplifier circuit fully differential operational amplifier main circuit comprises an NMOS tube M_N1,M_N2,M_CM2And PMOS transistor M_P3,M_P4. Differential input signal V_IP,V_INIs connected to M_N1,M_N2Through M of the gate electrode_N1,M_N2At M, is amplified_N1,M_N2Is of_ON1And V_OP1And obtaining a first-stage amplified signal of differential input. PMOS tube M_P3,M_P4Is an active load that provides high impedance so that the first stage of the operational amplifier has high gain.

The forward amplification compensation and push-pull driving circuit as the second stage comprises an NMOS tube M_N3,M_N4PMOS transistor M_P5,M_P6And a compensation capacitor C_M1,C_M2. NMOS tube M_N3,M_N4The circuit has two functions of (1) forward amplification compensation and (2) push-pull type driving stage. Will M_N3,M_N4Through C_F1And C_F2Connected into positive feedback, i.e. M_N3Gate through C of_F1AC coupling to V_INDrain connected to V_OPA forward amplification compensation path is provided. M_N4Gate through C of_F2AC coupling to V_IPDrain connected to V_ONAnd another forward amplification compensation path is provided to achieve the effect of broadband compensation. Furthermore M_N3,M_N4The static currents of the two NMOS tubes are determined by a bias circuit, but the dynamic currents of the two NMOS tubes are changed along with the magnitude of an input signal, and the larger the input signal is, the larger the dynamic current is, and the characteristics of a push-pull type driving stage are achieved. PMOS tube M_P5,M_P6Is connected with the grid input at V_ON1,V_OP1Drain connected to V_OPAnd V_ONFor the second stage of amplification, and in addition, a PMOS transistor M_P5,M_P6The dynamic current of (2) also changes with the magnitude of the input signal, and has the characteristics of a push-pull driving stage. Because M is_N3And M_N4Has two functions simultaneously, and C is added to increase the design flexibility of frequency compensation_M1And C_M2And finely adjusting the phase margin to ensure that various process angles can meet the requirement of the phase margin.

The common mode feedback circuit comprises an NMOS tube M_N5,M_N6,M_CM1And PMOS transistor M_P1,M_P2-a differential amplifier structure formed of a resistor R_S1,R_S2Detecting the output common mode level, and stabilizing the output common mode level to a stabilized voltage V by negative feedback_REF. V in common mode feedback loop_cmfbAnd V_fBoth nodes are added with RC series compensation (R)_C1,C_C1And R_C2,C_C2) The purpose of zero point compensation is achieved, and the phase margin of the common mode feedback loop is assisted.

The operational amplifier circuit of the embodiment of the utility model can adjust M according to different bandwidths_N3And M_N4The number of the middle MOS transistors connected in parallel, the structure of the NMOS switching array according to the embodiment of the present invention is shown in fig. 3, and the structure of the PMOS switching array is shown in fig. 4, which can increase or decrease the current consumption under different bandwidth requirements. The power consumption of the common mode feedback loop is adjusted according to different bandwidths, so that the bias circuit can switch the switch tube array M_CM1The architecture of fig. 4 may also be used. And in order to reduce systematic offset (systematic offset), two groups of switchable parallel PMOS (P-channel metal oxide semiconductor) tubes M of the common mode feedback circuit_P1、M_P2The architecture of fig. 4 may be employed to switch the number of parallel MOS transistors. The number of the parallel MOS tubes can be adjusted before leaving a factory and also adjusted in use.

The dynamic current of the push-pull output stage adopted by the above embodiment of the present invention varies with the magnitude of the input signal, and the larger the input signal is, the larger the dynamic current is, and vice versa, so that the smaller static current can be used to bias the push-pull output stage. And the push-pull output stage is analyzed by small signals, and the equivalent transconductance is g under the same static current_mn+g_mpTransconductance g equivalent to the output stage of a conventional operational amplifier_mn(or is g)_mp) Compared with the prior art, the amplification can be 1.5-2 times.

The frequency compensation method of the above embodiment of the present invention is considered as a broadband target, and the method considers selecting forward-forward (feed-forward) amplification compensation or cross-feedback miller compensation as in the background art.

The above embodiments of the present invention combine the forward amplification compensation and the push-pull driving stage in the switchable switch tube array, since no additional switch tube is requiredThe current is compensated by forward amplification, so that the power can be saved. In addition, the advantage of forward amplification compensation is that the transconductance of the forward amplification stage is properly designed, so that the traditional Miller compensation capacitor can be removed, and the bandwidth can be easily deduced. And then, the push-pull type driving stage is matched for use, so that a larger load can be driven by using lower static current, and the purpose of saving electricity is achieved. In the above embodiment of the present invention, two RC series circuits (R) are used to process the phase margin of the common mode feedback loop after the bandwidth of the main circuit is pushed out_C1,C_C1And R_C2,C_C2) The compensation achieves the effect of zero point compensation, and the power consumption of the common mode feedback loop can be saved.

Claims

1. An operational amplifier circuit comprises two differential signal input ends, two differential signal output ends, a bias circuit, a fully differential operational amplifier main circuit and a common mode feedback circuit, and is characterized in that the fully differential operational amplifier main circuit comprises a first differential amplification circuit serving as a first stage and a forward amplification compensation and push-pull driving circuit serving as a second stage, and the forward amplification compensation and push-pull driving circuit comprises two groups of switchable switch tube arrays participating in forward amplification compensation and push-pull driving.

2. The operational amplifier circuit as claimed in claim 1, wherein the first differential amplifier circuit comprises a first NMOS transistor, a second NMOS transistor, a third PMOS transistor, and a fourth PMOS transistor, and the forward amplification compensation and push-pull driving circuit comprises a fifth PMOS transistor, a sixth PMOS transistor, and the two switchable switch transistor arrays; the drain electrode of the first NMOS tube is connected with the positive electrode of the power supply through a third PMOS tube, and the drain electrode of the second NMOS tube is connected with the positive electrode of the power supply through a fourth PMOS tube; the source electrode of the first NMOS tube is connected with the source electrode of the second NMOS tube and then connected with the biasing circuit, the grid electrode of the first NMOS tube is connected with the first differential signal input end, and the grid electrode of the second NMOS tube is connected with the second differential signal input end; each group of switchable switch tube arrays comprises a plurality of switchable NMOS tubes connected in parallel, the grid electrode of the fifth PMOS tube is connected with the drain electrode of the first NMOS tube, and the grid electrode of the sixth PMOS tube is connected with the drain electrode of the second NMOS tube; the source electrode of the fifth PMOS tube and the source electrode of the sixth PMOS tube are connected with the positive electrode of the power supply, and the drain electrode of the fifth PMOS tube is connected with the first differential signal output end and is grounded through the NMOS tubes of the first group of switchable switching tube arrays; the drain electrode of the sixth PMOS tube is connected with the second differential signal output end and is grounded through the NMOS tube of the second group of switchable switching tube arrays; the grid electrodes of the NMOS tubes connected in parallel with the first group of switchable switch tube arrays are connected with the grid electrode of the second NMOS tube through a first alternating current coupling capacitor, and the grid electrodes of the NMOS tubes connected in parallel with the second group of switchable switch tube arrays are connected with the grid electrode of the first NMOS tube through a second alternating current coupling capacitor.

3. The operational amplifier circuit of claim 2, wherein the common mode feedback circuit comprises a second differential amplifying circuit and a common mode sampling circuit; the second differential amplification circuit comprises a fifth NMOS tube, a sixth NMOS tube, two groups of switchable parallel PMOS tubes and a common mode sampling circuit, wherein the drain electrode of the fifth NMOS tube is connected with the anode of the power supply through the first group of switchable parallel PMOS tubes, and the drain electrode of the sixth NMOS tube is connected with the anode of the power supply through the second group of switchable parallel PMOS tubes; the source electrode of the fifth NMOS tube is connected with the source electrode of the sixth NMOS tube and then connected with the bias circuit, the grid electrode of the fifth NMOS tube is connected with the output end of the common mode sampling circuit, and the grid electrode of the sixth NMOS tube is connected with the reference voltage signal input end; the common mode sampling circuit comprises two sampling resistors which are connected in series, and the connection point of the two sampling resistors is the output end of the common mode sampling circuit; two ends of the common mode sampling circuit are respectively connected with the first differential signal output end and the second differential signal output end.

4. The operational amplifier circuit of claim 3, wherein the common mode feedback circuit comprises a common mode feedback compensation circuit comprising a first RC hysteretic compensation circuit and a second RC hysteretic compensation circuit; the source electrode of the first group of the switchable parallel PMOS tubes and the source electrode of the second group of the switchable parallel PMOS tubes are connected with the positive electrode of the power supply, the drain electrode and the grid electrode of the first group of the switchable parallel PMOS tubes are connected with the drain electrode of the fifth NMOS tube, and the drain electrode and the grid electrode of the second group of the switchable parallel PMOS tubes are connected with the drain electrode of the sixth NMOS tube; the grid electrodes of the first group of switchable parallel PMOS tubes are connected with the positive electrode of the power supply through a second RC lag compensation circuit and are connected with the grid electrode of a third PMOS tube and the grid electrode of a fourth PMOS tube; the grid electrode of the fifth NMOS tube is grounded through the first RC hysteresis compensation circuit.

5. The operational amplifier circuit as claimed in claim 2, wherein the forward amplification compensation and push-pull driving circuit comprises two miller compensation capacitors, the first miller compensation capacitor is connected between the gate and the drain of the fifth PMOS transistor, and the second miller compensation capacitor is connected between the gate and the drain of the sixth PMOS transistor.

6. The operational amplifier circuit as claimed in claim 3, wherein the bias circuit comprises a reference current source, a first NMOS transistor of the bias circuit, a second NMOS transistor of the bias circuit, and a switchable switch transistor array of the bias circuit, the switchable switch transistor array of the bias circuit comprises a plurality of switchable parallel NMOS transistors; the input end of the reference current source is connected with the positive electrode of the power supply, the output end of the reference current source is connected with the drain electrode of the first NMOS tube of the bias circuit, the drain electrode of the first NMOS tube of the bias circuit is connected with the grid electrode, and the source electrode of the first NMOS tube of the bias circuit is grounded; the grid electrode of the second NMOS tube of the bias circuit is connected with the grid electrode of the first NMOS tube of the bias circuit, the source electrode of the second NMOS tube of the bias circuit is grounded, and the drain electrode of the second NMOS tube of the bias circuit is connected with the source electrode of the first NMOS tube of the first differential amplification circuit and the source electrode of the second NMOS tube; the grid electrode of the NMOS tube of the switchable switch tube array of the bias circuit is connected with the grid electrode of the first NMOS tube of the bias circuit, the source electrode of the NMOS tube of the switchable switch tube array of the bias circuit is grounded, and the drain electrode of the switchable switch tube array of the bias circuit is connected with the source electrode of the fifth NMOS tube of the second differential amplification circuit and the source electrode of the sixth NMOS tube.

7. The operational amplifier circuit as claimed in claim 6, wherein the gates of the NMOS transistors connected in parallel to the first group of switchable switching transistor arrays are connected to the gate of the first NMOS transistor of the bias circuit through a first bias resistor, and the gates of the NMOS transistors connected in parallel to the second group of switchable switching transistor arrays are connected to the gate of the first NMOS transistor of the bias circuit through a second bias resistor; the drain electrodes of the NMOS tubes connected in parallel with the first group of switchable switching tube arrays are connected with the drain electrode of the fifth PMOS tube, and the source electrodes of the NMOS tubes connected in parallel with the first group of switchable switching tube arrays are grounded; the drain electrodes of the NMOS tubes connected in parallel in the second group of switchable switch tube arrays are connected with the drain electrode of the sixth PMOS tube, and the source electrodes of the NMOS tubes connected in parallel in the second group of switchable switch tube arrays are grounded.