CN215120606U - Low-loss ideal diode - Google Patents

Abstract

The utility model discloses a low-loss ideal diode, the diode is including control IC, charge pump electric capacity C1, enhancement mode MOSFET, whole rectifier system device is few, do benefit to very much and reduce the volume of whole application scheme, control IC's power pin VIN connects enhancement mode MOSFET's source end, and as the positive pole of rectifier, control IC's charge pump pin CPO passes through electric capacity C1 and connects MOSFET's source end, control IC's drive pin Gate connects enhancement mode MOSFET's Gate end, control IC's pin OUT connects MOSFET's drain terminal, for the negative pole and the output of rectifier, this low-loss ideal diode is peripheral succinct, the controllable low-loss diode of consumption, reduce the rectifier consumption, simplify the cloth, reduce whole scheme volume, accord with the high energy efficiency, high power density's development trend, need not heat abstractor in the application.

Description

Low-loss ideal diode

Technical Field

The utility model relates to a semiconductor technology, concretely relates to low-loss ideal diode.

Background

The schottky diode is often used to replace a common diode (forward voltage drop is about 0.7V) as a rectifier in a high current circuit due to its forward voltage reduction (usually about 0.3V), which can greatly reduce the power loss caused by the diode, for example, the schottky diode can save (0.7V-0.3V) × 3A =1.2W power consumption under the current condition of 3A, and the voltage obtained from the cathode of the diode will be closer to the input voltage of the anode of the diode.

However, with the improvement of energy efficiency requirements, when a large current is applied, a large power consumption still occurs on the schottky diode serving as a rectifier, so that the energy efficiency cannot meet the requirements, and meanwhile, the schottky diode generates heat very seriously during operation and needs heat dissipation treatment, so that the volume of the whole scheme needs to be increased, and the scheme cost also increases.

SUMMERY OF THE UTILITY MODEL

In order to further reduce the power consumption of the rectifier and ensure that the load power can follow the input power, the utility model provides a low-loss ideal diode which can reduce the power consumption brought by the rectifier in an extremely simple and controllable way, and because the reduction of the power consumption of the rectifier, the application does not need a heat dissipation device, and the volume of the whole scheme is reduced, the utility model discloses a low-loss ideal diode which comprises a control IC, a charge pump capacitor C1 and an enhanced MOSFET, the whole rectification system has few devices, which is very beneficial to reducing the volume of the whole application scheme, a power pin VIN of the control IC is connected with the source end of the enhanced MOSFET and is used as the anode of the rectifier, a charge pump pin CPO of the control IC is connected with the source end of the MOSFET through a capacitor C1, a drive pin Gate end of the enhanced MOSFET is connected with the drive pin of the control IC, an OUT pin of the control IC is connected with the drain end of the MOSFET, the cathode and the output of the rectifier.

As an improvement of the utility model, the control IC comprises a comparator CMP1, a comparator CMP2, an operational amplifier AMP, a level conversion module, an LDO/BIAS/UVLO module and a charge pump module, the LDO/BIAS/UVLO module is used as a reference, a BIAS, an enable and a chip internal low voltage power VCC inside the control chip IC, the power VIN generates a charge pump current source through the charge pump module, an external capacitor C1 is charged through a pin CPO, the charge pump is used for pumping the CPO pin voltage to the VIN power voltage, an NMOS tube N1 and a PMOS tube P1 are connected with the CPO pin of the charge pump module through a capacitor C1, a voltage stabilizing tube DZ exists between the CPO pin and the VIN for the CPO voltage, the CPO voltage is ensured to be higher than the VIN voltage by the breakdown voltage of the voltage stabilizing tube DZ, two input ends of the comparator CMP1, the comparator CMP2 and the operational amplifier AMP are respectively connected with the cathode voltage and the VOUT voltage, an output end of a comparator CMP2 of a comparator CMP1 is connected with a level conversion module, the comparators CMP1 and CMP2 are used for comparing anode and cathode voltages of a rectifier, namely VIN and OUT voltages, an operational amplifier AMP is used for maintaining the voltage difference between VIN and OUT and ensuring that the cathode voltage VOUT is kept at a level lower than 25mV of the anode voltage VIN, the level conversion module is connected with an NMOS tube N1 and a PMOS tube P1 and is used for converting high and low levels VCC and GND output by the two comparators into high and low levels CPO and VIN so as to drive subsequent drive tubes, the NMOS tube N1 and the PMOS tube P1 are drive tubes of an IC, a source end of the PMOS tube P1 is connected with the CPO voltage, and a source end of the NMOS tube N1 is connected with the VIN voltage.

As an improvement of the present invention, the difference between the cathode voltage VOUT and the anode voltage VIN is equal to 25 mV.

As an improvement of the utility model, through comparator CMP1, cathode voltage VOUT when the rectifier is less than anode voltage VIN-75 mV's value, then control pull-up PMOS pipe P1 is to the quick pull-up of Gate pin, through comparator CMP2, cathode voltage VOUT-25mV when the rectifier is higher than anode voltage VIN, then control pull-down NMOS pipe N1 is to the quick pull-down of Gate pin, NMOS pipe N1 and PMOS pipe P1 are IC's drive tube, act as the quick pull-up or pull-down to drive pin Gate.

As an improvement of the utility model, the voltage value of the voltage stabilizing tube DZ is 5~ 7V.

As an improvement of the utility model, the chargedump module includes five annular inverters, and five annular inverters connect the condenser, connect a set of series diode through the condenser, and series diode connects PMOS pipe P2 and PMOS pipe P3, and PMOS pipe P2 and PMOS pipe P3 connect NMOS pipe N2 and NMOS pipe P3.

As an improvement of the utility model, the bias current Ib obtains fixed current source all the way at the CPO pin after NMOS, PMOS current mirror.

The utility model has the advantages that: the utility model provides a peripheral succinct, the controllable low-loss diode of consumption reduces the rectifier consumption, simplifies the fabric, reduces whole scheme volume, accords with high energy efficiency, high power density's development trend, need not heat abstractor on using.

Drawings

Fig. 1 is a schematic diagram of the low-and-medium-loss diode circuit structure of the present invention.

Fig. 2 is a schematic diagram of the effect of the three parts of the central control driving tube P1, the N1 and the operational amplifier AMP on the Gate pin.

Fig. 3 is a schematic diagram of an internal structure of a charge pump module according to the present invention.

Detailed Description

The present invention will be further elucidated with reference to the accompanying figures 1-3 and embodiments, it being understood that the following embodiments are only intended to illustrate the present invention and are not intended to limit the scope of the present invention.

Example (b): the diode comprises a control IC, a charge pump capacitor C1 and an enhancement type MOSFET, the whole rectification system has few devices, the size of the whole application scheme is favorably reduced, a power supply pin VIN of the control IC is connected with a source end of the enhancement type MOSFET and is used as an anode of the rectifier, a charge pump pin CPO of the control IC is connected with the source end of the MOSFET through a capacitor C1, a driving pin Gate of the control IC is connected with a Gate end of the enhancement type MOSFET, and a pin OUT of the control IC is connected with a drain end of the MOSFET and is used as a cathode and output of the rectifier.

The control IC comprises a comparator CMP1, a comparator CMP2, an operational amplifier AMP, a level conversion module, an LDO/BIAS/UVLO module and a charge pump module, wherein the LDO/BIAS/UVLO module is used as a reference, BIAS, enable and chip internal low-voltage power VCC inside the control chip IC, a power VIN generates a path of charge pump current source through the charge pump module, an external capacitor C1 is charged through a pin CPO, the charge pump module is used for pumping a CPO pin voltage to a VIN power voltage, an NMOS tube N1 and a PMOS tube P1, a CPO pin of the charge pump module is connected with a capacitor C1, a voltage regulator tube DZ is arranged between the CPO pin and the VIN for ensuring that the CPO voltage is higher than the voltage of the voltage DZ, two input ends of the comparator CMP VIN 1, the comparator CMP2 and the operational amplifier AMP are respectively connected with an anode voltage and a cathode voltage, and a comparator CMP2 of the comparator of the VOUT 1 is connected with a voltage regulator module, the comparators CMP1 and CMP2 are used for comparing anode and cathode voltages of the rectifier, namely VIN and OUT voltages, the operational amplifier AMP is used for maintaining the voltage difference between VIN and OUT and ensuring that the cathode voltage VOUT is kept at a level lower than 25mV of the anode voltage VIN, the level conversion module is connected with the NMOS tube N1 and the PMOS tube P1 and is used for converting high and low levels VCC and GND output by the two comparators into high and low levels CPO and VIN so as to drive subsequent driving tubes, the NMOS tube N1 and the PMOS tube P1 are driving tubes of an IC, the source end of the PMOS tube P1 is connected with the CPO voltage, the source end of the NMOS tube N1 is connected with the VIN voltage, and the difference between the cathode voltage VOUT and the anode voltage VIN is equal to 25 mV. When the cathode voltage VOUT of the rectifier is lower than the anode voltage VIN-75mV through a comparator CMP1, a pull-up PMOS tube P1 is controlled to pull up the Gate pin quickly, when the cathode voltage VOUT-25mV of the rectifier is higher than the anode voltage VIN through a comparator CMP2, a pull-down NMOS tube N1 is controlled to pull down the Gate pin quickly, an NMOS tube N1 and a PMOS tube P1 are IC driving tubes and are used for pulling up or pulling down the driving pin Gate quickly, the voltage value of a voltage stabilizing tube DZ is 5-7V, the ChargePump module comprises five groups of annular inverters, the five groups of annular inverters are connected with a capacitor and are connected with a group of series diodes through the capacitor, the series diodes are connected with a PMOS tube P2 and a PMOS tube P3, the PMOS tube P2 and a PMOS tube P3 are connected with an NMOS tube N2 and an NMOS tube P3, and a bias current Ib passes through an NMOS and a PMOS current mirror, and a fixed current source is obtained at the CPO pin.

The working principle is as follows: after the rectifier is powered on, namely the anode VIN of the rectifier is powered on, because the MOSFET has a parasitic diode to the drain terminal, and assuming that the forward voltage drop of the parasitic diode is 0.7V, VIN-0.7V is obtained at the cathode OUT of the rectifier firstly, then the voltage of a charge pump pin CPO of the chip is gradually increased to VIN + VDZ because an external capacitor C1 is charged, at the moment, a driving tube P1 is triggered to rapidly pull up a Gate pin because VOUT < VIN-75mV, for an external power tube MOSFET, the current capability of the MOSFET is greatly enhanced because the voltage of the Gate pin is rapidly increased, so that the cathode voltage VOUT is rapidly increased until VIN-75mV, then the voltage of the Gate pin is adjusted by an internal operational amplifier AMP of the IC, the AMP and the MOSFET actually form a negative feedback structure, when VOUT is low and VOUT +25mV < VIN, the AMP output is high, namely Vgs of the MOSFET is increased, the current capability is enhanced, the OUT voltage is pulled high, when VOUT is biased, i.e., VOUT +25mV > VIN, the AMP output is low, Vgs of the MOSFET decreases, the current capability becomes weak, the OUT voltage decreases, and thus the cathode voltage of the final rectifier is maintained at a level 25mV lower than the anode voltage by negative feedback.

The chip constantly keeps the detection of the anode voltage and the cathode voltage of the rectifier, the condition that the anode voltage is not changed, and the change of the cathode voltage controls the action of the driving tubes P1, N1 and the operational amplifier AMP on the Gate pins. Referring to FIG. 2, the OUT voltage is lower than VIN-75mV, DRV1 is low, the P1 transistor keeps pulling up the Gate, and the N1 transistor is closed; OUT voltage is higher than VIN +25mV, DRV2 is high level, N1 tube pulls down the Gate, P1 tube is closed; in the region where the driving transistors P1, N1 are active, the operational amplifier AMP is hardly active due to too weak current capability, and only when VIN-75mV < VOUT < VIN +25mV, both P1 and N1 are turned off, the operational amplifier AMP can really regulate Gate, and finally VOUT = VIN-25 mV.

The structure of the chargedump module is shown in fig. 3, the front five groups of ring inverters form an oscillator function, the oscillator can form a typical charge pump structure together with a rear capacitor and a series diode, the voltage of the source ends of P1 and P2 is raised finally, a fixed current source can be obtained at a CPO pin after bias current Ib passes through an NMOS current mirror and a PMOS current mirror, and the current source charges an external capacitor to raise the voltage of the CPO pin.

In the description of the present invention, it should be noted that the terms "upper", "lower", "left", "right", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention; furthermore, unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, as they may be fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.

Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made without departing from the spirit and scope of the present invention.

Claims (7)

1. A low-loss ideal diode is characterized by comprising a control IC, a capacitor C1 and an enhancement type MOSFET, wherein a power supply pin VIN of the control IC is connected with a source end of the enhancement type MOSFET and is used as an anode of a rectifier, a charge pump pin CPO of the control IC is connected with the source end of the MOSFET through the capacitor C1, a driving pin Gate of the control IC is connected with a Gate end of the enhancement type MOSFET, and a pin OUT of the control IC is connected with a drain end of the MOSFET and is used as a cathode and an output of the rectifier.

2. The low-loss ideal diode of claim 1, wherein the control IC internally comprises a comparator CMP1, a comparator CMP2, an operational amplifier AMP, a level conversion module, an LDO/BIAS/UVLO module, a ChargePump module, an NMOS transistor N1 and a PMOS transistor P1, a CPO pin of the ChargePump module is connected with a capacitor C1, a voltage stabilizing tube DZ is arranged between the CPO pin and the anode voltage VIN, two input ends of a comparator CMP1, a comparator CMP2 and an operational amplifier AMP are respectively connected with the anode voltage VIN and the cathode voltage VOUT, output ends of the comparator CMP1 and the comparator CMP2 are connected with a level conversion module, the level conversion module is connected with an NMOS tube N1 and a PMOS tube P1, the level conversion module is used for converting high and low levels VCC and GND output by the two comparators into high and low levels CPO and VIN, the NMOS transistor N1 and the PMOS transistor P1 are drive transistors of the IC, the source end of the PMOS transistor P1 is connected with the CPO voltage, and the source end of the NMOS transistor N1 is connected with the VIN voltage.

3. The low loss ideal diode of claim 2, wherein the difference between said cathode voltage VOUT and anode voltage VIN is equal to 25 mV.

4. The low loss ideal diode of claim 2, wherein the pull-up PMOS transistor P1 is controlled to pull up the Gate pin rapidly when the cathode voltage VOUT of the rectifier is lower than the anode voltage VIN-75mV via the comparator CMP1, and the pull-down NMOS transistor N1 is controlled to pull down the Gate pin rapidly when the cathode voltage VOUT-25mV of the rectifier is higher than the anode voltage VIN via the comparator CMP 2.

5. A low loss ideal diode according to claim 3 or 4, wherein the voltage value of the voltage regulator DZ is 5-7V.

6. The diode of claim 5, wherein said ChargePump module comprises five ring inverters, said five ring inverters are connected with a capacitor, and connected with a series diode through the capacitor, said series diode is connected with PMOS transistor P2 and PMOS transistor P3, and PMOS transistor P2 and PMOS transistor P3 are connected with NMOS transistor N2 and NMOS transistor P3.

7. The diode of claim 6, wherein a fixed current source is obtained at the CPO pin after the bias current Ib passes through the NMOS and PMOS current mirrors.

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