CN214794978U - Double-channel alternative integral frequency converter output voltage sampling circuit - Google Patents
Double-channel alternative integral frequency converter output voltage sampling circuit Download PDFInfo
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- CN214794978U CN214794978U CN202121198894.1U CN202121198894U CN214794978U CN 214794978 U CN214794978 U CN 214794978U CN 202121198894 U CN202121198894 U CN 202121198894U CN 214794978 U CN214794978 U CN 214794978U
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- 238000005070 sampling Methods 0.000 title claims abstract description 31
- 239000003990 capacitor Substances 0.000 claims abstract description 12
- 230000010354 integration Effects 0.000 claims description 17
- 230000002093 peripheral effect Effects 0.000 claims description 4
- 230000000737 periodic effect Effects 0.000 abstract description 4
- 238000007599 discharging Methods 0.000 abstract 1
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Abstract
The utility model discloses a converter output voltage sampling circuit of binary channels integral in turn relates to converter output voltage and detects technical field, including binary channels integrating circuit, integral reset circuit and output signal switching circuit, integrating circuit carries out the integral to the PWM square wave voltage of converter output, realizes calculating impulse voltage's average value in every carrier wave. The integral reset circuit is used for discharging electric charges of a capacitor in the integral circuit, so that integral zero clearing is realized, and normal work of the next period is guaranteed. The dual-channel integrating circuit realizes the continuous operation of the circuit through alternate work and reset, and can realize the periodic sampling of the square wave voltage output by the frequency converter at low cost by matching with the interrupt time sequence control of the main control DSP of the frequency converter.
Description
Technical Field
The utility model relates to a converter output voltage detects technical field, concretely relates to converter output voltage sampling circuit of binary channels integration in turn.
Background
When the frequency converter adopts a non-encoder vector control driving motor, the on-load performance is sensitive to the precision of output voltage, however, under the influence of nonlinear factors such as dead zones of switching devices and the like, the actual output voltage and the voltage given in a program often have larger deviation, and the performance under low speed is greatly influenced. At this time, the output voltage needs to be sampled and fed back to obtain better performance. In addition, in other applications, the output voltage of the frequency converter needs to be sampled. However, the output of the frequency converter is pwm square wave voltage containing a large number of harmonics, and what is actually needed in software is the real-time value of its fundamental wave, i.e. the average value of the pwm wave voltage in each carrier period. This presents great difficulties for sampling. In practical application, one scheme is to filter out high-frequency harmonics in pwm waves through a low-pass filter, but the scheme requires a deeper filtering depth, which causes a larger phase delay and amplitude attenuation of fundamental waves, and the filtering effects are different under different fundamental wave frequencies, and corresponding compensation needs to be performed in software according to real-time frequency, so that the effect is not ideal. And the other method is to sample by an ADC (analog to digital converter) which is far higher than the switching frequency, namely so-called periodic sampling, and then calculate and output the average value of the voltage in each carrier wave by operation processing.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a converter output voltage sampling circuit of binary channels integration in turn realizes converter output voltage fundamental wave sampling through the hardware circuit mode. Compared with a low-pass filtering fundamental wave sampling mode, the scheme has the advantages of no phase delay and amplitude attenuation, and compared with a high-frequency periodic sampling mode, the scheme has the advantages of simple circuit and low cost.
A dual-channel alternate integration frequency converter output voltage sampling circuit comprises a dual-channel integration circuit, an integration reset circuit and an output signal switching circuit;
the dual-channel integrating circuit comprises a first operational amplifier U1 and a second operational amplifier U2, wherein the non-inverting input end of the first operational amplifier U1 is grounded, a first integrating capacitor C1 is connected between the inverting input end and the output end of the first operational amplifier U1 in a bridging mode, peripheral circuits of the second operational amplifier U2 are the same as those of the first operational amplifier, the non-inverting input end of the second operational amplifier U2 is grounded, and a second integrating capacitor C2 is connected between the inverting input end and the output end of the second operational amplifier U2 in a bridging mode;
the integral reset circuit comprises a first analog gating switch S1 and a fourth analog gating switch S4, wherein the output of a frequency converter at one end of the first analog gating switch S1 is grounded, the other input end of the first analog gating switch S1 is grounded, the output of the first gating analog switch S1 is connected to the input of a first operational amplifier U1, the output of a frequency converter at one end of a fourth analog gating switch S4 is grounded, the other input end of the fourth gating analog gating switch S4 is connected to the input of a second operational amplifier U2;
the output signal switching circuit comprises a third analog gating switch S3 and a master control DSP, two input ends of the third analog gating switch S3 are respectively connected with the outputs of the first operational amplifier U1 and the second operational amplifier U2, and the output of the third analog gating switch S3 is connected with an ADC port of the master control DSP.
Preferably, the output of the first gating analog switch S1 is connected to the inverting input terminal of the first operational amplifier U1 through a zero-th resistor R0, and the output of the fourth gating analog switch S4 is connected to the inverting input terminal of the second operational amplifier U2 through a first resistor R1.
Preferably, the integral reset circuit further comprises a second analog switch S2 and a fifth analog switch S5, the second analog switch S2 is connected between the inverting input terminal and the output terminal of the first operational amplifier U1, and the fifth analog switch S5 is connected between the inverting input terminal and the output terminal of the second operational amplifier U2.
Preferably, the first analog gating switch S1, the second analog gating switch S2, the third analog gating switch S3, the fourth analog gating switch S4 and the fifth analog gating switch S5 are all connected to GPIO ports of the main control DSP.
The utility model has the advantages that: and the fundamental wave sampling of the output voltage of the frequency converter is realized in a hardware circuit mode. Compared with a low-pass filtering fundamental wave sampling mode, the scheme has the advantages of no phase delay and amplitude attenuation, and compared with a high-frequency periodic sampling mode, the scheme has the advantages of simple circuit and low cost.
Drawings
Fig. 1 is a circuit diagram of the output voltage sampling circuit of the dual-channel alternative integral frequency converter of the present invention;
FIG. 2 is a schematic diagram of the two-channel alternate integration and sampling process of the present invention;
Detailed Description
In order to make the technical means, creation features, achievement purposes and functions of the present invention easy to understand, the present invention is further described below with reference to the following embodiments.
As shown in fig. 1 to 2, a dual-channel alternate integration frequency converter output voltage sampling circuit is composed of a dual-channel integration circuit, an integration reset circuit, an output signal switching circuit and a matched switching device control scheme. The input voltage signal is alternately input into the dual-channel integrating circuit by taking the carrier period as an interval unit, and is used for solving the voltage average value in each carrier period. The integral reset circuit alternately resets the corresponding integral capacitor charges, and continuous operation of the circuit is ensured. The output signal switching is responsible for outputting the effective voltage in each switching period for sampling by an ADC port of the DSP. Correspondingly, in order to ensure the correctness of the sampling voltage of the DSP, the GPIO port of the main control DSP of the frequency converter needs to control the operation logic and timing of the switching device therein.
The dual-channel integration circuit for the frequency converter output voltage sampling scheme is connected to the inverting input end of the first operational amplifier U1 through one end of a zero-th resistor R0, and the non-inverting input end of the first operational amplifier U1 is grounded. A first integrating capacitor C1 is connected across the inverting input and output of the first operational amplifier U1. The peripheral circuit of the second operational amplifier U2 is the same as that of the first operational amplifier, one end of the first resistor R1 is connected to the inverting input terminal of the second operational amplifier U2, and the non-inverting input terminal of the second operational amplifier U2 is grounded. A second integrating capacitor C2 is connected across the inverting input and output of the second operational amplifier U2.
The integration reset circuit for the frequency converter output voltage sampling scheme is characterized in that an output voltage signal of the frequency converter is connected from one end of a first analog gating switch S1, the other input end of S1 is grounded, and the output of the first gating analog switch is connected to the input of a first integrator; the output voltage signal of the frequency converter is connected from one end of a fourth analog gating switch S4, the other input end of the S4 is grounded, and the output of the fourth gating analog switch is connected to the input of the second integrator; the second analog switch S2 is connected between the inverting input terminal and the output terminal of the first integrator; a fifth analog switch S5 is connected between the inverting input and the output of the second integrator.
The output signal switching circuit for the frequency converter output voltage sampling scheme is characterized in that the outputs of the first integrator and the second integrator are respectively connected to two input ends of a third analog gating switch S3, and the output end of S3 is connected to an ADC port of a master control DSP. The output of the first or second integrator can be selected to access the ADC port by controlling the drive signal of the third analogue gate switch.
The switching device control scheme is characterized in that a double-channel integrator command is given to enable the double-channel integrator command to be in alternate working and resetting states, GPIO is turned over at the initial position of each ADC interrupt program of a DSP, so that an integrator which is originally in the resetting state enters the working state, a voltage signal is input to the integrator through a corresponding analog gating switch, meanwhile, a bleeder switch which is connected to two ends of a capacitor in parallel is disconnected, the other integrator which is originally in the working state enters the resetting state, the analog gating switch signal of an input end is grounded, the bleeder switches which are connected to two ends of the capacitor in parallel are closed, and at the moment, an output signal switching circuit selects effective signals of the integrator which is in the working state to be output. At the start of the next ADC interrupt routine, the GPIO is flipped, and the process is similar to that described above.
The specific implementation mode and principle are as follows:
the voltage signal is inputted from one end of the first analog gating switch S1, and the other input end of the first analog gating switch S1 is grounded. The output of the first analog gating switch is connected to one end of a zero resistor R0, the other end of the zero resistor R0 is connected to the inverting input end of the first operational amplifier U1, and the non-inverting input end of the first operational amplifier U1 is grounded. The second analog switch S2 is connected in parallel with the first integrating capacitor C1 and is connected across the inverting input terminal and the output terminal of the first operational amplifier U1. The peripheral circuits of the second operational amplifier U2 are the same as those of the first operational amplifier, signals are input from one input end of the fourth analog gating switch S4, and the other input end of the fourth analog gating switch S4 is grounded. The output of the analog gating switch S4 is connected to one end of the first resistor R1, the other end of the first resistor R1 is connected to the inverting input terminal of the second operational amplifier U2, and the non-inverting input terminal of the second operational amplifier U2 is grounded. The fifth analog switch S5 is connected in parallel with the second integrating capacitor C2 and is connected across the inverting input terminal and the output terminal of the second operational amplifier U2. The output end of the first operational amplifier U1 and the output end of the second operational amplifier U2 are respectively connected to the input end of the third analog gating switch S3, and the output end of the third analog gating switch S3 is connected to the ADC port of the frequency converter main control DSP for sampling. After the control signals of the first, third and fourth analog gating switches and the second and fifth analog switches are processed through logic combination such as NOT gates and the like, the control signals are connected to a GPIO pin of a main control DSP of the frequency converter, and the specific logic combination is slightly different according to practical application.
Based on the foregoing, the utility model discloses a hardware circuit mode realizes converter output voltage fundamental wave sampling, and this scheme is compared and has the advantage of no phase delay and amplitude decay in low pass filtering fundamental wave sampling mode, compares in high frequency cycle sampling mode and has the advantage that the circuit is simple, with low costs.
It will be appreciated by those skilled in the art that the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The embodiments disclosed above are therefore to be considered in all respects as illustrative and not restrictive. All changes which come within the scope of the invention or which are equivalent to the scope of the invention are embraced by the invention.
Claims (4)
1. A dual-channel alternate integration frequency converter output voltage sampling circuit is characterized by comprising a dual-channel integration circuit, an integration reset circuit and an output signal switching circuit;
the dual-channel integrating circuit comprises a first operational amplifier U1 and a second operational amplifier U2, wherein the non-inverting input end of the first operational amplifier U1 is grounded, a first integrating capacitor C1 is connected between the inverting input end and the output end of the first operational amplifier U1 in a bridging mode, peripheral circuits of the second operational amplifier U2 are the same as those of the first operational amplifier, the non-inverting input end of the second operational amplifier U2 is grounded, and a second integrating capacitor C2 is connected between the inverting input end and the output end of the second operational amplifier U2 in a bridging mode;
the integral reset circuit comprises a first analog gating switch S1 and a fourth analog gating switch S4, wherein the output of a frequency converter at one end of the first analog gating switch S1 is grounded, the other input end of the first analog gating switch S1 is grounded, the output of the first gating analog switch S1 is connected to the input of a first operational amplifier U1, the output of a frequency converter at one end of a fourth analog gating switch S4 is grounded, the other input end of the fourth gating analog gating switch S4 is connected to the input of a second operational amplifier U2;
the output signal switching circuit comprises a third analog gating switch S3 and a master control DSP, two input ends of the third analog gating switch S3 are respectively connected with the outputs of the first operational amplifier U1 and the second operational amplifier U2, and the output of the third analog gating switch S3 is connected with an ADC port of the master control DSP.
2. The dual-channel alternating integration frequency converter output voltage sampling circuit according to claim 1, wherein: the output of the first gate analog switch S1 is connected to the inverting input terminal of the first operational amplifier U1 through a zero-th resistor R0, and the output of the fourth analog gate switch S4 is connected to the inverting input terminal of the second operational amplifier U2 through a first resistor R1.
3. The dual-channel alternating integration frequency converter output voltage sampling circuit according to claim 1, wherein: the integral reset circuit further comprises a second analog switch S2 and a fifth analog switch S5, the second analog switch S2 is connected between the inverting input terminal and the output terminal of the first operational amplifier U1, and the fifth analog switch S5 is connected between the inverting input terminal and the output terminal of the second operational amplifier U2.
4. The dual-channel alternating integration frequency converter output voltage sampling circuit according to claim 1, wherein: the first analog gating switch S1, the second analog gating switch S2, the third analog gating switch S3, the fourth analog gating switch S4 and the fifth analog gating switch S5 are all connected with GPIO ports of the master DSP.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121198894.1U CN214794978U (en) | 2021-05-31 | 2021-05-31 | Double-channel alternative integral frequency converter output voltage sampling circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121198894.1U CN214794978U (en) | 2021-05-31 | 2021-05-31 | Double-channel alternative integral frequency converter output voltage sampling circuit |
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| Publication Number | Publication Date |
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| CN214794978U true CN214794978U (en) | 2021-11-19 |
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| CN202121198894.1U Active CN214794978U (en) | 2021-05-31 | 2021-05-31 | Double-channel alternative integral frequency converter output voltage sampling circuit |
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2021
- 2021-05-31 CN CN202121198894.1U patent/CN214794978U/en active Active
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Effective date of registration: 20231122 Address after: 217028, No. 200 Linghu Avenue, Xinwu District, Wuxi City, Jiangsu Province, China, F7 Patentee after: Shenghang magnetic power technology (Wuxi) Co.,Ltd. Address before: 210001 No.1, Yangshan North Road, Qixia District, Nanjing City, Jiangsu Province Patentee before: Nanjing Vocational University of Industry Technology |