CN107332542A - A kind of heavy current pulse signal source - Google Patents
A kind of heavy current pulse signal source Download PDFInfo
- Publication number
- CN107332542A CN107332542A CN201710556258.3A CN201710556258A CN107332542A CN 107332542 A CN107332542 A CN 107332542A CN 201710556258 A CN201710556258 A CN 201710556258A CN 107332542 A CN107332542 A CN 107332542A
- Authority
- CN
- China
- Prior art keywords
- pulse
- output
- amplitude
- control signal
- current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000003079 width control Methods 0.000 claims abstract description 48
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims abstract description 32
- 230000008859 change Effects 0.000 claims abstract description 16
- 238000002955 isolation Methods 0.000 claims abstract description 14
- 230000008878 coupling Effects 0.000 claims abstract description 12
- 238000010168 coupling process Methods 0.000 claims abstract description 12
- 238000005859 coupling reaction Methods 0.000 claims abstract description 12
- 230000003287 optical effect Effects 0.000 claims abstract description 12
- 238000004088 simulation Methods 0.000 claims description 7
- 238000001914 filtration Methods 0.000 claims description 4
- 230000000630 rising effect Effects 0.000 abstract description 7
- 238000010586 diagram Methods 0.000 description 14
- 238000005259 measurement Methods 0.000 description 7
- 238000006243 chemical reaction Methods 0.000 description 6
- 230000005611 electricity Effects 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 210000001367 artery Anatomy 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 210000003462 vein Anatomy 0.000 description 3
- 239000008186 active pharmaceutical agent Substances 0.000 description 2
- 230000003321 amplification Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 238000003786 synthesis reaction Methods 0.000 description 2
- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical compound [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 230000009514 concussion Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- -1 gold aluminum Chemical compound 0.000 description 1
- 229910052744 lithium Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000009993 protective function Effects 0.000 description 1
- 238000012887 quadratic function Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000003381 stabilizer Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/017—Adjustment of width or dutycycle of pulses
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K7/00—Modulating pulses with a continuously-variable modulating signal
- H03K7/08—Duration or width modulation ; Duty cycle modulation
Landscapes
- Dc-Dc Converters (AREA)
Abstract
The invention discloses a kind of heavy current pulse signal source, high current amplitude and pulsewidth are set by front panel, corresponding DC reference voltage i.e. amplitude and pulse-width control signal are produced by digital circuit, it ensure that amplitude, the pulsewidth precision of heavy current pulse, then, by analog switch by DC reference voltage VsdThe input voltage controlled current source input in analog pulse width control signal Cw ' significant levels are interval, voltage controlled current source is then exported and DC reference voltage VsdThe constant current of linear change, it is ensured that heavy current pulse rising edge is precipitous, the small requirement of overshoot.Simultaneously, digital circuit as control is that amplitude control signal generation circuit is connected and is controlled with analog circuit respectively by two optical coupling isolation circuits OC1, OC2 with pulse-width control signal generation circuit by the present invention, effectively prevent analog circuit high voltage to the issuable infringement of digital circuit.
Description
Technical field
The invention belongs to signal generation technology field, more specifically, it is related to a kind of heavy current pulse signal source.
Background technology
With the development of high power semi-conductor actuation techniques, heavy current pulse signal source (or be heavy current pulse constant current
Source) it is used widely in fields such as test, industry, military affairs, and play very important effect.
Existing heavy current pulse generating means, such as on 07 02nd, 2014 Granted publication, notification number be
CN203688609U, entitled " a kind of heavy current pulse generating means " Chinese utility model patent, by being internally integrated A/D
ARM microcontroller module, lithium battery, voltage conversion circuit module, reverse exciting switching voltage regulator circuit module and the high current of converter
Pulse discharge circuit module composition.Because pulse signal PWM is produced by ARM microcontroller, and use reverse exciting switching voltage regulator circuit
Amplification mode is driven, its amplitude of heavy current pulse produced, pulsewidth precision and overshoot, rise time etc. be not all up to
To the requirement of signal source.
The content of the invention
It is an object of the invention to overcome the deficiencies in the prior art, a kind of heavy current pulse signal source is proposed, it is big to improve
Amplitude, the pulsewidth precision of current impulse, meanwhile, make that heavy current pulse rising edge is precipitous, overshoot is small, finally meets it as letter
The requirement that number source is used.
For achieving the above object, heavy current pulse signal source of the present invention, it is characterised in that including：
Front panel, the setting for exporting high current amplitude and pulsewidth, and setting value is sent into pulse current generation circuit；
Pulse current generation circuit, for exporting corresponding amplitude and arteries and veins to load resistance RL according to front panel user setting value
Wide heavy current pulse signal；
The pulse current generation circuit includes amplitude control signal generation circuit, pulsewidth modulation D/A change-over circuits, pulsewidth
Control signal generation circuit, analog switch, voltage controlled current source；
The amplitude control signal generation circuit output duty cycle amplitude control PWM ripple CA proportional to amplitude set value, will
Amplitude controls PWM ripples CA as optical coupling isolation circuit OC1 input, is converted into the simulation that low and high level is respectively 75V and 70V
Pwm control signal CA ', then as the control signal that amplitude analog switch is controlled in pulsewidth modulation D/A change-over circuits；
In pulsewidth modulation D/A change-over circuits, by simulating the control that pwm control signal CA ' is switched to amplitude analog, arteries and veins
The input of width modulation D/A change-over circuits is that low and high level is respectively that reference voltage Vr and analog references ground voltage AGND is 70V's
PWM ripples, after handling after filtering, export the DC reference voltage V proportional to input PWM ripple dutycyclessd；
The pulse-width control signal generation circuit output pulse width square wave equal with width sets value is used as pulse-width control signal Cw；
Pulse-width control signal Cw is converted to analog pulse width control signal Cw ' control analog switches by optical coupling isolation circuit OC2, and simulation is opened
Close DC reference voltage VsdThe input voltage controlled current source input in analog pulse width control signal Cw ' significant levels are interval；
Controlled constant-current source circuit is voltage control electric current type circuit, and its output current amplitude and input voltage amplitude are linear
Relationship change；In analog pulse width control signal Cw ' control DC reference voltages VsdWhen inputting voltage controlled current source input, voltage-controlled perseverance
Stream source is exported and DC reference voltage VsdThe constant current of linear change.
The object of the present invention is achieved like this.
Heavy current pulse signal source of the present invention sets high current amplitude and pulsewidth by front panel, is produced by digital circuit
Corresponding DC reference voltage is amplitude and pulse-width control signal, it is ensured that amplitude, the pulsewidth precision of heavy current pulse, so
Afterwards, in analog switch by DC reference voltage VsdThe voltage-controlled constant current of input in analog pulse width control signal Cw ' significant levels are interval
Source input, voltage controlled current source output and DC reference voltage VsdThe constant current of linear change, it is ensured that high current
Rising edge of a pulse is precipitous, the small requirement of overshoot.Meanwhile, the digital circuit as control is amplitude control signal production by the present invention
Raw circuit is connected with analog circuit respectively with pulse-width control signal generation circuit by two optical coupling isolation circuits OC1, OC2 goes forward side by side
Row control, effectively prevent analog circuit high voltage to the issuable infringement of digital circuit.
Brief description of the drawings
Fig. 1 is a kind of embodiment theory diagram of heavy current pulse signal source of the present invention；
Fig. 2 is the schematic block circuit diagram of pulse current generation circuit shown in Fig. 1；
Fig. 3 be user's setting amplitude set value and amplitude control PWM ripples CA graph of a relation；
Fig. 4 is amplitude set value and pulsewidth modulation D/A change-over circuits output DC reference voltage VsdGraph of a relation；
Fig. 5 is a kind of embodiment principle schematic of amplitude control signal generation circuit shown in Fig. 2；
Fig. 6 is a kind of embodiment schematic diagram of the change-over circuit of pulsewidth modulation D/A shown in Fig. 2；
Fig. 7 is a kind of embodiment principle schematic of pulse-width control signal generation circuit shown in Fig. 2；
Fig. 8 is the timing diagram of pulse-width control signal generation circuit shown in Fig. 7；
Fig. 9 is a kind of embodiment principle schematic of controlled constant-current source circuit shown in Fig. 2；
Figure 10 is FET protection circuit schematic diagram；
Figure 11 is FET observation circuit schematic diagram working properly；
Figure 12 is load two ends pulse voltage waveform figure when heavy current pulse signal amplitude is respectively 3.00A；
Figure 13 is load two ends pulse voltage waveform figure when heavy current pulse signal amplitude is respectively 5.00A.
Embodiment
The embodiment to the present invention is described below in conjunction with the accompanying drawings, so as to those skilled in the art preferably
Understand the present invention.Requiring particular attention is that, in the following description, when known function and design detailed description perhaps
When can desalinate the main contents of the present invention, these descriptions will be ignored herein.
Fig. 1 is a kind of embodiment theory diagram of heavy current pulse signal source of the present invention.
In the present embodiment there is provided a output pulse current amplitude 0-9.99A is adjustable, pulse width 0-99.99ms can
Adjust, output amplitude precision is less than 2%, pulsewidth precision and shown less than 1%, overshoot less than 5%, rise time less than 30us, amplitude
Show that precision is less than the heavy current pulse signal source that 1%, pulsewidth display precision is less than 1%.It has that circuit structure is simple, arranges value
With reality output pulse current parameter can be shown simultaneously, rising edge is precipitous, unloaded and overload protection, system working stability it is excellent
Point.
In the present embodiment, as shown in figure 1, heavy current pulse signal source of the present invention, including front panel 1, pulse current are produced
Raw circuit 2 and measurement and display circuit 3.
Front panel 1 exports the amplitude and width sets of high current according to user for heavy current pulse signal source, and by phase
The setting value feeding pulse current generation circuit 2 answered, user's setting value that pulse current generation circuit 2 is sent into according to front panel 1
The heavy current pulse signal of corresponding amplitude and pulsewidth is exported to load resistance RL.
Measurement is used for the measurement and display to output heavy current pulse signal amplitude and pulsewidth with display circuit 3, wherein right
The measurement of amplitude is to be based on Ohm's law, and the measurement to heavy current pulse signal amplitude is converted into and remembered using peak value of pulse detection
Recall measurement of the circuit 302 to the two ends pulse voltage of sample resistance 301 to realize, then by the conversion driving front panel of A/D converter 303
1 LED charactrons 103 are shown.Measurement to heavy current pulse signal pulsewidth is being taken by pulse width detection circuit 304
The both end voltage of sample resistance 301 is not 0 interval, and enablement count device 305 is counted to clock signal, then institute's count value is passed through
LED charactrons 104 are shown.
Pulse current generation circuit is the core circuit of heavy current pulse signal source, is also innovation of the present invention, can root
The heavy current pulse signal of corresponding amplitude and pulsewidth is produced according to setting value, while having triggering mode selection, overload and unloaded guarantor
Protective function.
Fig. 2 is the schematic block circuit diagram of pulse current generation circuit shown in Fig. 1.
1st, general structure
In the present embodiment, as shown in Fig. 2 pulse current generation circuit 2 includes：Amplitude control signal generation circuit 201,
Pulsewidth modulation D/A change-over circuits 202, analog switch 203, pulse-width control signal generation circuit 204, voltage controlled current source 205.
(1), amplitude set
In the present embodiment, amplitude toggle switch 101 is made up of three 8421 toggle switch, can be respectively used to needed for setting
Individual position, tenths and the percentiles of amplitude (unit is ampere).Its 8421 code value exported is produced as amplitude control signal
The raw Counter data input pin of circuit 201 input, control amplitude control signal generation circuit 201 is exportedDutycycle is set with amplitude The proportional amplitude control PWM ripples CA of definite value.
Using amplitude control PWM ripples CA as optical coupling isolation circuit OC1 input, be converted into low and high level be respectively 75V and 70V simulation pwm control signalCA ', then as the control that amplitude analog switch is controlled in pulsewidth modulation D/A change-over circuits 202
Signal processed；
In pulsewidth modulation D/A change-over circuits 202, by simulating the control that pwm control signal CA ' is switched to amplitude analog
System, the input of pulsewidth modulation D/A change-over circuits is that low and high level is respectively that reference voltage Vr and analog references ground voltage AGND is
70V PWM ripples, the DC reference electricity proportional to input PWM ripple dutycycles will be exported after handling after filteringPressureVsdOutput.
(2), width sets
Pulsewidth toggle switch 102 is made up of four 8421 toggle switch, ten of pulsewidth needed for being respectively used to set, individual
Position, tenths and percentiles (unit is millisecond).Its 8421 code value exported is used as pulse-width control signal generation circuit 204
Counter data input pin is inputted, the square wave conduct equal with width sets value of pulse-width control signal generation circuit output pulse width
Pulse-width control signal Cw.
Pulse-width control signal Cw is converted to analog pulse width control signal Cw ' controls simulation by optical coupling isolation circuit OC2 and opened
Close, analog switch is by DC reference voltage VsdThe input voltage controlled current source in analog pulse width control signal Cw ' significant levels are interval
Input.
(3), pulse current is produced
Controlled constant-current source circuit 205 is voltage control electric current type circuit, its output current amplitude and input voltage amplitude into
Linear relationship changes；In analog pulse width control signal Cw ' control DC reference voltages VsdWhen inputting voltage controlled current source input, pressure
Control constant-current source output and DC reference voltage VsdThe constant current of linear change.
Because the power consumption born in controlled constant-current source circuit on FET is with the resistance of external load and output high current
The change of pulse signal amplitude and change, ensure that FET can work in full range to reduce FET power consumption
Make under rated disspation, in the present embodiment, obtain total defeated using the method that three road controlled constant-current source circuit outputs are in parallel
Go out.
(4), unloaded, overload protection
The damage that unloaded and overload may in itself be caused to user, measured device and instrument (heavy current pulse signal source)
Evil, protection circuit 206 can when there are unloaded and overload situations in system output alarm signal A-over, pass through light-coupled isolation electricity
Output pulse width control signal locking after road OC3 is converted to digital alarm signal D-over and handled by exception handling circuit 207
Signal W-lock closes the pulse-width control signal Cw outputs of pulse-width control signal generation circuit 204, so as to stop exporting high current
Pulse signal.
2nd, amplitude control signal generation circuit
To make voltage controlled current source 205 set the adjustable heavy current pulse signal of output amplitude according to amplitude toggle switch 101,
The DC reference voltage V of respective magnitudes need to be provided itsd.Amplitude control signal generation circuit 201 i.e. by produce dutycycle with
The proportional amplitude control PWM ripple CA of amplitude set value, and then control the output amplitude of pulsewidth modulation D/A change-over circuits 202 and PWM
The proportional DC reference voltage V of dutycyclesd, so that the output amplitude of voltage controlled current source 205 and setting value identical high current
Pulse signal.The amplitude set value of user's setting and amplitude control PWM ripples CA relation it is as shown in Figure 3.
First carry out subtracting counting as shown in figure 3, in the presence of counting clock A_CLK, after amplitude set value assignment, when reducing to
When 0, assignment, and carry out plus count again when being added to 999, carries out assignment, carries out subtracting counting, such addition and subtraction again again
Count circulation to carry out, so produce the dutycycle amplitude control PWM ripple CA proportional to amplitude set value.
Amplitude set value and the output DC reference voltage of pulsewidth modulation D/A change-over circuits 202 VsdRelation as shown in Figure 4 two
Person is linear.
In voltage controlled current source 205 is operated in using 70V as the analog module with reference to ground level in the present invention, if choosing
Select and then need to use multiple light-coupled isolation device ability using conventional integrated D/A conversion chips acquisition Adjustable DC Reference Voltage
The conversion of digital input signal is completed, and the amplitude control signal generation circuit 201 that the present invention is designed coordinates homemade pulsewidth
Modulation D/A change-over circuits 202 then only need that using a light-coupled isolation device i.e. optical coupling isolation circuit OC1 required essence just can be obtained
Spend desired DC reference voltage Vsd。
In the present invention, amplitude control signal generation circuit 201 be by three cascade decimal add subtraction count devices, one
S/R latch, one and door and two NAND gates are constituted, the 8421 code values i.e. amplitude set that amplitude toggle switch 101 is exported
It is worth and is inputted as the setting value of three decimal add subtraction count devices, addition and subtraction wheel flow accounting is carried out to arranges value by counter
The purpose of the adjustable PWM ripples of output duty cycle then can be achieved.Amplitude control signal generation circuit 201 is as shown in Figure 5.
In the present embodiment, as shown in figure 5, in amplitude control signal generation circuit 201, high-order decimal add subtraction
Counter plus counting input end Pu and subtract the decimal add subtraction count device that counting input end Pd is connected respectively to low one
Carry output Cu and borrow output end Cd, the setting value input of each decimal add subtraction count device is D0~D3
Be connected with the code value output end of 8421 toggle switch, the carry output Cu of the decimal add subtraction count device of highest order and
Output end Cd is borrowed, as two inputs with door, three decimal add subtraction count devices cascaded are used as with the output LD of door
Put several signal LD；Meanwhile, the carry output Cu of the decimal add subtraction count device of highest order distinguishes with output end Cd is borrowed
It is connected with the S ends and R ends of S/R latch, the Q ends output of S/R latch passes through a NAND gate and non-post with counting clock A_CLK
The decimal add subtraction count device for being output to lowest order subtracts counting input end Pd, and the Q' ends of S/R latch output with counting when
Clock A_CLK is output to the decimal add subtraction count device of lowest order by another NAND gate and non-post plus counting input end
Pu, so, the signal of the Q ends output of S/R latch is the dutycycle amplitude control PWM ripple CA proportional to amplitude set value,
Its course of work is as shown in figure 3, the state of S/R latch is input to lowest order ten by NAND gate control counting clock A_CLK and entered
Forward-backward counter processed plus counting input end Pu still subtract counting input end Pd, and then reducing to 0 with door every time or Jia 999
When, during by borrowing or carry signal is high, output high level carries out putting operation to the decimal add subtraction count devices of three cascades,
So as to export the dutycycle amplitude control PWM ripple CA proportional to amplitude set value in S/R latch.
S/R latch Q ends control PWM ripple CA output ends as amplitude, the high electricity of output when counter carries out subtraction count
Flat, counter carries out exporting low level during plus coujnt.The amplitude code code value held time by input counter of low and high level
Determine.Because for any amplitude set value, the counting summation for carrying out a subtraction count and a plus coujnt is all 1000,
So the amplitude control PWM ripple CA cycles are constant, and addition and subtraction gate time is determined by the code value of input amplitude code.Which achieves
The purpose of the adjustable PWM ripples of output cycle certain dutycycle.
3rd, pulsewidth modulation D/A change-over circuits
Pulsewidth modulation D/A change-over circuits 202 realize the pwm signal CA for controlling digital magnitude by filtering and are converted to mould
Intend DC voltage Vsd outputs, so as to provide adjustable reference voltage for controlled constant-current source circuit, circuit theory diagrams are as indicated with 2.
In order to prevent high voltage in analog circuit, heavy current from sealing in and burning digital circuit in digital circuit, while being also
Level conversion is realized, it is respectively 75V and 70V that amplitude control PWM ripples CA switched into low and high level using optical coupling isolation circuit OC1
Simulation pwm control signal CA ', pwm control signal CA ' in pulsewidth modulation D/A change-over circuits as controlling amplitude analog for simulation
The control signal of switch, reference voltage Vr is superimposed upon in CA ' low levels interval on the Vo of zeroing circuit output and sends into single order
Low-pass filter circuit inverting input.The signal for so inputting low-pass filter circuit is to be accounted for amplitude control PWM ripples CA with frequently same
Sky compares but low and high level is respectively Vr+70V and 70V PWM ripples, is less than PWM fundamental frequencies when setting filter cutoff frequency
The higher hamonic wave in PWM ripples can be effectively filtered out when 1/5, so that it is i.e. straight only to leave the DC voltage proportional to PWM duty cycle
Flow reference voltage Vsd, realize the conversion from PWM ripple to DC voltage.
4th, pulse-width control signal generation circuit
By above passing through to the setting for exporting pulse current width with producing principles and methods, pulse-width control signal Cw
The DC reference voltage V that control analog switch exports D/A change-over circuitssdSent into during pulse-width control signal Cw significant levels
Controlled constant-current source circuit input, so as to export and pulse-width control signal pulsewidth identical pulse current.Due to pulse-width controlled letter
Number pulsewidth determine the pulsewidth of final output pulsed current signal.So be can be with defeated for the design core of pulse width control circuit
Go out the pulsewidth code value identical square-wave signal that pulse width is set with front panel.
In the present embodiment, the central principle of pulse-width control signal generation circuit 204 is that setting value is entered by counter
Row subtraction count realizes that upset occurs for accurate timing triggering d type flip flop output again by being opened along synthesis final output with pulsewidth dial-up
Close the pulse-width control signal of arranges value same pulse width.Pulse-width control signal generation circuit principle schematic is as shown in Figure 7.
In the present embodiment, as shown in fig. 7, pulse-width control signal generation circuit includes the decimal add subtraction of four cascades
Counter be lowest order borrow output end Cd respectively with high one subtract counting input end Pd be connected, d type flip flop FF1, D trigger
Device FF2 and two NAND gates；D type flip flop FF1 clock end CK is as the input of trigger signal, and D ends are that D1 meets+5V, Q ends
That is Q1 is output to d type flip flop FF2 D ends i.e. D2；D type flip flop FF2 clock end CK and highest order decimal add subtraction count device
Borrow output end Cd connections；The d type flip flop FF1 output of Q ends and d type flip flop FF2 Q' ends be Q2' export as one with it is non-
Two inputs of door input, the NAND gate output signal is pulse-width control signal Cw；
D type flip flop FF1 Q ends are that inputted with 100KHz pulse signals as another NAND gate two of Q1 outputs are defeated
Enter, what NAND gate output was connected to lowest order decimal add subtraction count device subtracts counting input end Pd；Each decimal system plus-minus
The setting value input of method counter is that D0~D3 is connected with the code value output end of 8421 toggle switch；
So, after trigger signal is arrived, d type flip flop FF1 outputs Q1 is changed into high level, while 100KHz clock signal inputs
The subtracting input of decimal add subtraction count device, and subtraction count is done since width sets value, touched when counter reduces to 0
Hair d type flip flop FF2 overturns output Q2 states, and pulse-width control signal Cw is exported Q1 rising edge by d type flip flop FF1 and touched
Output is synthesized after the trailing edge NAND operation for the output Q2' for sending out d type flip flop FF2.
Because clock signal frequency is 100KHz, when setting pulsewidth code value D to change in 0000-9999, four chip level onlines
The time delay t for borrowing signal of number device afterbody outputL=D0.01ms, so eventually through the arteries and veins obtained along synthesis
Wide control signal Cw low level times are corresponding tL=D0.01ms, has reached pulse-width control signal significant level width
The purpose for being controlled and being changed between 0-99.99ms by pulsewidth toggle switch arranges value, circuit timing diagram is as shown in Figure 8.
5th, controlled constant-current source circuit
Controlled constant-current source circuit using FET as switching tube is the core circuit for producing pulse current, its output current
Amplitude is determined that circuit theory diagrams are as shown in Figure 9 by input voltage amplitude.
Amplifier serves as the effect for comparing amplification in circuit, is had according to its empty short and resolution:
UN=Vsd
Then output current amplitude I is：
I=(VA-Vsd)/Rsd
By above formula, it can be seen that the amplitude of output current is by DC reference voltage VsdWith reference resistance RsdDetermine, and with bearing
Carry change unrelated.So as fixed power source voltage VAWith reference resistance RsdOne timing, output current amplitude is only electric with DC reference
Press VsdLinear change.
Voltage-stabiliser tube Dz plays voltage clamping effect in circuit, and fet gate voltage is limited in into 0.7V-UzScope it
It is interior, it is ensured that FET will not be because grid voltage is excessive and damages.Electric capacity C1, C2 and C3 couple of diverse location in this external circuit
Output pulse waveform has different adjustment effect.Filter capacitor C1 can play a part of smooth input pulse voltage, integral element
Electric capacity C2 can ensure output pulse waveform without concussion, without overshoot, and waveform is smooth.Electric capacity C3 can improve circuit response speed,
Lift output pulse signal rising edge.
The reality of the FET when controlled constant-current source circuit has pulse current generation can be calculated according to circuit theory diagrams
When dissipated power be：
PD=[VA-(RL+RSp+Rsd)·I]·I
In the present embodiment, sampling resistor RspWith reference resistance RsdThe gold aluminum casing resistor that resistance is 0.5 Ω is chosen,
Due to maximum output current I in this patentmaxFor 10A, maximum load resistance RLmaxFor 5 Ω, to allow circuit can be to negative
Carry and the adjustable pulse current of amplitude in gamut scope is provided, therefore according to formula VA=Imax·RLmax(20V is safety electricity to+20V
Pressure allowance) it can be calculated VA=70V.Bring above parameter into PD=[VA-(RL+RSp+Rsd) I] FET can be obtained in I
Real-time dissipated power and the magnitude relation of load resistance and output pulse current are as follows：
PD=70I- (RL+1)·I2
By above formula it can be seen that when dead load resistance is a certain determination value, the dissipated power on FET
It is the quadratic function for exporting pulse current amplitude.Different amplitude pulse electric currents are being loaded and exported with different resistances for guarantee system
When, FET can be operated in below rated disspation value, and output amplitude is realized using three road in parallel controlled constant-current source circuit
The purpose of pulse current.Be computed, when using the scheme of Parallel opertation per the power consumption of FET operationally all the way for：
It can be seen that when exporting identical magnitude current, when exporting pulse current with single channel pulsed constant current supply on FET
Power is compared, and multi-channel parallel every FET power consumption of output pulse current is the 1/n of single channel, has reached reduction FET work(
The purpose of consumption.
6th, protection circuit
FET drain voltage is with output pulse current amplitude when heavy current pulse signal source is in efforts state
With load resistance change and constantly change.When unloaded or overload situations occurs in system, FET drain voltage will exceed
FET can normal work safety value, it is possible to by FET drain voltage is monitored and and safe voltage
Value be compared after as unloaded and overload situations alarm signal.
The P-channel enhancement type FET F6218L used in the present invention in controlled constant-current source circuit U in normal workDS
<0V, once there are unloaded, overload situations, drain voltage UDTo drastically it raise so that UDS>0V,.Due to FET source class electricity
Press USPoint voltage changes between 65V-70V, so need to only set drain electrode safe voltage to be less than 65V, works as UDMagnitude of voltage is higher than safety
Then start corresponding protection mechanism during voltage.To realize above-mentioned functions, devise and be made up of voltage comparator and optical coupling isolator
Protection circuit, voltage comparator complete to UDPoint voltage and the comparison of set safe voltage value, comparative result turn through optocoupler
Digital control circuit is sent into after changing as the output control signal of pulse-width control signal.Protection circuit schematic diagram is as shown in Figure 10.
The terminal voltage of voltage comparator circuit homophase input shown in Figure 10 UTBy resistance R3 and R4 to amplifier source voltage
Produce, its value is
Comparator reverse input end voltage UNPutting voltage is：
Diode D presence realizes the isolation to FET drain voltage and voltage comparator input.Imitate on the spot
Should pipe drain voltage UD<UN+UonWhen, diode is not turned on, and the input voltage of comparator is UN, due to UN<UT, so voltage ratio
U is exported compared with deviceN=+UOM=UA, at this moment optocoupler output digital high；Work as UD>UN+UonWhen, diode current flow, comparator it is defeated
Enter voltage for UD-UonIf, UD-Uon>UT, voltage comparator output UO=-UOM=58V, at this moment optocoupler output digital low.UN+
UonThe safe voltage thresholds as set, UDThe low level that optical coupling isolator is exported during more than secure threshold is entered as over-pressed signal
Enter in digital control module, stop pulsewidth PWM output, pulse current generation module exports no current to protect signal
Source.
Protection circuit during unloaded and overload situations, which occurs, in system will export low level alarm signal, and exception handling circuit will be right
This alarm signal is responded, and produces the output that block signal stops pulse-width control signal, so that halt system output pulse electricity
Stream, reaches the purpose of protection system.Exception handling circuit schematic diagram is as shown in figure 11.
During system unloaded operation, FET drain voltage rises to moment the reference ground level of analog module,
So as to which the safe voltage set more than protection circuit makes it export the unloaded alarm signal of low level, at this moment width is 0.1ms, is risen
The output that this unloaded alarm signal controls S/R latch can be captured at once along the capture signal synchronous with pulse-width control signal
Overturn, so that exporting the unloaded block signal of low level stops the output of pulsewidth PWM ripples, and drive buzzer and alarm LED
Work.
If overload situations occurs in the process of running in system, protection circuit will export low level overload-alarm signal, meeting
Low level is directly produced by S/R latch and overloads block signal termination pulsewidth PWM ripple outputs, so as to reach that halt system is exported
The purpose of pulse current.Abnormality processing can produce block signal to close pulse wide when understanding unloaded and overload by being analyzed above
Control signal output is spent so as to halt system work.When drain voltage recovers normal or access load, turn back on or by
Under manual reset key can with reset lockout signal, while each time produce pulse-width control signal before can all produce blocked reset
Signal, it is ensured that system can recover normal work when FET works in the secure state.
Four, experimental waveforms
Heavy current pulse signal source, in external 5 Ω load resistances, setting output heavy current pulse signal amplitude is respectively
Two ends pulse voltage waveform is loaded when 3.00A, 5.00A as shown in Figure 12,13.
It can be seen that the amplitude of heavy current pulse, pulsewidth precision are high from Figure 12,13, meanwhile, make heavy current pulse rising edge
Precipitous, overshoot is small, realizes the purpose of the present invention.
Although illustrative embodiment of the invention is described above, in order to the technology of the art
Personnel understand the present invention, it should be apparent that the invention is not restricted to the scope of embodiment, to the common skill of the art
For art personnel, as long as various change is in the spirit and scope of the present invention that appended claim is limited and is determined, these
Change is it will be apparent that all utilize the innovation and creation of present inventive concept in the row of protection.
Claims (3)
1. a kind of heavy current pulse signal source, it is characterised in that including：
Front panel, the setting for exporting high current amplitude and pulsewidth, and setting value is sent into pulse current generation circuit；
Pulse current generation circuit, for exporting corresponding amplitude and pulsewidth to load resistance RL according to front panel user setting value
Heavy current pulse signal；
The pulse current generation circuit includes amplitude control signal generation circuit, pulsewidth modulation D/A change-over circuits, pulse-width controlled
Signal generating circuit, analog switch, voltage controlled current source；
The amplitude control signal generation circuit output duty cycle amplitude control PWM ripple CA proportional to amplitude set value, by amplitude
Control PWM ripples CA as optical coupling isolation circuit OC1 input, be converted into the simulation PWM controls that low and high level is respectively 75V and 70V
Signal CA ' processed, then as the control signal that amplitude analog switch is controlled in pulsewidth modulation D/A change-over circuits；
In pulsewidth modulation D/A change-over circuits, by simulating the control that pwm control signal CA ' is switched to amplitude analog, pulsewidth is adjusted
The input of D/A change-over circuits processed is that low and high level is respectively the PWM that reference voltage Vr and analog references ground voltage AGND are 70V
Ripple, the DC reference voltage V proportional to input PWM ripple dutycycles will be exported after handling after filteringsdOutput；
The pulse-width control signal generation circuit output pulse width square wave equal with width sets value is used as pulse-width control signal Cw；Pulsewidth
Control signal Cw is converted to analog pulse width control signal Cw ' control analog switches by optical coupling isolation circuit OC2, and analog switch will
DC reference voltage VsdThe input voltage controlled current source input in analog pulse width control signal Cw ' significant levels are interval；
Controlled constant-current source circuit is voltage control electric current type circuit, and its output current amplitude and input voltage amplitude are linear
Change；In analog pulse width control signal Cw ' control DC reference voltages VsdWhen inputting voltage controlled current source input, voltage controlled current source
Output and DC reference voltage VsdThe constant current of linear change.
2. heavy current pulse signal source according to claim 1, it is characterised in that the amplitude control signal generation circuit
It is made up of the decimal add subtraction count devices of three cascades, S/R latch, one with door and two NAND gates；
High-order decimal add subtraction count device plus counting input end Pu and subtract counting input end Pd be connected respectively to it is low by one
Position decimal add subtraction count device carry output Cu and borrow output end Cd, each decimal add subtraction count device
Setting value input is that D0~D3 is connected with the code value output end of 8421 toggle switch, the decimal add subtraction meter of highest order
Count the carry output Cu of device and borrow output end Cd, as two inputs with door, three cascades are used as with the output LD of door
Decimal add subtraction count device put several signal LD；Meanwhile, the carry output of the decimal add subtraction count device of highest order
Cu and borrow output end Cd and be connected respectively with the S ends and R ends of S/R latch, the output of Q ends and the counting clock A_CLK of S/R latch
The decimal add subtraction count device that lowest order is output to by a NAND gate and non-post subtracts counting input end Pd, and SR is latched
The Q' ends output of device is output to the decimal add subtraction meter of lowest order with counting clock A_CLK by another NAND gate and non-post
Count device adds counting input end Pu, so, and the signal of the Q ends output of S/R latch is that dutycycle is proportional to amplitude set value
Amplitude control PWM ripples CA.
3. heavy current pulse signal source according to claim 1, it is characterised in that the pulse-width control signal generation circuit
Decimal add subtraction count device including four cascades is that the output end Cd that borrows of lowest order counts defeated with high one subtract respectively
Enter to hold Pd connections, d type flip flop FF1, d type flip flop FF2 and two NAND gates；D type flip flop FF1 clock end CK believes as triggering
Number input, D ends are that D1 meets+5V, and Q ends are the D ends i.e. D2 that Q1 is output to d type flip flop FF2；D type flip flop FF2 clock end CK
It is connected with the output end Cd that borrows of highest order decimal add subtraction count device；The d type flip flop FF1 output of Q ends and d type flip flop FF2
Q' ends be two inputs of the Q2' outputs as the input of NAND gate, the NAND gate output signal is pulse-width control signal
Cw；
D type flip flop FF1 Q ends are two inputs that Q1 outputs are inputted with 100KHz pulse signals as another NAND gate, should
What NAND gate output was connected to lowest order decimal add subtraction count device subtracts counting input end Pd；Each decimal add subtraction count
The setting value input of device is that D0~D3 is connected with the code value output end of 8421 toggle switch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710556258.3A CN107332542B (en) | 2017-07-10 | 2017-07-10 | A kind of heavy current pulse signal source |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710556258.3A CN107332542B (en) | 2017-07-10 | 2017-07-10 | A kind of heavy current pulse signal source |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107332542A true CN107332542A (en) | 2017-11-07 |
| CN107332542B CN107332542B (en) | 2019-08-20 |
Family
ID=60197345
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710556258.3A Expired - Fee Related CN107332542B (en) | 2017-07-10 | 2017-07-10 | A kind of heavy current pulse signal source |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107332542B (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109120170A (en) * | 2018-10-19 | 2019-01-01 | 连云港杰瑞电子有限公司 | A kind of adjustable inversion sine wave source of small-power electric voltage frequency |
| CN110022148A (en) * | 2019-04-23 | 2019-07-16 | 中国电子科技集团公司第四十三研究所 | Three multilevel digital signal modulation circuits of one kind and modulator approach |
| CN110048712A (en) * | 2019-05-17 | 2019-07-23 | 湖北京邦科技有限公司 | Pulse generating device and chip including the pulse generating device |
| CN111799648A (en) * | 2020-07-23 | 2020-10-20 | 哈尔滨理工大学 | Low-temperature drift driving circuit of current tuning semiconductor laser |
| CN112865787A (en) * | 2021-02-15 | 2021-05-28 | 北京瑞尔天天科技有限公司 | High-precision and high-stability pulse counting circuit |
| CN114285315A (en) * | 2021-12-30 | 2022-04-05 | 吉林大学 | Pulse current generation module |
| CN114285317A (en) * | 2021-12-30 | 2022-04-05 | 吉林大学 | High-stability pulse current generation circuit |
| WO2023159666A1 (en) * | 2022-02-22 | 2023-08-31 | 华中科技大学 | Waveform-programmable ultra-high-speed pulse current generation apparatus |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101295872A (en) * | 2007-04-28 | 2008-10-29 | 昂宝电子（上海）有限公司 | System and method for providing overcurrent and overpower protection for power converter |
| CN101567519A (en) * | 2009-05-27 | 2009-10-28 | 北京国科世纪激光技术有限公司 | Large-current pulse LD laser driving power supply |
| CN202094854U (en) * | 2011-02-28 | 2011-12-28 | 南京新联电讯仪器有限公司 | Digital display pulse signal generator |
| CN103117735A (en) * | 2013-01-31 | 2013-05-22 | 杭州电子科技大学 | Periodic pulse width/voltage signal multifunctional precise converting switch |
| CN204316474U (en) * | 2014-12-27 | 2015-05-06 | 芜湖国睿兆伏电子有限公司 | For the pwm circuit of Switching Power Supply remote control benchmark |
-
2017
- 2017-07-10 CN CN201710556258.3A patent/CN107332542B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101295872A (en) * | 2007-04-28 | 2008-10-29 | 昂宝电子（上海）有限公司 | System and method for providing overcurrent and overpower protection for power converter |
| CN101567519A (en) * | 2009-05-27 | 2009-10-28 | 北京国科世纪激光技术有限公司 | Large-current pulse LD laser driving power supply |
| CN202094854U (en) * | 2011-02-28 | 2011-12-28 | 南京新联电讯仪器有限公司 | Digital display pulse signal generator |
| CN103117735A (en) * | 2013-01-31 | 2013-05-22 | 杭州电子科技大学 | Periodic pulse width/voltage signal multifunctional precise converting switch |
| CN204316474U (en) * | 2014-12-27 | 2015-05-06 | 芜湖国睿兆伏电子有限公司 | For the pwm circuit of Switching Power Supply remote control benchmark |
Non-Patent Citations (1)
| Title |
|---|
| 史新建 等: "大电流脉冲恒流源***设计", 《科学技术与工程》 * |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109120170B (en) * | 2018-10-19 | 2020-09-01 | 连云港杰瑞电子有限公司 | Low-power voltage frequency-adjustable inversion sine wave signal source |
| CN109120170A (en) * | 2018-10-19 | 2019-01-01 | 连云港杰瑞电子有限公司 | A kind of adjustable inversion sine wave source of small-power electric voltage frequency |
| CN110022148B (en) * | 2019-04-23 | 2023-10-24 | 中国电子科技集团公司第四十三研究所 | Three-level digital signal modulation circuit and modulation method |
| CN110022148A (en) * | 2019-04-23 | 2019-07-16 | 中国电子科技集团公司第四十三研究所 | Three multilevel digital signal modulation circuits of one kind and modulator approach |
| CN110048712A (en) * | 2019-05-17 | 2019-07-23 | 湖北京邦科技有限公司 | Pulse generating device and chip including the pulse generating device |
| CN111799648A (en) * | 2020-07-23 | 2020-10-20 | 哈尔滨理工大学 | Low-temperature drift driving circuit of current tuning semiconductor laser |
| CN112865787A (en) * | 2021-02-15 | 2021-05-28 | 北京瑞尔天天科技有限公司 | High-precision and high-stability pulse counting circuit |
| CN112865787B (en) * | 2021-02-15 | 2024-06-07 | 北京瑞尔天天科技有限公司 | High-precision and high-stability pulse counting circuit |
| CN114285315A (en) * | 2021-12-30 | 2022-04-05 | 吉林大学 | Pulse current generation module |
| CN114285315B (en) * | 2021-12-30 | 2023-09-05 | 吉林大学 | Pulse current generation module |
| CN114285317B (en) * | 2021-12-30 | 2023-09-15 | 吉林大学 | High-stability pulse current generation circuit |
| CN114285317A (en) * | 2021-12-30 | 2022-04-05 | 吉林大学 | High-stability pulse current generation circuit |
| WO2023159666A1 (en) * | 2022-02-22 | 2023-08-31 | 华中科技大学 | Waveform-programmable ultra-high-speed pulse current generation apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107332542B (en) | 2019-08-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107332542B (en) | A kind of heavy current pulse signal source | |
| CN103219705B (en) | The short-circuit protection method of half bridge resonant transformer and device | |
| CN107154723B (en) | A kind of Constant Current Control System of flyback power supply CCM and DCM mode | |
| CN103852637B (en) | Intelligent electric meter with fundamental wave metering function and measurement method thereof | |
| CN105514938A (en) | Overcurrent protection method and overcurrent protection circuit for direct current frequency conversion driver | |
| CN107167747A (en) | The monitoring device and method of CCM buck converter inductance and output capacitance | |
| CN202034765U (en) | Switch power source short circuit protection circuit | |
| CN105553255B (en) | A kind of constant service time method for controlling frequency conversion for Switching capacitors | |
| CN109587882A (en) | Eliminate LED drive circuit, driving device and the driving method for powering on flashing | |
| CN105467333A (en) | Switching power supply no-load detection circuit and detection method | |
| DE19754126A1 (en) | Circuit arrangement for controlling an electrical drive unit | |
| CN105871189B (en) | A kind of over-current detection circuit | |
| CN108809069A (en) | A kind of monocycle peak current limit circuit | |
| CN207248982U (en) | A kind of burst pulse voltage sampling circuit | |
| CN110676806B (en) | Overcurrent protection circuit of direct current electronic contactor | |
| CN107346947B (en) | Inverter control circuit with constant pulse width output and operation mode thereof | |
| CN205811853U (en) | A kind of switch converters non-linear modulation voltage mode control device | |
| CN202948357U (en) | Constant-current constant-power implementation circuit | |
| CN211530731U (en) | Switch converter cycle-by-cycle overcurrent detection circuit based on D-type trigger | |
| CN204538649U (en) | A kind of output protection circuit | |
| CN201336629Y (en) | Dynamic braking unit of frequency converter | |
| CN101752878B (en) | Digit type fast and accurate self-synchronous parallel operation control method of electric generator | |
| CN203206213U (en) | A frequency divider | |
| CN201955363U (en) | Pulse width adjustable current generation and detection circuit | |
| CN206629001U (en) | A kind of DC motor speed drive system based on TMS320F2812 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20190820 |