CN214702570U - Pressure sensor - Google Patents

Abstract

The utility model relates to a pressure sensor, pressure sensor include substrate structure and top layer structure, the top layer structure includes the first silicon layer, locate the first insulating layer at the first silicon layer back, locate the piezoresistive layer at the first insulating layer back, locate the first lower insulating layer of top layer in the front of the first silicon layer, form in the positive thick semiconductor material layer of the first lower insulating layer of top layer and wrap up the second lower insulating layer of top layer of thick semiconductor material layer; the first silicon layer serves as a pressure sensitive membrane; the thick semiconductor material layer is used as an island structure; the piezoresistive layer comprises at least one piezoresistive layer; the upper surface of the substrate structure is recessed downwards to form a bonding groove, and the thick semiconductor material layer is bonded in the bonding groove and forms a gap with the bonding groove. The pressure sensor forms a thick semiconductor material layer used as an island structure on the front surface of the first silicon layer, so that the purposes of effectively controlling the thickness consistency and the plane size consistency of the pressure sensitive film are achieved.

Description

Pressure sensor

Technical Field

The utility model relates to a pressure sensor technical field especially relates to a pressure sensor.

Background

With the rise of industries such as the internet of things, MEMS (Micro electro Mechanical Systems) sensors have a huge application prospect due to the advantages of small size, low power consumption, light weight, fast response and the like. In particular, MEMS pressure sensors have great application in the fields of automotive electronics, consumer products, industrial control and the like.

The traditional MEMS pressure sensor is mainly based on the traditional single-layer SOI wafer, a back-side wet etching scheme is adopted to etch a sensitive film and a back island structure, and the thickness of the sensitive film is determined by the etching rate and the etching time of the wet etching. However, the wet etching of silicon is usually performed by heating (85 ℃) KOH solution or TMAH solution, and during the heating process, due to the evaporation of water and the reaction between the etching solution and silicon, the concentration of KOH or TMAH solution changes with the duration of the reaction, so it is difficult to precisely control the etching depth. Meanwhile, due to the anisotropy of silicon, when a silicon substrate is subjected to wet etching from the back by using KOH or TMAH, a pattern with a trapezoidal cross section is inevitably generated by the opening pattern, wherein the pattern is small at the top and large at the bottom. This makes the planar size of the product itself much larger than the planar size of the pressure-sensitive membrane actually required, and the product is difficult to miniaturize.

In order to avoid the problem of size increase caused by anisotropic wet etching of silicon, a dry etching technique of silicon based on a conventional single-layer SOI wafer is adopted in the prior art. Theoretically, the deep reactive ion etching of silicon can enable the side of an etched pattern to be close to 90 degrees, so that the plane size of the opening of a chip can be reduced, and the problem of overlarge back corrosion opening is avoided. However, in the actual process, the deep reactive ion etching of silicon hardly ensures the consistency of the etching angle, and the etching precision of 82-92 degrees can be generally ensured in the 8-inch wafer industry. In consideration of lateral etching and other problems, deep reactive ion etching of silicon is adopted, and the problems of alignment and etching compensation of the top-layer piezoresistive structure and the back island are complicated. Theoretically, only the piezoresistive structure is aligned with the boundary (stress concentration position) of the back island, the performance (such as sensitivity, nonlinearity, pressure overload resistance and the like) of the pressure sensor can be guaranteed, and once deviation exists, the performance change of the pressure sensor can generate great deviation from the designed value. In addition, as the traditional single-layer SOI wafer is adopted, the etching depth is still determined by the etching rate and the etching time, and the consistency of the etching depth is low.

In order to solve the problems, in the prior art, a double-layer SOI wafer (DSOI) is adopted for back etching to manufacture the pressure sensor, and during back deep reactive ion etching, the etching can be automatically stopped at a silicon oxide position by utilizing the high selection ratio of silicon and silicon oxide, so that the problem of etching depth consistency can be relatively well solved. However, the etched charged ions will be concentrated at the silicon oxide, and as the etching time increases, a significant lateral etching effect (also called a floating effect) will be generated at the bottom of the etching, thereby affecting the plane size of the sensitive film of the pressure sensor, the position alignment of the top layer piezoresistance and the back island, and the like. Further, since the back surface etching is adopted, the problem of lateral dimensional variation due to angular variation of the deep reactive ion etching side cannot be solved (even if the etching is 500um, even if the angular variation is 1 °, the lateral variation of 500um × tan1 ° -9 um occurs).

SUMMERY OF THE UTILITY MODEL

Based on this, the utility model provides a pressure sensor forms the thick semiconductor material layer that is used as island structure in the front of first silicon layer, reaches the purpose of the thickness uniformity and the plane size uniformity of effective control pressure sensitive membrane.

A pressure sensor comprises a substrate structure and a top layer structure, wherein the top layer structure comprises a first silicon layer, a first insulating layer arranged on the back surface of the first silicon layer, a piezoresistive layer arranged on the back surface of the first insulating layer, a top layer first lower insulating layer arranged on the front surface of the first silicon layer, a thick semiconductor material layer formed on the front surface of the top layer first lower insulating layer and a top layer second lower insulating layer wrapping the thick semiconductor material layer; the first silicon layer serves as a pressure sensitive membrane; the thick semiconductor material layer is used as an island structure; the piezoresistive layer comprises at least one piezoresistive layer;

the upper surface of the substrate structure is sunken downwards to form a bonding groove, and the thick semiconductor material layer is bonded in the bonding groove and forms a gap with the bonding groove.

In the pressure sensor, the thick semiconductor material layer used as the island structure is formed on the front surface of the first silicon layer, and the thick semiconductor material layer is bonded in the bonding groove of the substrate structure and forms a gap with the bonding groove, so that the thickness consistency and the plane size consistency of the pressure sensitive film (namely the first silicon layer) can be effectively controlled, the phenomenon that sealing materials generate air leakage or are pushed away by high pressure can be avoided by utilizing the front surface pressure sensing technology of the pressure sensitive film, meanwhile, the nonlinearity of the pressure sensitive film can be reduced, and the range of measurable pressure can be increased.

In one embodiment, the top layer structure further includes a top insulating layer disposed on a back surface of the first insulating layer and covering the piezoresistive layer, the top insulating layer is provided with a conductive contact hole exposing the piezoresistive layer, and the conductive contact hole is used for exposing a portion of the piezoresistive layer to the top insulating layer;

the pressure sensor also comprises a metal block which is correspondingly arranged at the conductive contact hole and is electrically communicated with the piezoresistive layer.

In one embodiment, each of the piezoresistors is provided with at least one conductive contact hole, and each of the conductive contact holes is provided with at least one metal block.

In one embodiment, the piezoresistors are provided in plurality, and the piezoresistive layer further comprises a conductive connecting line for connecting the plurality of piezoresistors;

and each piezoresistor or each conductive connecting line is correspondingly provided with at least one conductive contact hole, and each conductive contact hole is correspondingly provided with at least one metal block.

In one embodiment, the substrate structure is formed with an air inlet penetrating through the substrate structure, and the air inlet is communicated with the groove bottom of the bonding groove.

Drawings

Fig. 1 is a schematic longitudinal sectional view of a pressure sensor according to an embodiment of the present invention;

fig. 2 to 13 are process flow diagrams of the pressure sensor shown in fig. 1.

Detailed Description

In order to facilitate understanding of the present invention, the present invention will be described more fully hereinafter with reference to the accompanying drawings. The preferred embodiments of the present invention are shown in the drawings. The invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

As shown in fig. 1, a pressure sensor manufactured based on a Double-layer silicon-on-insulator (DSOI) wafer according to an embodiment of the present invention includes: the structure comprises a substrate structure 1 and a top layer structure 2, wherein the top layer structure 2 comprises a first silicon layer 21, a first insulating layer 22 arranged on the back surface of the first silicon layer 21, a piezoresistive layer 231 arranged on the back surface of the first insulating layer 22, a top layer first lower insulating layer 24 arranged on the front surface of the first silicon layer 21, a thick semiconductor material layer 25 formed on the front surface of the top layer first lower insulating layer 24, and a top layer second lower insulating layer 26 covering the thick semiconductor material layer 25; the first silicon layer 21 serves as a pressure sensitive membrane; the thick semiconductor material layer 25 serves as an island structure; the piezoresistive layer 231 includes at least one piezoresistive layer 2311.

The upper surface of the substrate structure 1 is recessed downwards to form a bonding groove 10, and the thick semiconductor material layer 25 is bonded in the bonding groove 10 and forms a gap with the bonding groove.

In the pressure sensor 1, the thick semiconductor material layer 25 used as an island structure is formed on the front surface of the first silicon layer 21, the thick semiconductor material layer 25 is bonded in the bonding groove 10 of the substrate structure 1 and forms a gap with the bonding groove 10, so that the thickness consistency and the plane size consistency of the pressure sensitive film (namely the first silicon layer 21) can be effectively controlled, the phenomenon that sealing materials generate air leakage or are pushed away by high pressure can be avoided by utilizing the front surface pressure sensing technology of the pressure sensitive film, meanwhile, the nonlinearity of the pressure sensitive film can be reduced, and the range of measurable pressure can be increased.

The utility model discloses pressure sensor adopts the DSOI wafer to the first silicon layer 21 of DSOI wafer is as the pressure sensitive membrane, and its thickness uniformity is good. The lateral dimensions of the pressure sensitive membrane are determined by the graphic dimensions of the bonding grooves 10 of the substrate structure 1, which are easy to control compared to the back-side cavity-opening approach of the prior art. In addition, by utilizing the characteristics of the SOI wafer, the piezoresistive structure has no PN junction and can work at high temperature (generally more than 150 ℃).

In one embodiment, as shown in fig. 1, the doping type of the first silicon layer 21 can be freely selected according to actual needs, so that the pressure sensor can improve the stability of the output of the pressure sensor under high temperature (generally, more than 150 degrees), reduce the probability of the failure of the pressure sensor, and enable the pressure sensor to work in an environment with a temperature higher than 150 ℃. In one embodiment, the first silicon layer 21 is doped N-type.

In one embodiment, as shown in FIG. 1, the first insulating layer 22 is a silicon oxide layer.

In one embodiment, as shown in FIG. 1, the layer 25 of conductive semiconductor material is made of a polysilicon material to enable electrical continuity of the internal circuitry of the pressure sensor.

In one embodiment, as shown in fig. 1, the top layer structure 2 further includes a top insulating layer 27 disposed on the back surface of the first insulating layer 22 and covering the piezoresistive layer 231, a conductive contact hole 271 corresponding to the piezoresistive layer 231 is disposed on the top insulating layer 27, and the conductive contact hole 271 is used for partially exposing the piezoresistive layer 231 to the top insulating layer 27. Through the arrangement of the conductive contact hole 271, the pressure sensor is electrified. It should be noted that the number of the conductive contact holes 271 may be one or more.

In one embodiment, as shown in FIG. 1, the pressure sensor further includes a metal block 3 disposed at the conductive contact hole 271 and in electrical communication with the piezoresistive layer 231 to facilitate the energization of the pressure sensor.

In a specific embodiment, as shown in fig. 1, at least one conductive contact hole 271 is correspondingly disposed on each of the piezoresistors 2311, and at least one metal block 3 is correspondingly disposed on each of the conductive contact holes 271.

In the embodiment shown in fig. 1, two piezoresistors 2311 are provided, one conductive contact hole 271 is provided for each piezoresistor 2311, and one metal block 3 is provided for each conductive contact hole 271. The two piezoresistors 2311 are electrically isolated from each other by the upper insulating layer 27 of the top layer and then are complementarily electrically connected by the metal block 3 of the upper layer. At this time, the metal block 3 serves as a connecting line to electrically connect the two piezoresistors 2311 and also provides a function of a wire-bonding wire pad in the following process.

In an embodiment not shown in the drawings, if the piezoresistors are still provided in plurality, the piezoresistive layer further includes a conductive connection line for connecting the piezoresistors, and each of the piezoresistors is provided with at least one conductive contact hole, and each of the conductive contact holes is provided with at least one metal block. At this time, the piezoresistors are connected with each other through a conductive connecting wire, and the subsequent metal block only has the function of wire-bonding routing.

In another embodiment not shown in the drawings, if the piezoresistors are still provided in plurality, the piezoresistive layer further includes a conductive connection line for connecting the piezoresistors, and each conductive connection line is provided with at least one corresponding conductive contact hole, and each conductive contact hole is provided with at least one corresponding metal block. At this time, the piezoresistors are connected with each other through the conductive connecting line, but the conductive connecting line is provided with the metal block, so that the resistance of the conductive connecting line can be further reduced, and finally, the metal block also provides the wire-bonding routing function.

In one embodiment, as shown in fig. 1, the substrate structure 1 includes a central silicon material layer 11 and an upper insulating layer 12 formed on an upper surface of the central silicon material layer 11.

In one embodiment, as shown in fig. 1, for a pressure sensor requiring gauge pressure or differential pressure, a gas inlet 100 penetrating through the substrate structure 1 may be formed on the substrate structure 1, and the gas inlet 100 is communicated with the groove bottom of the bonding groove 10 to meet the structural requirement of the pressure sensor requiring gauge pressure or differential pressure.

As shown in fig. 2 to 13, a method for manufacturing a pressure sensor according to an embodiment of the present invention includes:

s1, a first silicon wafer a shown in fig. 2 is selected, and a front insulating layer 201 and a back insulating layer 202 are grown on the front and back of the first silicon wafer a, respectively (see fig. 3). As shown in fig. 2, the first silicon wafer a is a Double-SOI (DSOI) wafer having a Double-layer "silicon on insulator" structure, and includes a first silicon layer 21, a first insulating layer 22, a second silicon layer 23, a second insulating layer 28, and a third silicon layer 29, which are sequentially stacked and covered, and a surface of the first silicon layer 21 facing away from the third silicon layer 29 is a front surface of the first silicon layer 21, that is, a front surface of the first silicon wafer a.

Preferably, the first silicon layer 21, the second silicon layer 23 and the third silicon layer 29 are doped with the same type, so that the pressure sensor has improved stability of sensor output under high temperature (generally greater than 150 degrees), the failure probability of the pressure sensor is reduced, and the pressure sensor can operate in an environment with temperature higher than 150 ℃. Furthermore, the doping concentrations and the crystal orientations of the first silicon layer 21, the second silicon layer 23 and the third silicon layer 29 can be freely selected according to actual requirements, and in this embodiment, the first silicon layer 21, the second silicon layer 23 and the third silicon layer 29 are both doped with (100) crystal orientation and N-type.

Further, the first insulating layer 22 and the second insulating layer 28 are both silicon oxide layers.

S2, forming a thick semiconductor material layer 25 (fig. 4) on the front surface of the first silicon layer 21 to serve as an island structure.

Specifically, in step S2, the thick semiconductor material layer 25 is formed by:

first, thick semiconductor materials (as shown in fig. 3), such as epitaxially grown polysilicon materials, are grown on the front and back surfaces of the first silicon wafer a. The thickness of the thick semiconductor material can be tailored to the design requirements of the pressure sensor.

Then, the thick semiconductor material on the back side of the first silicon wafer a is etched away, and the thick semiconductor material on the front side of the first silicon wafer a is patterned to form a thick semiconductor material layer 25 serving as an island structure.

And S3, removing the front surface insulating layer 201 grown in the S1, and regenerating a top layer first lower insulating layer 24 on the front surface of the first silicon wafer a, and regenerating a top layer second lower insulating layer 26 wrapping the thick semiconductor material layer 25 on the front surface of the first silicon wafer a (as shown in FIG. 5), so as to obtain a top layer primary structure. Preferably, the top first lower insulating layer 24 and the top second lower insulating layer 26 are formed of a silicon oxide material.

The top first lower insulating layer 24 is partially contiguous with the top second lower insulating layer 26 to form the entire top lower insulating layer.

And S4, forming a substrate structure 1, wherein the substrate structure 1 is provided with a bonding groove 10.

Specifically, in step S4, the substrate structure 1 is formed by:

first, a second silicon wafer b is selected, and the second silicon wafer b is used as the middle silicon material layer 11, and the substrate insulating layer 101 is formed on the upper surface and the lower surface of the second silicon wafer 11.

Then, the second silicon wafer b and the insulating base layer 101 formed on the upper surface of the second silicon wafer b are patterned to form the bonding grooves 10 (see fig. 6).

Then, the insulating base layer 101 on the upper surface of the second silicon wafer b is removed, and the insulating base layer 12 covering the upper surface 101 of the second silicon wafer b and the inner wall of the bonding groove 10 is regenerated on the upper surface 101 of the second silicon wafer b (as shown in fig. 7), so as to obtain the substrate structure 1.

S5, as shown in fig. 8, inverting the primary structure of the top layer, and bonding the thick semiconductor material layer 25 in the bonding groove 10, wherein a gap is formed between the thick semiconductor material layer 25 and the bonding groove 10.

And S6, removing the redundant layer structure.

Specifically, in step S6, the removing the unnecessary layer structure includes:

removing the back insulating layer 202, the third silicon layer 29 and the second insulating layer 28 of the top primary structure; the insulating base layer 101 formed on the lower surface of the second silicon wafer b is removed (see fig. 9).

S7, doping the second silicon layer 23 (as shown in fig. 10), and patterning the doped second silicon layer 23 to form a piezoresistive layer 231, where the piezoresistive layer 231 is formed with at least one piezoresistive 2311, so as to obtain a top layer structure 2 (as shown in fig. 11).

The doping elements, concentrations and doping processes of the second silicon layer 23 may be selected according to the requirements, and typically, a boron ion implantation is performed, and the second silicon layer 22 is uniformly doped by using a high temperature annealing method, wherein the doping concentration is greater than 1E20cm^-3。

In one embodiment, in S7, after the forming the piezoresistive layer 231, the method includes:

first, an upper top insulating layer 27 is deposited on the back of the first insulating layer 22 to cover the piezoresistive layer 231. The piezoresistive layer 231 is protected by depositing a top-layer upper insulating layer 27 on the back of the first insulating layer 22. Preferably, the top insulating layer 27 is formed by Plasma Enhanced Chemical Vapor Deposition (PECVD) of silicon oxide.

Then, patterning the insulating layer 27 on the top layer to form a conductive contact hole 271; the conductive contact hole 271 is used for exposing the piezoresistive layer 231 to the upper insulating layer 27, so as to electrify the pressure sensor.

After the conductive contact hole 271 is formed, a metal block 3 electrically conductive to the piezoresistive layer 231 may be formed at the conductive contact hole 271. Preferably, the metal block 3 may be formed by depositing and patterning a high temperature resistant conductive metal Pad.

Preferably, each of the piezoresistors 2311 is correspondingly formed with at least one of the conductive contact holes 271, and each of the conductive contact holes 271 is correspondingly formed with at least one of the metal blocks 3.

In other embodiments not shown in the drawings, if the piezoresistors are provided in plurality, the piezoresistive layer may be further formed with a conductive connection line for connecting the plurality of piezoresistors in S7. At least one conductive contact hole is correspondingly formed on each piezoresistor or each conductive connecting line, and at least one metal block is correspondingly formed on each conductive contact hole.

If the conductive contact hole is formed corresponding to the piezoresistance, the metal block only has the function of wire-bonding routing pad. If the conductive contact hole is formed corresponding to the conductive connection line, the resistance of the conductive connection line can be further reduced, and meanwhile, the metal block also has the function of wire-bonding routing pad.

And S8, obtaining the pressure sensor.

It should be noted that, in the actual production process, the completion of the above steps S1-S8 is used to obtain an absolute pressure type pressure sensor.

In the actual production process, if a gauge pressure or differential pressure type pressure sensor is required. Then the following steps need only be added after said S7:

an air inlet 100 penetrating through the substrate structure 1 is formed on the substrate structure 1, and the air inlet 100 is communicated with the groove bottom of the bonding groove 10.

Specifically, the gas inlet 100 formed through the substrate structure 1 includes:

first, deep reactive ions of silicon are used to etch the first via hole 110 on the middle silicon material layer 11, and the etching is stopped on the bottom surface of the insulating layer 12 on the substrate by using the self-stop principle (see fig. 12).

Then, the position of the insulating layer 12 on the substrate corresponding to the first through hole 110 is removed to form a second through hole 120, and the first through hole 110 is communicated with the second through hole 120 to obtain the gas inlet 100 (as shown in fig. 13).

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above examples only represent preferred embodiments of the present invention, which are described in more detail and detail, but are not to be construed as limiting the scope of the invention. It should be noted that, for those skilled in the art, without departing from the spirit of the present invention, several variations and modifications can be made, which are within the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the appended claims.

Claims (5)

1. A pressure sensor, characterized by: the structure comprises a substrate structure and a top layer structure, wherein the top layer structure comprises a first silicon layer, a first insulating layer arranged on the back surface of the first silicon layer, a piezoresistive layer arranged on the back surface of the first insulating layer, a top layer first lower insulating layer arranged on the front surface of the first silicon layer, a thick semiconductor material layer formed on the front surface of the top layer first lower insulating layer and a top layer second lower insulating layer coating the thick semiconductor material layer; the first silicon layer serves as a pressure sensitive membrane; the thick semiconductor material layer is used as an island structure; the piezoresistive layer comprises at least one piezoresistive layer;

the upper surface of the substrate structure is sunken downwards to form a bonding groove, and the thick semiconductor material layer is bonded in the bonding groove and forms a gap with the bonding groove.

2. The pressure sensor of claim 1, wherein: the top layer structure further comprises a top layer upper insulating layer which is arranged on the back surface of the first insulating layer and wraps the piezoresistive layer, a conductive contact hole corresponding to the piezoresistive layer is formed in the top layer upper insulating layer, and the conductive contact hole is used for enabling the piezoresistive layer to be partially exposed out of the top layer upper insulating layer;

the pressure sensor also comprises a metal block which is correspondingly arranged at the conductive contact hole and is electrically communicated with the piezoresistor.

3. The pressure sensor of claim 2, wherein: each piezoresistor is correspondingly provided with at least one conductive contact hole, and each conductive contact hole is correspondingly provided with at least one metal block.

4. The pressure sensor of claim 2, wherein: the piezoresistors are provided in plurality, and the piezoresistor layer further comprises a conductive connecting wire for connecting the piezoresistors;

and each piezoresistor or each conductive connecting line is correspondingly provided with at least one conductive contact hole, and each conductive contact hole is correspondingly provided with at least one metal block.

5. The pressure sensor of claim 1, wherein: the air inlet penetrating through the substrate structure is formed in the substrate structure and communicated with the groove bottom of the bonding groove.

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