CN214588824U

CN214588824U - Novel semiconductor device packaging structure

Info

Publication number: CN214588824U
Application number: CN202120818616.5U
Authority: CN
Inventors: 潘波; 辜睿智
Original assignee: Chengdu Scilicon Electric Co ltd
Current assignee: Chengdu Scilicon Electric Co ltd
Priority date: 2021-04-20
Filing date: 2021-04-20
Publication date: 2021-11-02
Anticipated expiration: 2031-04-20

Abstract

The utility model discloses a novel semiconductor device packaging structure, which comprises a semiconductor device and a plastic package layer, wherein the semiconductor device is sequentially provided with a copper substrate layer, a heat conduction insulating layer, a PCB (printed Circuit Board) layer and a chip layer from top to bottom, and the semiconductor device is placed in the plastic package layer; a plurality of pins are arranged on the left side and the right side of the copper substrate layer; the plastic packaging layer is provided with the temperature measuring hole, and by means of the mode, the problems that a single tube scheme is difficult in structural design, high in failure rate, large in parasitic parameter, poor in heat dissipation, large in thermal resistance, low in overcurrent capacity and the like can be effectively solved.

Description

Novel semiconductor device packaging structure

Technical Field

The utility model relates to a semiconductor device field, concretely relates to novel semiconductor device packaging structure.

Background

The existing module has large volume and low power density, and the performance of a device cannot be fully exerted because the temperature of a chip cannot be accurately measured; the module has the advantages of small volume, high power density, low parasitic parameter, low thermal resistance and flexible scheme design.

SUMMERY OF THE UTILITY MODEL

To the above-mentioned not enough among the prior art, the utility model provides a novel semiconductor device packaging structure.

In order to achieve the above object, the utility model adopts the following technical scheme:

a novel semiconductor device packaging structure comprises a semiconductor device and a plastic packaging layer, wherein the semiconductor device comprises a copper substrate layer, a heat conduction insulating layer, a PCB (printed Circuit Board) layer and a chip layer from top to bottom in sequence, and the semiconductor device is placed in the plastic packaging layer;

a plurality of pins are arranged on the left side and the right side of the copper substrate layer;

and the plastic packaging layer is provided with a temperature measuring hole.

The technical scheme has the advantages that the chip in the single tube is integrated into one device by utilizing the packaging, so that the cost is reduced, the reliability is improved, the parasitic parameter is reduced, and the thermal resistance is reduced.

Furthermore, the plastic package layer is a groove with an opening at the top end, and the length and width of the groove are the same as those of the semiconductor device.

The further scheme has the beneficial effect that the semiconductor device is fixed in the plastic package layer.

Further, the height of the side wall of the groove is the same as the height of the semiconductor device.

The beneficial effect of the further scheme is that the copper substrate layer of the semiconductor device can be well contacted with the radiator.

Furthermore, mounting holes from top to bottom are formed in the side walls of the grooves on the front side and the rear side of the plastic packaging layer.

The beneficial effect of the above-mentioned further scheme is that a plurality of mounting means are provided.

Further, the temperature measuring hole penetrates through the bottom surface of the plastic packaging layer to the chip layer.

The beneficial effect of above-mentioned further scheme is that, the outside temperature measurement equipment of being convenient for can carry out direct temperature measurement to inside chip or PCB board.

Furthermore, one surface of the chip layer is welded on the PCB layer, and the other surface of the chip layer is closely attached to the bottom surface of the plastic packaging layer.

The beneficial effect of the above-mentioned further scheme is, utilize PCB sheet layer overcurrent, memory chip's heat and spread the heat of chip and derive the heat.

Furthermore, the pins are welded on the PCB layer and penetrate through the left side wall and the right side wall of the plastic packaging layer to be bent downwards.

The beneficial effect of above-mentioned further scheme is that, the pin all adopts welded mode to fix on PCB, effectively reduces contact resistance, increases the ability of overflowing, reduces and generates heat.

Furthermore, the lower surface of the heat conduction insulating layer is closely attached to the upper surface of the PCB layer, and the upper surface of the heat conduction insulating layer is closely attached to the lower surface of the copper substrate layer.

Further, the heat conducting insulating layer is made of one of aluminum oxide, silicon nitride or silicon carbide.

The beneficial effects of the above-mentioned further scheme are that, utilize heat conduction insulating material to carry out electrical insulation to upper and lower layer, transmit the heat that the chip gave out simultaneously to, transmit the radiator through the copper substrate layer.

Furthermore, the upper surface of the copper substrate layer is closely attached to the radiator, and the contact surface of the copper substrate layer and the radiator is coated with heat-conducting silicone grease.

The beneficial effect of the further scheme is that the heat radiator is used for carrying out centralized heat management on the semiconductor device.

Drawings

Fig. 1 is a front view of the semiconductor device package structure of the present invention.

Fig. 2 is a schematic view of the bottom structure of the semiconductor device package structure of the present invention.

Fig. 3 is a top schematic view of the semiconductor device package structure of the present invention.

Description of reference numerals: 1. a plastic packaging layer; 2. a chip layer; 3. a PCB board layer; 4. a thermally conductive insulating layer; 5. a copper substrate layer; 6. a pin; 7. a temperature measuring hole; 8. and (7) installing holes.

Detailed Description

The following description of the embodiments of the present invention is provided to facilitate the understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and various changes may be made apparent to those skilled in the art within the spirit and scope of the present invention as defined and defined by the appended claims.

A novel semiconductor device packaging structure is shown in figures 1-3 and comprises a semiconductor device and a plastic packaging layer 1, wherein the semiconductor device comprises a copper substrate layer 5, a heat conduction insulating layer 4, a PCB (printed circuit board) layer 3 and a chip layer 2 from top to bottom in sequence, and the semiconductor device is placed in the plastic packaging layer 1;

a plurality of pins 6 are arranged on the left side and the right side of the copper substrate layer 5;

the plastic package layer 1 is provided with a temperature measuring hole 7.

Further, the plastic package layer 1 is a groove with an opening at the top end, the size of the groove is the same as that of the semiconductor device, and the plastic package layer 1 can adopt epoxy resin to plastically package the semiconductor device for fixing each device.

Furthermore, the height of the side wall of the groove is the same as that of the semiconductor device, and when the upper surface of the packaging structure is in contact with a radiator, poor contact caused by too high plastic packaging material can be effectively avoided, so that poor radiating effect is caused.

Further, the mounting holes 8 are formed in the groove side walls of the front side and the rear side of the plastic package layer 1 from top to bottom, the connection between the packaging structure and the radiator can be changed in a screw locking mode, the module is fixed on the radiator through the mounting holes 8, and meanwhile, the copper substrate layer 5 can be welded on the radiator through a metal welding process.

Further, copper substrate layer 5, heat conduction insulating layer 4 and PCB sheet layer 3 constitute the DBC structure jointly, and heat conduction insulating layer 4 is used for DBC upper and lower layer electrical insulation and passes to the heat of lower floor's chip, in this embodiment, should consider to select for use insulating material that coefficient of heat conductivity is big and heat capacity is big, such as aluminium oxide, silicon nitride or carborundum.

Further, the temperature measuring hole 7 penetrates through the bottom surface of the plastic package layer 1 to the chip layer 2, the position of the temperature measuring hole 7 should be away from the position where the temperature of the semiconductor device is highest, and the position where the heat productivity of the chip layer 2 and the PCB layer 3 is maximum, in this embodiment, the temperature measuring hole is arranged on the center line of the bottom plate of the plastic package layer 1 and is away from the center of the bottom plate by 6.3 mm.

Furthermore, the chip layer 2 is welded on the PCB layer 3, so that the PCB layer 3 has the characteristics of strong overcurrent capacity and uniformity, and can quickly diffuse heat, so that the heat diffusion is quicker, and the thermal resistance of a system is lower.

Further, pins 6 are welded and fixed on PCB sheet layer 3, and a plurality of pins 6 pass and wrap up behind the 1 lateral wall of plastic envelope layer all around PCB sheet layer 3 and bend downwards, effectively reduce contact resistance, increase the ability of overflowing, reduce and generate heat.

Furthermore, the upper surface of the copper substrate layer 5 is attached to the heat sink, in this embodiment, the copper substrate layer 5 may be welded to the heat sink by a welding method, or may be locked to the heat sink by installing screws in the mounting holes 8, and the contact surface between the copper substrate layer 5 and the heat sink may be butcher heat-conductive silicone grease as the heat-conductive material.

In this embodiment, the heat sink may be an independent heat sink or a cold plate, and may perform centralized thermal management on the semiconductor device. In this embodiment, the heat sink may be an independent heat sink or a cold plate, and may perform centralized thermal management on the semiconductor device.

It will be appreciated by those of ordinary skill in the art that the embodiments described herein are intended to assist the reader in understanding the principles of the invention, and it is to be understood that the scope of the invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific modifications and combinations based on the teachings of the present invention without departing from the spirit of the invention, and such modifications and combinations are still within the scope of the invention.

Claims

1. The novel semiconductor device packaging structure is characterized by comprising a semiconductor device and a plastic packaging layer (1), wherein the semiconductor device comprises a copper substrate layer (5), a heat conduction insulating layer (4), a PCB (printed circuit board) layer (3) and a chip layer (2) from top to bottom in sequence, and the semiconductor device is placed in the plastic packaging layer (1);

a plurality of pins (6) are arranged on the left side and the right side of the copper substrate layer (5);

the plastic packaging layer (1) is provided with a temperature measuring hole (7).

2. The novel semiconductor device packaging structure according to claim 1, wherein the molding layer (1) is a groove with an opening at the top end, and the length and width dimensions of the groove are the same as those of the semiconductor device.

3. The novel semiconductor device package structure of claim 2, wherein the height of the sidewall of the recess is the same as the height of the semiconductor device.

4. The novel semiconductor device package structure of claim 3, wherein the side walls of the grooves on the front and back sides of the plastic package layer (1) are provided with mounting holes (8) from top to bottom.

5. The novel semiconductor device package structure according to claim 1, wherein the temperature measuring hole (7) penetrates through the bottom surface of the molding compound layer (1) to the chip layer (2).

6. The novel semiconductor device package structure of claim 1, wherein the upper surface of the chip layer (2) is soldered to the bottom surface of the groove of the plastic package layer (1) and the upper and lower surfaces of the PCB layer (3) are closely attached to the bottom surface of the groove.

7. The novel semiconductor device package structure of claim 6, wherein the plurality of leads (6) are soldered on the PCB board layer (3), and the plurality of leads (6) are bent downward after passing through the left and right side walls of the molding layer (1).

8. The novel semiconductor device package structure of claim 1, wherein the lower surface of the thermally conductive and insulating layer (4) is attached to the upper surface of the PCB board layer (3) and the upper surface is attached to the lower surface of the copper substrate layer (5).

9. The novel semiconductor device package structure of claim 8, wherein the thermally conductive and insulating layer (4) is made of one of aluminum oxide, silicon nitride or silicon carbide.

10. The novel semiconductor device package structure of claim 1, wherein the upper surface of the copper substrate layer (5) is closely attached to the heat sink, and the contact surface of the copper substrate layer (5) and the heat sink is coated with a heat conductive silicone grease.