CN214411209U - Power metal oxide semiconductor field effect transistor - Google Patents
Power metal oxide semiconductor field effect transistor Download PDFInfo
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- CN214411209U CN214411209U CN202120432684.8U CN202120432684U CN214411209U CN 214411209 U CN214411209 U CN 214411209U CN 202120432684 U CN202120432684 U CN 202120432684U CN 214411209 U CN214411209 U CN 214411209U
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Abstract
The utility model discloses a power metal oxide semiconductor field effect transistor, including N type epitaxial layer that is arranged in the silicon carbide substrate, the light doping P type well layer that is arranged in upper portion among the N type epitaxial layer, the light doping P type well layer is provided with first heavy doping N type source region, second heavy doping N type source region on the upper portion interval that is arranged in region between first slot, the second slot, the contact surface of first heavy doping N type source region, second heavy doping N type source region and light doping P type well layer is the arcwall face; the left side surface and the right side surface of the heavily doped P-type region are respectively contacted with partial areas of arc surfaces of a first heavily doped N-type source region and a second heavily doped N-type source region, the contact surface of the heavily doped P-type region and a lightly doped P-type well layer is an arc surface protruding downwards, and the contact surface of the lightly doped P-type well layer and an N-type epitaxial layer is an arc surface protruding downwards. The utility model discloses the transistor makes the electric field more even, has improved the withstand voltage ability of power MOS device.
Description
Technical Field
The present invention relates to a power mosfet, and more particularly to a power mosfet.
Background
The trench power MOS device is developed on the basis of a planar power MOS device. Compared with a planar power MOS device, the planar power MOS device has the advantages of low on-resistance, low saturation voltage, high switching speed, high channel density, small chip size and the like; the groove type structure is adopted, and the parasitic JFET (junction field effect transistor) effect existing in the planar power MOS device is eliminated. At present, deep trench power MOS devices have been developed to become the mainstream of middle-low voltage high-power MOS devices. However, the conventional trench high-power MOS device still has many technical problems to be improved.
Disclosure of Invention
The utility model provides a power metal oxide semiconductor field effect transistor, this power metal oxide semiconductor field effect transistor make the electric field more even, have improved the withstand voltage ability of power MOS device.
In order to achieve the above purpose, the utility model adopts the technical scheme that: a power metal oxide semiconductor field effect transistor comprises an N-type epitaxial layer located in a silicon carbide substrate, and a lightly doped P-type well layer located at the middle upper part of the N-type epitaxial layer, wherein a first groove and a second groove are formed in the lightly doped P-type well layer at intervals, the first groove and the second groove located in the lightly doped P-type well layer extend into the N-type epitaxial layer from the upper surface of the lightly doped P-type well layer, a gate polycrystalline silicon part is arranged in each of the first groove and the second groove, and the first groove and the second groove are respectively isolated from the gate polycrystalline silicon parts through a gate oxide layer;
the lightly doped P-type well layer is positioned at the upper part of a region between the first groove and the second groove and is provided with a first heavily doped N-type source region and a second heavily doped N-type source region at intervals, the first heavily doped N-type source region and the second heavily doped N-type source region are respectively positioned at the periphery of the first groove and the periphery of the second groove, and the contact surfaces of the first heavily doped N-type source region, the second heavily doped N-type source region and the lightly doped P-type well layer are arc surfaces;
the light-doped P-type well layer is provided with a light-doped P-type region in a region between a first light-doped N-type source region and a second light-doped N-type source region, the upper surface of the light-doped P-type region is positioned on the upper surface of the light-doped P-type well layer in the vertical direction, the lower surface of the light-doped P-type region extends to the middle of the light-doped P-type well layer, the left side surface and the right side surface of the light-doped P-type region are respectively contacted with partial regions of arc surfaces of the first light-doped N-type source region and the second light-doped N-type source region in the horizontal direction, the contact surface of the light-doped P-type region and the light-doped P-type well layer is an arc surface protruding downwards, and the contact surface of the light-doped P-type well layer and the N-type epitaxial layer is an arc surface protruding downwards;
a dielectric layer covers the upper portions of the first groove and the second groove and the upper portions of the first heavily doped N-type source region and the second heavily doped N-type source region close to the grooves, and a metal layer covers the upper portions of the heavily doped P-type region and the upper portions of the first heavily doped N-type source region and the second heavily doped N-type source region far away from the grooves.
The relevant content in the above technical solution is explained as follows:
1. in the above scheme, the depth of each of the first heavily doped N-type source region and the second heavily doped N-type source region is greater than the corresponding width.
2. In the above scheme, the depth ratio of the lightly doped P-type well layer to the heavily doped P-type region is 10: 3 to 5.
3. In the above scheme, the lightly doped P-type well layer is a lightly doped aluminum silicon carbide well layer.
4. In the above scheme, the first heavily doped N-type source region and the second heavily doped N-type source region are heavily doped silicon carbide source regions of phosphorus.
5. In the above scheme, the thickness of the gate oxide layer is 0.03 μm to 0.07 μm.
Because of the application of the technical scheme, compared with the prior art, the utility model has the following advantages:
the utility model discloses power metal oxide semiconductor field effect transistor, it is located first slot, the peripheral first heavily doped N type source region of second slot, the contact surface of second heavily doped N type source region and light doping P type well layer is the arcwall face, heavily doped P type district left and right sides face respectively with first heavily doped N type source region, the partial region contact of the arcwall face separately of second heavily doped N type source region, heavily doped P type district is bellied arcwall face downwards with the contact surface of light doping P type well layer, the contact surface of light doping P type well layer and N type epitaxial layer is bellied arcwall face downwards, it is more even to make the electric field, the withstand voltage ability of power MOS device has been improved.
Drawings
Fig. 1 is a schematic structural diagram of a power mosfet of the present invention.
In the above drawings: 1. an N-type epitaxial layer; 2. a lightly doped P-type well layer; 3. a first trench; 4. a second trench; 5. a gate polysilicon portion; 6. isolating the gate oxide layer; 7. a first heavily doped N-type source region; 8. a second heavily doped N-type source region; 9. heavily doped P-type region; 10. a dielectric layer; 11. a metal layer.
Detailed Description
The invention will be further described with reference to the following examples:
example 1: a power metal oxide semiconductor field effect transistor comprises an N-type epitaxial layer 1 positioned in a silicon carbide substrate, and a lightly doped P-type well layer 2 positioned at the middle upper part of the N-type epitaxial layer 1, wherein a first groove 3 and a second groove 4 are formed in the lightly doped P-type well layer 2 in a spaced mode, the first groove 3 and the second groove 4 positioned in the lightly doped P-type well layer 2 extend into the N-type epitaxial layer 1 from the upper surface of the lightly doped P-type well layer 2, a gate polycrystalline silicon part 5 is arranged in each of the first groove 3 and the second groove 4, and the first groove 3 and the second groove 4 are isolated from the respective gate polycrystalline silicon part 5 through a gate oxide layer 6;
the lightly doped P-type well layer 2 is provided with a first heavily doped N-type source region 7 and a second heavily doped N-type source region 8 at intervals at the upper part of the region between the first groove 3 and the second groove 4, the first heavily doped N-type source region 7 and the second heavily doped N-type source region 8 are respectively arranged at the periphery of the first groove 3 and the second groove 4, and the contact surfaces of the first heavily doped N-type source region 7, the second heavily doped N-type source region 8 and the lightly doped P-type well layer 2 are arc surfaces;
a heavily doped P-type region 9 is arranged in a region, located between the first heavily doped N-type source region 7 and the second heavily doped N-type source region 8, of the lightly doped P-type well layer 2, in the vertical direction, the upper surface of the heavily doped P-type region 9 is located on the upper surface of the lightly doped P-type well layer 2, the lower surface of the heavily doped P-type region 9 extends to the middle of the lightly doped P-type well layer 2, in the horizontal direction, the left side surface and the right side surface of the heavily doped P-type region 9 are respectively in contact with partial regions of arc surfaces of the first heavily doped N-type source region 7 and the second heavily doped N-type source region 8, the contact surface of the heavily doped P-type region 9 and the lightly doped P-type well layer 2 is an arc surface protruding downwards, and the contact surface of the lightly doped P-type well layer 2 and the N-type epitaxial layer 1 is an arc surface protruding downwards;
a dielectric layer 10 covers the first trench 3 and the second trench 4 and the areas of the first heavily doped N-type source region 7 and the second heavily doped N-type source region 8 close to the trenches, and a metal layer 11 covers the heavily doped P-type region 9 and the areas of the first heavily doped N-type source region 7 and the second heavily doped N-type source region 8 far away from the trenches.
The depth ratio of the lightly doped P-type well layer 2 to the heavily doped P-type region 9 is 10: 4.
the lightly doped P-type well layer 2 is a silicon carbide well layer lightly doped with aluminum.
The first heavily doped N-type source region 7 and the second heavily doped N-type source region 8 are heavily doped silicon carbide source regions.
The thickness of the gate oxide layer isolation 6 is 0.06 μm.
Example 2: a power metal oxide semiconductor field effect transistor comprises an N-type epitaxial layer 1 positioned in a silicon carbide substrate, and a lightly doped P-type well layer 2 positioned at the middle upper part of the N-type epitaxial layer 1, wherein a first groove 3 and a second groove 4 are formed in the lightly doped P-type well layer 2 in a spaced mode, the first groove 3 and the second groove 4 positioned in the lightly doped P-type well layer 2 extend into the N-type epitaxial layer 1 from the upper surface of the lightly doped P-type well layer 2, a gate polycrystalline silicon part 5 is arranged in each of the first groove 3 and the second groove 4, and the first groove 3 and the second groove 4 are isolated from the respective gate polycrystalline silicon part 5 through a gate oxide layer 6;
the lightly doped P-type well layer 2 is provided with a first heavily doped N-type source region 7 and a second heavily doped N-type source region 8 at intervals at the upper part of the region between the first groove 3 and the second groove 4, the first heavily doped N-type source region 7 and the second heavily doped N-type source region 8 are respectively arranged at the periphery of the first groove 3 and the second groove 4, and the contact surfaces of the first heavily doped N-type source region 7, the second heavily doped N-type source region 8 and the lightly doped P-type well layer 2 are arc surfaces;
a heavily doped P-type region 9 is arranged in a region, located between the first heavily doped N-type source region 7 and the second heavily doped N-type source region 8, of the lightly doped P-type well layer 2, in the vertical direction, the upper surface of the heavily doped P-type region 9 is located on the upper surface of the lightly doped P-type well layer 2, the lower surface of the heavily doped P-type region 9 extends to the middle of the lightly doped P-type well layer 2, in the horizontal direction, the left side surface and the right side surface of the heavily doped P-type region 9 are respectively in contact with partial regions of arc surfaces of the first heavily doped N-type source region 7 and the second heavily doped N-type source region 8, the contact surface of the heavily doped P-type region 9 and the lightly doped P-type well layer 2 is an arc surface protruding downwards, and the contact surface of the lightly doped P-type well layer 2 and the N-type epitaxial layer 1 is an arc surface protruding downwards;
a dielectric layer 10 covers the first trench 3 and the second trench 4 and the areas of the first heavily doped N-type source region 7 and the second heavily doped N-type source region 8 close to the trenches, and a metal layer 11 covers the heavily doped P-type region 9 and the areas of the first heavily doped N-type source region 7 and the second heavily doped N-type source region 8 far away from the trenches.
The depth dimension of each of the first heavily doped N-type source region 7 and the second heavily doped N-type source region 8 is greater than the corresponding width dimension.
The depth ratio of the lightly doped P-type well layer 2 to the heavily doped P-type region 9 is 10: 4.6.
the lightly doped P-type well layer 2 is a silicon carbide well layer lightly doped with aluminum.
The first heavily doped N-type source region 7 and the second heavily doped N-type source region 8 are heavily doped silicon carbide source regions.
The thickness of the gate oxide isolation 6 is 0.04 μm.
In the embodiment, the lightly doped P-type well layer 2 is a lightly doped aluminum silicon carbide well layer, and is formed by distributing aluminum for 4-5 times, wherein the lightly doped P-type well layer 2 is formed by distributing aluminum in the epitaxial growth of a silicon carbide substrate; forming an oxide layer on the gate oxide layer isolation 6 by dry oxidation at 1200-1400 ℃; the silicon carbide source region heavily doped with phosphorus is formed by distributing phosphorus for 3-4 times; the heavily doped P-type region 9 is formed by distributing aluminum 5-6 times.
When the power metal oxide semiconductor field effect transistor is adopted, the contact surfaces of the first heavily doped N-type source region, the second heavily doped N-type source region and the lightly doped P-type well layer which are positioned at the periphery of the first groove and the second groove are arc-shaped surfaces, the left side surface and the right side surface of the heavily doped P-type region are respectively contacted with the partial regions of the arc-shaped surfaces of the first heavily doped N-type source region and the second heavily doped N-type source region, the contact surface of the heavily doped P-type region and the lightly doped P-type well layer is an arc-shaped surface protruding downwards, the contact surface of the lightly doped P-type well layer and the N-type epitaxial layer is an arc-shaped surface protruding downwards, an electric field is more uniform, and the voltage resistance of a power MOS device is improved.
The above embodiments are only for illustrating the technical concept and features of the present invention, and the purpose of the embodiments is to enable people skilled in the art to understand the contents of the present invention and to implement the present invention, which cannot limit the protection scope of the present invention. All equivalent changes and modifications made according to the spirit of the present invention should be covered by the protection scope of the present invention.
Claims (6)
1. A power mosfet, comprising: the silicon carbide substrate comprises an N-type epitaxial layer (1) positioned in a silicon carbide substrate and a lightly doped P-type well layer (2) positioned on the middle upper part of the N-type epitaxial layer (1), wherein a first groove (3) and a second groove (4) are formed in the lightly doped P-type well layer (2) at intervals, the first groove (3) and the second groove (4) positioned in the lightly doped P-type well layer (2) extend into the N-type epitaxial layer (1) from the upper surface of the lightly doped P-type well layer (2), a gate polycrystalline silicon part (5) is arranged in each of the first groove (3) and the second groove (4), and the first groove (3) and the second groove (4) are isolated from the gate polycrystalline silicon part (5) through a gate oxide layer (6);
the upper part of the lightly doped P-type well layer (2) in the region between the first groove (3) and the second groove (4) is provided with a first heavily doped N-type source region (7) and a second heavily doped N-type source region (8) at intervals, the first heavily doped N-type source region (7) and the second heavily doped N-type source region (8) are respectively arranged at the periphery of the first groove (3) and the periphery of the second groove (4), and the contact surfaces of the first heavily doped N-type source region (7), the second heavily doped N-type source region (8) and the lightly doped P-type well layer (2) are arc surfaces;
a heavily doped P-type region (9) is arranged in the region of the lightly doped P-type well layer (2) between the first heavily doped N-type source region (7) and the second heavily doped N-type source region (8), in the vertical direction, the upper surface of the heavily doped P-type region (9) is positioned on the upper surface of the lightly doped P-type well layer (2), and the lower surface of the heavily doped P-type region (9) extends to the middle part of the lightly doped P-type well layer (2), in the horizontal direction, the left side surface and the right side surface of the heavily doped P-type region (9) are respectively contacted with the partial regions of the respective arc surfaces of the first heavily doped N-type source region (7) and the second heavily doped N-type source region (8), the contact surface of the heavily doped P-type region (9) and the lightly doped P-type well layer (2) is an arc surface which protrudes downwards, the contact surface of the lightly doped P-type well layer (2) and the N-type epitaxial layer (1) is a downward convex arc surface;
a dielectric layer (10) covers the upper portions of the first groove (3) and the second groove (4) and the areas, close to the grooves, of the first heavily doped N-type source area (7) and the second heavily doped N-type source area (8), and a metal layer (11) covers the upper portions of the heavily doped P-type area (9) and the areas, far away from the grooves, of the first heavily doped N-type source area (7) and the second heavily doped N-type source area (8).
2. The power mosfet of claim 1 wherein: the depth dimension of each of the first heavily doped N-type source region (7) and the second heavily doped N-type source region (8) is larger than the corresponding width dimension.
3. The power mosfet of claim 1 wherein: the depth ratio of the lightly doped P-type well layer (2) to the heavily doped P-type region (9) is 10: 3 to 5.
4. The power mosfet of claim 1 wherein: the lightly doped P-type well layer (2) is a lightly doped aluminum silicon carbide well layer.
5. The power mosfet of claim 1 wherein: the first heavily doped N-type source region (7) and the second heavily doped N-type source region (8) are heavily doped silicon carbide source regions of phosphorus.
6. The power mosfet of claim 1 wherein: the thickness of the gate oxide layer isolation (6) is 0.03 μm to 0.07 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120432684.8U CN214411209U (en) | 2021-02-26 | 2021-02-26 | Power metal oxide semiconductor field effect transistor |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202120432684.8U CN214411209U (en) | 2021-02-26 | 2021-02-26 | Power metal oxide semiconductor field effect transistor |
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| CN214411209U true CN214411209U (en) | 2021-10-15 |
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| CN202120432684.8U Active CN214411209U (en) | 2021-02-26 | 2021-02-26 | Power metal oxide semiconductor field effect transistor |
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