CN214279968U - Semiconductor device adopting power half-bridge overlapping sealing scheme and half-bridge circuit module - Google Patents

Abstract

A semiconductor device and a half-bridge circuit module using a power half-bridge stack encapsulation scheme are disclosed, the semiconductor device including a package frame and at least two transistors stacked on a base of the package frame, wherein an upper transistor of two adjacent transistors is disposed in a first open window region of an upper surface of a lower transistor, in which a series or parallel connection is implemented. The utility model discloses a semiconductor device has reduced the demand to the base island quantity of base with the range upon range of setting of at least two transistors on packaging frame's base, is convenient for and ordinary packaging frame is compatible, has reduced the encapsulation cost. The utility model discloses a half-bridge circuit module is with the range upon range of setting of first transistor and second transistor on packaging frame's base, and first transistor and second transistor pass through conducting layer electric connection and establish ties, have reduced the demand to the base island of packaging frame's base, are convenient for and ordinary packaging frame is compatible, have reduced the encapsulation cost.

Description

Semiconductor device adopting power half-bridge overlapping sealing scheme and half-bridge circuit module

Technical Field

The utility model relates to a semiconductor technology field specifically relates to an adopt power half-bridge to fold semiconductor device and half-bridge circuit module of sealing scheme.

Background

In the field of high-voltage high-power supply application, it is a common method to implement various power supply topologies by using a high-voltage MOS (metal-oxide semiconductor) half-bridge and a driving technique thereof.

In reference to fig. 1, a drain terminal of an upper tube M1 is connected to a bus potential V1, a source terminal of a lower tube M2 is connected to a reference potential V2, and a source terminal of the upper tube M1 is connected to a drain terminal of the lower tube M2.

Referring TO the TO252 package structure of fig. 2, most of the NMOS transistors are three-terminal devices, the pins include a source terminal S, a gate terminal G and a drain terminal D, and in a high-voltage (over 500V withstand voltage) MOS half-bridge structure, two required high-voltage NMOS transistors are mostly combined structures of two discrete independent package NMOS transistors, so that the integration level is low, or two independent NMOS transistors are integrated, a specially designed package architecture is required, and the cost is high.

SUMMERY OF THE UTILITY MODEL

In view of the above problems, an object of the present invention is to provide a semiconductor device and a half-bridge circuit module using a power half-bridge stacked package scheme, so as to implement an integrated package of at least two transistors with a conventional package architecture, thereby reducing the integrated package cost of multiple transistors.

According to the utility model discloses an aspect provides an adopt power half-bridge to fold semiconductor device who seals scheme, a serial communication port, include:

a package frame including a base;

at least two transistors stacked on the base, wherein,

an upper surface of a lower transistor of adjacent transistors of the at least two transistors includes a first windowed area including at least one of a source electrode and a drain electrode of the lower transistor;

an upper transistor of adjacent transistors of the at least two transistors is disposed in the first open window region of the lower transistor, and a lower surface of the upper transistor includes at least one of a source electrode and a drain electrode of the upper transistor and is connected in series or in parallel with at least one of the source electrode and the drain electrode of the lower transistor.

Optionally, a transistor of the at least two transistors comprises a vertical double diffused metal oxide semiconductor tube.

Optionally, the at least two transistors comprise:

the transistor comprises a base, a first transistor and a second transistor, wherein the base is provided with a first windowing area and a second windowing area which are separated by an insulating layer, the upper surface of the first transistor comprises a drain electrode, the first windowing area of the first transistor comprises a source electrode of the first transistor, and the second windowing area of the first transistor comprises a gate electrode of the first transistor;

a second transistor disposed on the first window region of the first transistor, an upper surface of the second transistor including the first window region and a second window region separated by an insulating layer, a lower surface of the second transistor including a drain electrode electrically connected to a source electrode of the first transistor, the first window region of the second transistor including a source electrode of the second transistor, the second window region of the second transistor including a gate electrode of the second transistor,

the first transistor and the second transistor are both longitudinal double-diffused metal oxide field effect transistors.

Optionally, a conductive layer is disposed between the first windowing region of the first transistor and the lower surface of the second transistor, and the conductive layer includes conductive adhesive.

Optionally, the first transistor and the second transistor are high voltage transistors.

Optionally, the first transistor and the second transistor are NMOS transistors.

Optionally, an area of the first open window region of the first transistor is larger than an area of a lower surface of the second transistor.

Optionally, the package frame includes:

a first pin electrically connected to a drain electrode of a lower surface of the first transistor;

and the second pin is electrically connected with the source electrode of the first windowing area of the second transistor.

Optionally, the gate electrode of the first transistor and the gate electrode of the second transistor are electrically connected to two leads of the package frame or to the same lead of the package frame, respectively.

According to another aspect of the present invention, there is provided a half-bridge circuit module, comprising:

a package frame including a base;

a first transistor disposed on the base, an upper surface of the first transistor including a first windowed area, the first windowed area including a first electrode of the first transistor;

a second transistor disposed over the first transistor, a lower surface of the second transistor including a second electrode of the second transistor; and

and the conductive layer is provided with an upper surface and a lower surface, wherein the lower surface of the conductive layer is coupled with the first windowing region, and the upper surface of the conductive layer is coupled with the lower surface of the second transistor and is used for electrically connecting the first electrode of the first transistor with the second electrode of the second transistor.

The utility model provides a semiconductor device has reduced the demand to the base island quantity of base with the range upon range of setting of at least two transistors on the base of encapsulation frame, is convenient for and ordinary encapsulation frame is compatible, has reduced the encapsulation cost.

The utility model provides a half-bridge circuit module is with the range upon range of setting of first transistor and second transistor on packaging frame's base, through the first electrode of the first transistor of conducting layer electric connection and the second electrode of second transistor, has reduced the demand to the base island quantity of base, is convenient for compatible with ordinary packaging frame, has reduced the encapsulation cost.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

fig. 1 shows a schematic structural diagram of a half-bridge cell according to the prior art;

FIG. 2 shows a schematic diagram of a package structure according to the prior art;

fig. 3 shows a schematic cross-sectional structure of a transistor according to the prior art;

fig. 4 shows a schematic top surface structure of a transistor of a semiconductor device according to an embodiment of the present invention;

fig. 5 shows a schematic cross-sectional structure diagram of a transistor of a semiconductor device according to an embodiment of the present invention;

fig. 6 shows a schematic partial structure diagram of a semiconductor device according to an embodiment of the present invention.

Detailed Description

Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.

The following detailed description of the embodiments of the present invention is provided with reference to the accompanying drawings and examples.

Fig. 3 shows a schematic cross-sectional structure of a transistor according to the prior art.

As shown in fig. 3, the transistor 100 is a VDMOS (Vertical Double-diffused Metal Oxide Semiconductor), in this embodiment, it is an N-type VDMOS, and an epitaxial layer 120 is disposed on a substrate 110, two ends of an upper surface of the epitaxial layer 120 include two spaced well regions 130, an upper surface of each of the two well regions 130 includes a doped region 131, a gate structure is disposed on the epitaxial layer 120 and includes a gate Oxide layer 141 and a polysilicon gate 142, a projection of the polysilicon gate 142 on the upper surface of each of the two well regions 130 is located between the two doped regions 131, and two ends of the polysilicon gate 142 respectively extend to the two doped regions 131 to form a channel region between the two doped regions 131, the gate Oxide layer 141 is disposed around the polysilicon gate 142 to isolate the polysilicon gate 142 from direct electrical connection with other structures, a source Metal layer 101 is disposed on the upper surface of the transistor 100 and electrically contacts the well regions 130 and the doped regions 131, a source electrode is led out through the source metal layer 101 to form a source electrode S, the lower surface of the substrate 110 is covered with the drain metal layer 102 to lead out a drain electrode to form a drain electrode D, and the polysilicon gate 142 leads out a gate electrode G.

Taking an N-type VDMOS as an example, the substrate 110 is an N-type doped substrate, such as a silicon substrate, the drift region 120 is an N-type doped region, the well region 130 is a P-type doped region, and the transistor 100 has a structure with a source S on top and a drain D on bottom.

Fig. 4 shows a schematic top surface structure diagram of a transistor of a semiconductor device according to an embodiment of the present invention, and fig. 5 shows a schematic cross-sectional structure diagram of a transistor of a semiconductor device according to an embodiment of the present invention, where fig. 5 corresponds to a schematic cross-sectional structure diagram of the transistor 200 in fig. 4 along line AA.

Referring to fig. 4 and 5, an upper surface of the transistor 200 of the semiconductor device according to the embodiment of the present invention includes a first open window region 201 and a gate structure 220 separated by an insulating layer 210, an upper surface of the first open window region 201 corresponds to a source electrode, the gate structure 220 includes a second open window region 221 therein for a gate electrode (polysilicon gate), a lower surface of the transistor 200 corresponds to a drain electrode, and in an example of an N-type VDMOS, the transistor 200 has the same structure as the transistor 100 except that the source electrode is clearly separated from the gate electrode. The electrode material is typically copper, i.e., copper is coated on the surfaces of the first window 201 and the second window 221 and on the lower surface of the transistor 200.

The thickness from the upper surface of the insulating layer 210 to the lower surface of the transistor 200 is greater than the thickness from the upper surfaces of the first and second windowing regions 201 and 221 to the lower surface of the transistor 200, so that the insulating performance can be ensured, and the subsequent positioning stability of the upper-layer transistor in the first windowing region of the lower-layer transistor can be facilitated.

Fig. 6 shows a schematic partial structure diagram of a semiconductor device according to an embodiment of the present invention.

As shown in fig. 6, the semiconductor device 300 according to the embodiment of the invention includes a package frame including a base 310 and a lead 320 fixedly connected to the base 310, and a first transistor 2001 and a second transistor 2002 provided in the package frame. The first transistor 2001 and the second transistor 2002 have the same structure as the transistor 200, except that the size of the second transistor 2002 is smaller than that of the first transistor 2001, and mainly that the surface area of the first window region of the first transistor 2001 is larger than or equal to the area of the lower surface of the second transistor 2002, so that the second transistor 2002 can be placed in the first window region of the first transistor 2001 and extraction of the gate electrode of the second window region of the first transistor 2001 is facilitated.

In an alternative embodiment, the size of the second transistor 2002 is larger than the size of the first open window region of the first transistor 2001, and the corresponding electrodes of the first transistor 2001 and the second transistor 2002 (the source electrode (first electrode) of the first open window region of the first transistor 2001 is connected with the drain electrode (second electrode) of the lower surface of the second transistor 2002) can be electrically connected reliably through the conductive layer 301, so that the size design of the second transistor 2002 can be maintained, the performance of the second transistor 2002 can be guaranteed, and the performance of a corresponding half-bridge circuit module can be guaranteed.

The first transistor 2001 and the second transistor 2002 are sequentially stacked on the base 310, the first transistor 2001 is a lower transistor and is directly disposed on the upper surface of the base 310, and the drain electrode of the lower surface of the first transistor 2001 is electrically connected to one of the leads 320 through a wiring arrangement on the base 310, and is led out to correspond to the drain terminal of the semiconductor device 300.

The second transistor 2002 corresponds to an upper transistor, is provided in the first window region of the first transistor 2001, a drain electrode of a lower surface of the second transistor 2002 is electrically connected to a source electrode of an upper surface of the first window region of the first transistor 2001, a series structure of the first transistor 2001 and the second transistor 2002 is formed, the source electrode of the first window region of the second transistor 2002, a gate electrode of the second window region, and a gate electrode of the second window region of the first transistor 2001 are connected to the corresponding leads 320 through the wire wiring 304 to lead out the source electrode of the second transistor 2002 as a source of the semiconductor device 300, and gate electrodes of the first transistor 2001 and the second transistor 2002 are led out.

The gate electrodes of the second windowing regions of the first transistor 2001 and the second transistor 2002 can be respectively led out TO two pins 320 or the same pin 320, so that the integrated control is realized, the integrated control can be applied TO TO252 packaging, and only three pins are led out.

In this embodiment, the conductive layer 301 is a conductive adhesive, and the lower surface of the second transistor 2002 is electrically connected to the upper surface of the first open window region of the first transistor 2001 through the conductive adhesive, so that the reliability of the electrical connection can be ensured. In an alternative embodiment, the lower surface of the second transistor 2002 and the upper surface of the first open window region of the first transistor 2001 are electrically connected by a pad bonding, and correspondingly, the conductive layer 301 is made of other conductive material such as solder.

In this embodiment, the first transistor 2001 and the second transistor 2002 have source electrodes on the upper surfaces and drain electrodes on the lower surfaces, and are stacked to form a series connection, which is a small improvement over the structure of the conventional VDMOS transistor 100 and is easy to implement. In an alternative embodiment, the upper surface of the first transistor 2001 may be simultaneously provided with a source electrode and a drain electrode, the electrode may be led out to the pin 320 by using a conducting wire, the source electrode and the drain electrode of the second transistor 2002 may be provided on the same surface, and connected in series or in parallel with the source electrode and the drain electrode on the upper surface of the first transistor 2001, which may also reduce the requirement for the number of base islands of the base 310.

The utility model discloses the range upon range of setting of the first transistor 2001 of semiconductor device 300 and second transistor 2002, second transistor 2002 set up on the first windowing district of first transistor 2001, and the requirement to the base 310 of encapsulation frame is limited only to placing first transistor 2001, can adopt conventional encapsulation frame, need not independent design encapsulation frame, has realized the encapsulation of the double transistor of half-bridge structure under the condition that does not increase encapsulation frame design cost. The first transistor 2001 and the second transistor 2002 are stacked in such a manner that the connection distance is short, thereby reducing the resistance in the series connection path.

In this embodiment, two transistors are stacked, and in an optional embodiment, a plurality of transistors are stacked, so that the requirement on the number of base islands of a package frame can be reduced, and the package cost can be reduced.

The utility model discloses an adopt semiconductor device of power half-bridge overlapping scheme to stack up the setting on packaging frame's base with two at least transistors, reduced the demand to the base island quantity of base, be convenient for with ordinary packaging frame is compatible, reduced the encapsulation cost. The package of the power half-bridge encapsulation scheme can be selected from TO252, TO247, TO263 and the like.

In some embodiments, the routing locations, directions, thicknesses, etc. may be different from those shown or described above.

It should be understood that the position relationship of "up" and "down" is reversed, or the position relationship of the whole angle after unified adjustment is within the protection scope of the present invention.

In accordance with the embodiments of the present invention as set forth above, these embodiments are not exhaustive and do not limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and its various embodiments with various modifications as are suited to the particular use contemplated. The present invention is limited only by the claims and their full scope and equivalents.

Claims (10)

1. A semiconductor device employing a power half-bridge stack encapsulation scheme, comprising:

a package frame including a base;

at least two transistors stacked on the base, wherein,

an upper surface of a lower transistor of adjacent transistors of the at least two transistors includes a first windowed area including at least one of a source electrode and a drain electrode of the lower transistor;

an upper transistor of adjacent transistors of the at least two transistors is disposed in the first open window region of the lower transistor, and a lower surface of the upper transistor includes at least one of a source electrode and a drain electrode of the upper transistor and is connected in series or in parallel with at least one of the source electrode and the drain electrode of the lower transistor.

2. The semiconductor device according to claim 1,

the transistors of the at least two transistors comprise vertical double-diffused metal oxide semiconductor transistors.

3. The semiconductor device according to claim 2, wherein the at least two transistors comprise:

the transistor comprises a base, a first transistor and a second transistor, wherein the base is provided with a first windowing area and a second windowing area which are separated by an insulating layer, the upper surface of the first transistor comprises a drain electrode, the first windowing area of the first transistor comprises a source electrode of the first transistor, and the second windowing area of the first transistor comprises a gate electrode of the first transistor;

a second transistor disposed on the first window region of the first transistor, an upper surface of the second transistor including the first window region and a second window region separated by an insulating layer, a lower surface of the second transistor including a drain electrode electrically connected to a source electrode of the first transistor, the first window region of the second transistor including a source electrode of the second transistor, the second window region of the second transistor including a gate electrode of the second transistor,

the first transistor and the second transistor are both longitudinal double-diffused metal oxide field effect transistors.

4. The semiconductor device according to claim 3,

a conducting layer is arranged between the first windowing area of the first transistor and the lower surface of the second transistor and comprises conducting resin.

5. The semiconductor device according to claim 3,

the first transistor and the second transistor are high voltage transistors.

6. The semiconductor device according to claim 5,

the first transistor and the second transistor are NMOS transistors.

7. The semiconductor device according to claim 3,

the area of the first windowing area of the first transistor is larger than the area of the lower surface of the second transistor.

8. The semiconductor device of claim 3, wherein the package frame comprises:

a first pin electrically connected to a drain electrode of a lower surface of the first transistor;

and the second pin is electrically connected with the source electrode of the first windowing area of the second transistor.

9. The semiconductor device according to claim 3 or 8,

the gate electrode of the first transistor and the gate electrode of the second transistor are electrically connected to two leads of the package frame or to the same lead of the package frame, respectively.

10. A half-bridge circuit module, comprising:

a package frame including a base;

a first transistor disposed on the base, an upper surface of the first transistor including a first windowed area, the first windowed area including a first electrode of the first transistor;

a second transistor disposed over the first transistor, a lower surface of the second transistor including a second electrode of the second transistor; and

and the conductive layer is provided with an upper surface and a lower surface, wherein the lower surface of the conductive layer is coupled with the first windowing region, and the upper surface of the conductive layer is coupled with the lower surface of the second transistor and is used for electrically connecting the first electrode of the first transistor with the second electrode of the second transistor.

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