CN213042123U

CN213042123U - High-frequency sine gating signal generation device

Info

Publication number: CN213042123U
Application number: CN202022040011.6U
Authority: CN
Inventors: 祁留锋; 周石磊; 邵继虎
Original assignee: Beijing Zhongchuangwei Nanjing Quantum Communication Technology Co ltd
Current assignee: Beijing Zhongchuangwei Nanjing Quantum Communication Technology Co ltd
Priority date: 2020-09-16
Filing date: 2020-09-16
Publication date: 2021-04-23
Anticipated expiration: 2030-09-16

Abstract

The utility model discloses a high-frequency sine gating signal generating device, which relates to the field of signal detection and comprises a clock generator, a first phase-locked loop, a second phase-locked loop, a FPGA, a filter, an adjustable attenuator, an amplifier and a coupler which are electrically connected in sequence; the FPGA comprises a high-speed communication interface, and the high-speed communication interface of the FPGA is electrically connected with the filter. The sinusoidal gating signal generation device can generate sinusoidal gating signals with high frequency for the sinusoidal gating single photon detector.

Description

High-frequency sine gating signal generation device

Technical Field

The application relates to the field of signal detection, in particular to a high-frequency sine gating signal generation device.

Background

The single photon detector is used as a very key device in a quantum key distribution system, and index parameters of the single photon detector directly determine the performance of a quantum communication system, such as communication rate, safe communication distance and the like. Currently, a single photon detector based on semiconductor materials is mainly used in practice, and avalanche photodiodes based on InGaAs/InP are mainly used in near infrared bands. The single photon detector based on the InGaAs/InP avalanche photodiode mainly adopts a free mode and a gating mode, and for the free mode, the single photon source can reach the detector at any time, but due to the fact that dead time is long, the repetition frequency of the single photon source is limited, the single photon source can only work at low speed, and dark count is large; in order to overcome the dark count of the single-photon detector, the quantum key distribution system requires that the detector basically works in a gating mode. At present, the gating signals of the detector are mainly divided into two types, one is sine wave gating, and the other is square wave gating; for the square wave gating single photon detector, because the frequency spectrum range of peak noise is very wide, the noise suppression technology is difficult, so that the peak noise is less adopted in practice, and the sine wave gating single photon detector is generally adopted at present. The existing sine gating signal frequency for the sine wave gating single photon detector is generally low, and a device capable of generating a high-frequency sine gating signal is needed.

SUMMERY OF THE UTILITY MODEL

The application provides a high-frequency sine gating signal generation device to solve the problem that the gating signal frequency of a sine wave gating single photon detector in the prior art is low.

The embodiment of the utility model provides a concrete technical scheme is:

a high-frequency sine gating signal generation device is characterized by comprising a clock generator, a first phase-locked loop, a second phase-locked loop, an FPGA, a filter, an adjustable attenuator, an amplifier and a coupler which are electrically connected in sequence; the FPGA comprises a high-speed communication interface, and the high-speed communication interface of the FPGA is electrically connected with the filter.

Preferably, the high-speed communication interface of the FPGA is a GTx interface.

Preferably, one output end of the coupler is connected to the sine wave gated single photon detector.

Preferably, the frequency multiplication coefficient of the first phase-locked loop is greater than the frequency multiplication coefficient of the second phase-locked loop.

Preferably, the amplifier is a power amplifier.

Preferably, the power amplifier is a two-stage power amplifier.

Preferably, the power amplifier is a three-stage power amplifier.

According to the scheme, the high-frequency sinusoidal gating signal generating device is high in frequency and good in stability of sinusoidal gating signals generated by the high-frequency sinusoidal gating signal generating device.

Specific embodiments of the present invention are disclosed in detail with reference to the following description and the accompanying drawings, which specify the manner in which the principles of the invention may be employed. It should be understood that the embodiments of the present invention are not so limited in scope. The embodiments of the invention include many variations, modifications and equivalents within the spirit and scope of the appended claims. Features that are described and/or illustrated with respect to one embodiment may be used in the same way or in a similar way in one or more other embodiments, in combination with or instead of the features of the other embodiments.

Drawings

The drawings described herein are for illustration purposes only and are not intended to limit the scope of the present disclosure in any way. In addition, the shapes, the proportional sizes, and the like of the respective members in the drawings are merely schematic for helping the understanding of the present invention, and do not specifically limit the shapes, the proportional sizes, and the like of the respective members of the present invention. The skilled person in the art can, under the teaching of the present invention, choose various possible shapes and proportional dimensions to implement the invention according to the specific situation.

Fig. 1 is a schematic diagram of a high-frequency sinusoidal gating signal generating apparatus according to the present application.

Detailed Description

The details of the present invention can be more clearly understood with reference to the accompanying drawings and the description of the embodiments of the present invention. However, the specific embodiments of the present invention described herein are for the purpose of explanation only, and should not be construed as limiting the invention in any way. Given the teachings of the present invention, the skilled person can conceive of any possible variants based on the invention, which should all be considered as belonging to the scope of the invention. It will be understood that when an element is referred to as being "disposed on" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "mounted," "connected," and "connected" are to be construed broadly and may include, for example, mechanical or electrical connections, communications between two elements, direct connections, indirect connections through intermediaries, and the like. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and the like as used herein are for illustrative purposes only and do not denote a unique embodiment.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Fig. 1 is a schematic diagram of a high-frequency sinusoidal gating signal generation apparatus according to the present application. Referring to fig. 1, a high-frequency sinusoidal gating signal generation apparatus includes a clock generator, a first phase-locked loop, a second phase-locked loop, an FPGA, a filter, an adjustable attenuator, an amplifier, and a coupler, which are electrically connected in sequence.

Specifically, the clock generator is used for generating a preliminary digital clock signal, and the frequency of the digital clock signal is low, such as 100 KHz; the first phase-locked loop is used for carrying out frequency multiplication on a preliminary digital clock signal generated by the clock generator to obtain a first frequency multiplication digital clock signal; the second phase-locked loop is used for carrying out frequency multiplication processing on the first frequency multiplication digital clock signal again to obtain a second frequency multiplication digital clock signal; the FPGA is used for processing the second digital clock signal to obtain a high-bit-rate digital signal with the duty ratio of 40% -60%; the filter is used for filtering a high-frequency part in the digital signal to obtain a fundamental frequency sinusoidal signal; the adjustable attenuator can adjust the size of the sinusoidal signal and is used for outputting the sinusoidal signal after power adjustment; the amplifier is used for amplifying the sinusoidal signal output by the adjustable attenuator to obtain a gate control signal; the coupler is used for power distribution and is used for outputting a gating signal with certain power to the single-photon detector.

The frequency multiplication coefficient of the first phase-locked loop is larger than that of the second phase-locked loop, and the first phase-locked loop and the second phase-locked loop are both low-jitter phase-locked loops. In a specific embodiment, the first phase-locked loop is configured to multiply the preliminary 100KHz digital clock signal into a 10MHz first multiple digital clock signal, the second phase-locked loop is configured to multiply the 10MHz first multiple digital clock signal into a 100MHz/125MHz second multiple digital clock signal again, the FPGA is configured to process the 100MHz/125MHz second multiple digital clock signal into a 2.5Gbps code rate signal with a duty ratio of 40% -60%, and then, the signal is filtered by the filter to obtain a 1.25GHz sinusoidal signal.

The FPGA comprises a high-speed communication interface which can be set as a GTx interface, and the FPGA is electrically connected with the filter through the high-speed communication interface. The amplifier is set as a power amplifier, and the power amplification factor of the power amplifier is a fixed value and is used for amplifying the power of the sine wave gating signal adjusted by the adjustable attenuator. One output end of the coupler is connected with the sine wave gate-controlled single photon detector, and a signal output by the coupler is a high-frequency sine gate-controlled signal; and the sine wave gated single-photon detector receives the high-frequency sine gated signal and is used for single-photon detection in a quantum key distribution system.

The power amplifier can be a two-stage power amplifier or a three-stage power amplifier, wherein the two-stage power amplifier is formed by connecting two power amplifiers in series, and the three-stage power amplifier is formed by connecting three power amplifiers in series. The two-stage power amplifier or the three-stage power amplifier is electrically connected with the output end of the adjustable attenuator.

Through the embodiment, the sinusoidal gating signal with high frequency can be generated, and through multi-stage frequency multiplication processing, the signal jitter is low, and the stability is good.

In another possible embodiment, the adjustable attenuator may be disposed in the middle of the two-stage power amplifier or the three-stage power amplifier, that is, the output terminal of the filter is connected to the input terminal of the first-stage power amplifier, the output terminal of the first-stage power amplifier is connected to the input terminal of the adjustable attenuator, and the output terminal of the adjustable attenuator is connected to the remaining one-stage power amplifier or the remaining two-stage power amplifier.

The present application has been described in detail with reference to specific embodiments and illustrative examples, but the description is not intended to limit the application. Those skilled in the art will appreciate that various equivalent substitutions, modifications or improvements may be made to the presently disclosed embodiments and implementations thereof without departing from the spirit and scope of the present disclosure, and these fall within the scope of the present disclosure. The protection scope of this application is subject to the appended claims.

Claims

1. A high-frequency sine gating signal generation device is characterized by comprising a clock generator, a first phase-locked loop, a second phase-locked loop, an FPGA, a filter, an adjustable attenuator, an amplifier and a coupler which are electrically connected in sequence;

the FPGA comprises a high-speed communication interface, and the high-speed communication interface of the FPGA is electrically connected with the filter.

2. The apparatus according to claim 1, wherein the high-speed communication interface of the FPGA is a GTx interface.

3. The high frequency sinusoidal gating signal generation device according to claim 1, wherein an output of the coupler is connected to a sinusoidal gated single photon detector.

4. The apparatus according to claim 1, wherein the first phase-locked loop has a frequency multiplication factor greater than that of the second phase-locked loop.

5. A high frequency sinusoidal gating signal generation device according to claim 1, wherein the amplifier is a power amplifier.

6. The high frequency sinusoidal gating signal generation device of claim 5, wherein the power amplifier is a two-stage power amplifier.

7. The apparatus according to claim 5, wherein the power amplifier is a three-stage power amplifier.