CN107271055B - Infrared single photon detection system of parallel avalanche photodiode array structure - Google Patents
Infrared single photon detection system of parallel avalanche photodiode array structure Download PDFInfo
- Publication number
- CN107271055B CN107271055B CN201610247486.8A CN201610247486A CN107271055B CN 107271055 B CN107271055 B CN 107271055B CN 201610247486 A CN201610247486 A CN 201610247486A CN 107271055 B CN107271055 B CN 107271055B
- Authority
- CN
- China
- Prior art keywords
- circuit
- parallel
- chip
- signal
- pin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000001514 detection method Methods 0.000 title claims abstract description 53
- 230000003287 optical effect Effects 0.000 claims abstract description 46
- 238000006243 chemical reaction Methods 0.000 claims abstract description 12
- 238000012545 processing Methods 0.000 claims abstract description 11
- 239000003990 capacitor Substances 0.000 claims description 150
- 230000008878 coupling Effects 0.000 claims description 17
- 238000010168 coupling process Methods 0.000 claims description 17
- 238000005859 coupling reaction Methods 0.000 claims description 17
- 239000013078 crystal Substances 0.000 claims description 12
- 101100381996 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) BRO1 gene Proteins 0.000 claims description 7
- 238000012216 screening Methods 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 9
- 238000000098 azimuthal photoelectron diffraction Methods 0.000 description 89
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 230000001360 synchronised effect Effects 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 230000007306 turnover Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
- G01J5/00—Radiation pyrometry, e.g. infrared or optical thermometry
- G01J5/10—Radiation pyrometry, e.g. infrared or optical thermometry using electric radiation detectors
- G01J5/20—Radiation pyrometry, e.g. infrared or optical thermometry using electric radiation detectors using resistors, thermistors or semiconductors sensitive to radiation, e.g. photoconductive devices
- G01J5/22—Electrical features thereof
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Electronic Switches (AREA)
- Optical Communication System (AREA)
Abstract
The invention relates to an infrared single photon detection system with a parallel avalanche photodiode array structure, which comprises a parallel APD array driving circuit, wherein the output end of the parallel APD array driving circuit is connected with the input end of a parallel APD array, the output end of the parallel APD array is connected with the input end of a signal detection circuit, the output end of the signal detection circuit is connected with the input end of an analog-to-digital conversion circuit, the output end of the signal analog-to-digital conversion circuit is connected with the input end of a signal processing circuit, and the output end of the signal processing circuit is connected with the input end of a digital signal output circuit. The invention converts a single photon signal into an avalanche electric signal by using the parallel APD array, enables the parallel APD array to work in a Geiger mode by using the direct current bias voltage circuit, realizes the channel time sequence switching function of the parallel APD array by using the high-speed pulse gate time sequence signal circuit and the multi-channel optical switch, reduces the dead time of an APD device, overcomes the post-pulse effect of a detector, and effectively improves the working frequency and the detection efficiency of the detector.
Description
Technical Field
The invention relates to the technical field of weak signal detection in quantum communication and quantum information technology, in particular to an infrared single photon detection system with a parallel avalanche photodiode array structure.
Background
At present, an infrared single photon detector mainly uses a photoelectric detection method by using an APD device, and the principle of the infrared single photon detector is that when a junction semiconductor device receives a single photon, the photoelectric effect of a photon-generated carrier is utilized, and the avalanche multiplication effect of the carrier is generated by means of the action of a strong electric field, so that a high-sensitivity weak avalanche signal is obtained, and a plurality of special photoelectric signal processing methods are developed, so that great progress is made, and the infrared single photon detector is practically applied to an actual quantum cryptography communication system.
The infrared single photon detector based on the InGaAs/InP APD device has the advantages of high response speed, high detection sensitivity, low dark count rate, high count repetition rate, low cost, strong practicability and the like, and the InGaAs/InP APD serving as a heterojunction compound semiconductor device has greatly progressed in the research of device technology and structure in recent years, the performance index is improved, and commercial devices have been developed successfully. With the improvement of device performance and the development of weak signal detection electronics, single photon detectors based on InGaAs/InP APDs are still the dominant method of future high-speed infrared single photon detection technology.
Due to some defects in the InGaAs/InP APD material, it is easy to become a trapping center for carriers. Because the carrier is captured by the capture center and released after a period of time, an avalanche signal, namely a post-pulse effect, is also generated, the current main solution is to set a certain dead time, namely a period of time after the avalanche is restrained, so that the bias voltage applied to the APD is far smaller than the avalanche voltage, and the released carrier can not trigger the avalanche. For example, for a single photon detector with a trigger frequency of 100MHz, the maximum count rate does not exceed 100kHz, and the APD bias voltage is reduced by setting a suitable dead time and does not detect for several mus, so that the post-pulse effect problem can be effectively solved. However, for high-speed detectors with count repetition rates above GHz, the dead time between effective detections can only be set to the order of 1ns at most, well below the carrier lifetime in APD, and therefore the post-pulse effect at high-speed detection cannot be overcome at all.
Disclosure of Invention
The invention aims to provide an infrared single photon detection system with a parallel avalanche photodiode array structure, which can reduce the dead time of an APD device and effectively improve the working frequency and detection efficiency of a detector.
In order to achieve the above purpose, the present invention adopts the following technical scheme: the infrared single photon detection system comprises a parallel APD array driving circuit for driving a parallel APD array, wherein the output end of the parallel APD array driving circuit is connected with the control input end of the parallel APD array, the output end of the parallel APD array is connected with the input end of a signal detection circuit for converting a single photon signal output by the parallel APD array into an avalanche electric signal and extracting the avalanche electric signal, the output end of the signal detection circuit is connected with the input end of an analog-to-digital conversion circuit for converting the extracted avalanche electric signal into a digital signal, the output end of the signal analog-to-digital conversion circuit is connected with the input end of a signal processing circuit for detecting and counting the converted digital signal in a discrimination mode, and the output end of the signal processing circuit is connected with the input end of the digital signal output circuit.
The parallel APD array is formed by a plurality of APD devices in a separated mode to form a parallel array structure, or a plurality of APD chips are integrated on the same chip to be packaged into a device; the parallel APD array comprises two control inputs and an output, wherein a dc bias voltage signal is input as a first control input, an ac gating bias signal is input as a second control input, and an avalanche electrical signal is output as an output.
The parallel APD array driving circuit consists of a direct-current bias voltage circuit, a high-speed pulse gate control time sequence signal circuit and a multi-channel optical switch, the signal detection circuit consists of a multi-stage low-pass filter circuit and a high-speed broadband amplifying circuit, the analog-digital conversion circuit adopts a high-speed comparison circuit, and the signal processing circuit consists of a digital signal discrimination circuit and a counter; the output end of the direct current bias voltage circuit is connected with the first control input end of the parallel APD array, the output end of the high-speed pulse gating time sequence signal circuit is connected with the second control input end of the parallel APD array, the output end of the parallel APD array is connected with the first input end of the multichannel optical switch, the output end of the high-speed pulse gating time sequence signal circuit is also connected with the second input end of the multichannel optical switch, the output end of the multichannel optical switch is connected with the input end of the multistage low-pass filter circuit, the output end of the multistage low-pass filter circuit is connected with the input end of the high-speed broadband amplifying circuit, the output end of the high-speed broadband amplifying circuit is connected with the input end of the high-speed comparison circuit, the output end of the high-speed comparison circuit is connected with the input end of the digital signal discrimination circuit, the output end of the digital signal discrimination circuit is connected with the input end of the counter, and the output end of the counter is connected with the input end of the digital signal output circuit.
The DC bias voltage circuit comprises a chip U3, a MOS transistor T1, a fast rectifying diode D1, a filter inductor L8, resistors R51-R57, capacitors C62-C64 and filter capacitors C65-C70, wherein the chip U3 is a PWM switch control chip UC3845, the resistor R53 is connected with the capacitor C62 in parallel, two ends of the parallel end are respectively connected with 1 pin and 2 pin of the chip U3, 2 pin of the chip U3 is also respectively connected with one end of the resistor R51 and one end of the resistor R52, 4 pin of the chip U3 is connected with one end of the resistor R54, 3 pin of the chip U3 is grounded through the capacitor C63, 4 pin of the chip U3 is grounded through the capacitor C64, 8 pin of the chip U3 is grounded through the filter capacitor C65, the pin 7 of the chip U3 is respectively grounded through a filter capacitor C66 and a filter capacitor C67, the pin 6 of the chip U3 is connected with the pin 4 of the MOS transistor T1 through a resistor R56, the pin 5 of the chip U3 is respectively connected with the pins 1, 2 and 3 of the MOS transistor T1 through a resistor R57, the pins 5, 6, 7 and 8 of the MOS transistor T1 are connected in parallel and then connected with one end of a filter inductor L8, the pin 5 of the MOS transistor T1 is connected with the anode of a fast rectifying diode D1, the cathode of the fast rectifying diode D1 is respectively grounded through the filter capacitor C69 and the filter capacitor C70, and the cathode of the fast rectifying diode D1 is used as the output end of a DC bias voltage circuit and is connected with the first control input end of the parallel array.
The high-speed pulse gate control time sequence signal circuit comprises a chip U5, a resistor R50, power supply filter capacitors C56-C59 and signal coupling capacitors C60-C61, wherein the chip U5 is a 12.5GHz broadband power amplifier, and a 1 foot of the chip U5 is grounded through the power supply filter capacitors C56 and C59 which are connected in parallel; the 3 pin is grounded through parallel power supply filter capacitors C57 and C58; the 7 pin of the power supply is grounded; the 8 pin is respectively connected with one end of a signal coupling capacitor C60 and one end of a resistor R50, the other end of the signal coupling capacitor C60 is connected with a high-frequency signal source signal provided by the outside, the other end of the resistor R50 is grounded, the 9 pin of a chip U5 is connected with one end of a signal coupling capacitor C61, the other end of the signal coupling capacitor C61 is used as an output end of a high-speed pulse gate control time sequence signal circuit, and the other end of the signal coupling capacitor C61 is respectively connected with a second control input end of a parallel APD array and a second input end of a multichannel optical switch.
The multichannel optical switch comprises a chip U4, an active crystal oscillator Y40, filter inductors L6-L7, power supply filter capacitors C40-C55 and resistors R40-R45, wherein the chip U4 adopts a programmable FPGA controller with the model of EP1C6T144C8N, the chip U4 comprises a chip U4A and a chip U4B, a 10 pin of the chip U4A is connected with a 3 pin of the active crystal oscillator Y40 through the resistor R40, a 2 pin of the active crystal oscillator Y40 is grounded, a 4 pin of the active crystal oscillator Y40 is respectively connected with one end of the resistor R44 and one end of the power supply filter capacitor C55, the other end of the power supply filter capacitor C55 is grounded, the power supply filter capacitors C40, C42 and C44 are connected in parallel, the other end of the power supply filter capacitor C is respectively connected with one end of the filter inductor L6 and the other end of the filter inductor L6 is connected with one end of the power supply filter capacitor C46, and the other end of the power supply filter capacitor C46 is grounded; the power supply filter capacitors C41, C43 and C45 are connected in parallel, and a parallel end of the power supply filter capacitors C41, C43 and C45 is respectively connected with the pin 29 of the chip U4A and one end of the filter inductor L7, the other end of the filter inductor L7 is connected with one end of the power supply filter capacitor C47, and the other end of the power supply filter capacitor C47 is grounded; the power supply filter capacitors C52, C53 and C54 are connected in parallel, one end of the parallel end is connected with the pin 81 of the chip U4B, and the other end is grounded; pin 73 of the chip U4B is used as a first input end of the multichannel optical switch and is connected with an output end of the parallel APD array, pin 105 of the chip U4B is used as a second input end of the multichannel optical switch and is connected with an output end of the high-speed pulse gate control time sequence signal circuit, and pins 61, 62 and 67-72 of the chip U4B are used as output ends of the multichannel optical switch and are connected with an input end of the multistage low-pass filter circuit.
The multistage low-pass filter circuit comprises 15 stages of LC passive microwave low-pass filters LPF 1-LPF 2, a resistor R1, an inductor L1 and capacitors C1-C2, the high-speed broadband amplifying circuit comprises a chip U1, inductors L2-L3, resistors R2-R3 and capacitors C3-C19, the chip U1 adopts an adjustable gain broadband amplifier ADL5330, the 1 foot of the adjustable gain broadband amplifier is respectively connected with one ends of the capacitors C19 and C3, and the other ends of the capacitors C19 and C3 are grounded; the 24 pins are respectively connected with one ends of the resistors R2 and R3, and the other end of the resistor R3 is grounded; the 16 pin is respectively connected with one end of an inductor L2 and one end of a capacitor C17, the other end of the capacitor C17 is used as an output end of a high-speed broadband amplifying circuit, the other end of the capacitor C17 is connected with an input end of a high-speed comparison circuit, the capacitors C11 and C12 are connected in parallel, the other end of the inductor L2 is respectively connected with one end parallel end of an inductor L3 and one end parallel end of the capacitors C11 and C12, and the other end parallel end of the capacitors C11 and C12 is grounded; the 15 pin is respectively connected with one end of the inductor L3 and one end of the capacitor C18, and the other end of the capacitor C18 is grounded; the input end of the 15-stage LC passive microwave low-pass filter LPF1 is connected with one end of a capacitor C2, the other end of the capacitor C2 is connected with one end of an inductor L1, the inductor is used as the input end of a multi-stage low-pass filter circuit and is connected with the output end of a multi-channel optical switch, the other end of the inductor L1 is grounded through a resistor R1 and the capacitor C1 in sequence, the output end of the 15-stage LC passive microwave low-pass filter LPF1 is connected with the input end of the 15-stage LC passive microwave low-pass filter LPF2, and the output end of the 15-stage LC passive microwave low-pass filter LPF2 is connected with the 3 pins of the chip U1 through a capacitor C4 and a capacitor C6 in sequence.
The high-speed comparison circuit comprises a chip U2, an inductor L4, resistors R5-R11 and capacitors C21-C31, wherein the chip U2 adopts a high-speed comparator ADCMP573, a pin 2 of the chip is used as an input end of the high-speed comparison circuit and is respectively connected with one end of a resistor R5 and an output end of a high-speed broadband amplifying circuit, and the other end of the resistor R5 is grounded; the 3 pin is respectively connected with one end of an inductor L4 and one end of a capacitor C22, the inductor L4 is grounded through a capacitor C21, and the other end of the capacitor C22 is grounded; the 11 pin is used as the output end of the high-speed comparison circuit and is connected with the input end of the digital signal discrimination circuit.
According to the technical scheme, the invention has the following advantages: firstly, a parallel APD array formed by a plurality of discrete APD devices is used for converting a single photon signal into an avalanche electric signal, the parallel APD array is enabled to work in a Geiger mode by utilizing a direct-current bias voltage circuit, a channel time sequence switching function of the parallel APD array is realized by utilizing a high-speed pulse gate control time sequence signal circuit and a multi-channel optical switch, and the dead time of the APD devices is reduced; secondly, the working speed of the infrared single photon detection system with the parallel APD array structure is up to 2GHz, and the repetition frequency is up to more than 1000 MHz; third, the infrared single photon detection system with the parallel APD array structure overcomes the post-pulse effect of the detector and effectively improves the working frequency and the detection efficiency of the detector.
Drawings
Fig. 1 is a block diagram of a system architecture of the present invention.
FIG. 2 is a block diagram of a specific system architecture of the present invention;
fig. 3, fig. 4, fig. 5, fig. 6, and fig. 7 are schematic circuit diagrams of the dc bias voltage circuit, the high-speed pulse gate timing signal circuit, the multi-channel optical switch, the signal detection circuit, and the high-speed comparison circuit in fig. 2, respectively.
Detailed Description
As shown in fig. 1, an infrared single photon detection system with a parallel avalanche photodiode array structure includes a parallel APD array driving circuit 10 for driving a parallel APD array, an output end of the parallel APD array is connected to a control input end of the parallel APD array, an output end of the parallel APD array is connected to an input end of a signal detection circuit 20 for converting a single photon signal output by the parallel APD array into an avalanche electric signal and extracting the avalanche signal, an output end of the signal detection circuit 20 is connected to an input end of an analog-to-digital conversion circuit for converting the extracted avalanche electric signal into a digital signal, an output end of the signal analog-to-digital conversion circuit is connected to an input end of a signal processing circuit 40 for performing discrimination detection and counting on the converted digital signal, and an output end of the signal processing circuit 40 is connected to an input end of the digital signal output circuit. The parallel APD array is formed by a plurality of APD devices in a separated mode to form a parallel array structure, or a plurality of APD chips are integrated on the same chip to be packaged into a device; the parallel APD array comprises two control inputs and an output, wherein a dc bias voltage signal is input as a first control input, an ac gating bias signal is input as a second control input, and an avalanche electrical signal is output as an output.
As shown in fig. 2, the parallel APD array driving circuit 10 is composed of a dc bias voltage circuit 11, a high-speed pulse gate timing signal circuit 12 and a multi-channel optical switch 13, the signal detection circuit 20 is composed of a multi-stage low-pass filter circuit 21 and a high-speed broadband amplifying circuit 22, the analog-to-digital conversion circuit adopts a high-speed comparison circuit 30, and the signal processing circuit 40 is composed of a digital signal discrimination circuit and a counter; the output end of the direct current bias voltage circuit 11 is connected with a first control input end of a parallel APD array, the output end of the high-speed pulse gating time sequence signal circuit 12 is connected with a second control input end of the parallel APD array, the output end of the parallel APD array is connected with a first input end of a multi-channel optical switch 13, the output end of the high-speed pulse gating time sequence signal circuit 12 is also connected with a second input end of the multi-channel optical switch 13, the output end of the multi-channel optical switch 13 is connected with the input end of a multi-stage low-pass filter circuit 21, the output end of the multi-stage low-pass filter circuit 21 is connected with the input end of a high-speed broadband amplifying circuit 22, the output end of the high-speed broadband amplifying circuit 22 is connected with the input end of a high-speed comparison circuit 30, the output end of the high-speed comparison circuit 30 is connected with the input end of a digital signal discrimination circuit, the output end of the digital signal discrimination circuit is connected with the input end of a counter, and the output end of the counter is connected with the input end of the digital signal output circuit.
As shown in fig. 3, the dc bias voltage circuit 11 includes a chip U3, a MOS transistor T1, a fast rectifying diode D1, a filter inductor L8, resistors R51 to R57, capacitors C62 to C64, and filter capacitors C65 to C70, where the chip U3 is a PWM switch control chip UC3845, the resistor R53 is connected in parallel with the capacitor C62, two ends of the parallel end are respectively connected to pins 1 and 2 of the chip U3, pin 2 of the chip U3 is also respectively connected to one ends of the resistor R51 and the resistor R52, pin 4 of the chip U3 is connected to one end of the resistor R54, pin 3 of the chip U3 is grounded through the capacitor C63, pin 4 of the chip U3 is grounded through the capacitor C64, pin 8 of the chip U3 is grounded through the filter capacitor C65, the pin 7 of the chip U3 is respectively grounded through a filter capacitor C66 and a filter capacitor C67, the pin 6 of the chip U3 is connected with the pin 4 of the MOS transistor T1 through a resistor R56, the pin 5 of the chip U3 is respectively connected with the pins 1, 2 and 3 of the MOS transistor T1 through a resistor R57, the pins 5, 6, 7 and 8 of the MOS transistor T1 are connected in parallel and then connected with one end of a filter inductor L8, the pin 5 of the MOS transistor T1 is connected with the anode of a fast rectifying diode D1, the cathode of the fast rectifying diode D1 is respectively grounded through the filter capacitor C69 and the filter capacitor C70, and the cathode of the fast rectifying diode D1 is used as the output end of a DC bias voltage circuit 11 and is connected with the first control input end of the parallel APD array.
As shown in fig. 4, the high-speed pulse gate timing signal circuit 12 includes a chip U5, a resistor R50, power supply filter capacitors C56 to C59, and signal coupling capacitors C60 to C61, where the chip U5 is a 12.5GHz broadband power amplifier, and a 1 pin of the chip U is grounded through the parallel power supply filter capacitors C56 and C59; the 3 pin is grounded through parallel power supply filter capacitors C57 and C58; the 7 pin of the power supply is grounded; the 8 pin is respectively connected with one end of a signal coupling capacitor C60 and one end of a resistor R50, the other end of the signal coupling capacitor C60 is connected with a high-frequency signal source signal provided by the outside, the other end of the resistor R50 is grounded, the 9 pin of a chip U5 is connected with one end of a signal coupling capacitor C61, the other end of the signal coupling capacitor C61 is used as an output end of a high-speed pulse gate control time sequence signal circuit 12, and the other end of the signal coupling capacitor C61 is respectively connected with a second control input end of a parallel APD array and a second input end of a multichannel optical switch 13.
As shown in fig. 5, the multi-channel optical switch 13 includes a chip U4, an active crystal oscillator Y40, filter inductors L6 to L7, power filter capacitors C40 to C55 and resistors R40 to R45, where the chip U4 adopts a programmable FPGA controller with a model EP1C6T144C8N, the chip U4 includes two parts of the chip U4A and the chip U4B, the 10 pin of the chip U4A is connected to the 3 pin of the active crystal oscillator Y40 through the resistor R40, the 2 pin of the active crystal oscillator Y40 is grounded, the 4 pin of the active crystal oscillator Y40 is connected to one end of the resistor R44 and one end of the power filter capacitor C55 respectively, the other end of the power filter capacitor C55 is grounded, the power filter capacitors C40, C42 and C44 are connected in parallel, and their parallel connection ends are connected to the 8 pin of the chip U4A and one end of the filter inductor L6 respectively, and the other end of the filter inductor L6 is connected to one end of the power filter capacitor C46, and the other end of the power filter capacitor C46 is grounded; the power supply filter capacitors C41, C43 and C45 are connected in parallel, and a parallel end of the power supply filter capacitors C41, C43 and C45 is respectively connected with the pin 29 of the chip U4A and one end of the filter inductor L7, the other end of the filter inductor L7 is connected with one end of the power supply filter capacitor C47, and the other end of the power supply filter capacitor C47 is grounded; the power supply filter capacitors C52, C53 and C54 are connected in parallel, one end of the parallel end is connected with the pin 81 of the chip U4B, and the other end is grounded; pin 73 of the chip U4B is used as a first input end of the multi-channel optical switch 13, connected with an output end of the parallel APD array, pin 105 of the chip U4B is used as a second input end of the multi-channel optical switch 13, connected with an output end of the high-speed pulse gate timing signal circuit 12, and pins 61, 62 and 67-72 of the chip U4B are used as output ends of the multi-channel optical switch 13, connected with an input end of the multi-stage low-pass filter circuit 21.
As shown in fig. 6, the multi-stage low-pass filter circuit 21 includes 15 stages of LC passive microwave low-pass filters LPF1 to LPF2, a resistor R1, an inductor L1, and capacitors C1 to C2, the high-speed broadband amplifying circuit 22 includes a chip U1, inductors L2 to L3, resistors R2 to R3, and capacitors C3 to C19, the chip U1 employs an adjustable gain broadband amplifier ADL5330, a 1 pin of which is connected to one ends of the capacitors C19 and C3, and the other ends of the capacitors C19 and C3 are grounded; the 24 pins are respectively connected with one ends of the resistors R2 and R3, and the other end of the resistor R3 is grounded; the pin 16 is respectively connected with one end of an inductor L2 and one end of a capacitor C17, the other end of the capacitor C17 is used as an output end of a high-speed broadband amplifying circuit 22, the other end of the capacitor C17 is connected with an input end of a high-speed comparison circuit 30, the capacitors C11 and C12 are connected in parallel, the other end of the inductor L2 is respectively connected with one end parallel end of an inductor L3 and one end parallel end of the capacitors C11 and C12, and the other end parallel end of the capacitors C11 and C12 is grounded; the 15 pin is respectively connected with one end of the inductor L3 and one end of the capacitor C18, and the other end of the capacitor C18 is grounded; the input end of the 15-stage LC passive microwave low-pass filter LPF1 is connected with one end of a capacitor C2, the other end of the capacitor C2 is connected with one end of an inductor L1, the inductor is used as the input end of a multi-stage low-pass filter circuit 21 and is connected with the output end of a multi-channel optical switch 13, the other end of the inductor L1 is grounded through a resistor R1 and the capacitor C1 in sequence, the output end of the 15-stage LC passive microwave low-pass filter LPF1 is connected with the input end of the 15-stage LC passive microwave low-pass filter LPF2, and the output end of the 15-stage LC passive microwave low-pass filter LPF2 is connected with the 3 pins of a chip U1 through a capacitor C4 and a capacitor C6 in sequence.
As shown in fig. 7, the high-speed comparison circuit 30 includes a chip U2, an inductor L4, resistors R5 to R11, and capacitors C21 to C31, where the chip U2 employs a high-speed comparator ADCMP573, and a pin 2 thereof is used as an input end of the high-speed comparison circuit 30 and connected to one end of the resistor R5 and an output end of the high-speed broadband amplifying circuit 22, and the other end of the resistor R5 is grounded; the 3 pin is respectively connected with one end of an inductor L4 and one end of a capacitor C22, the inductor L4 is grounded through a capacitor C21, and the other end of the capacitor C22 is grounded; the 11 pin is used as the output end of the high-speed comparison circuit 30 and is connected with the input end of the digital signal discrimination circuit.
The invention is further described below with reference to fig. 1 to 7.
The invention uses a parallel APD array to convert a single photon signal into an avalanche electric signal, uses a direct current bias voltage circuit 11 to enable the parallel APD array to work in a Geiger mode, uses a high-speed pulse gate control time sequence signal circuit 12 and a multi-channel optical switch 13 to realize a channel time sequence switching function of the parallel APD array, and converts the avalanche electric signal output by the parallel APD array into a digital signal through a low-pass filtering and broadband amplifying process of a signal detection circuit 20, and then uses a signal analog-digital conversion circuit to carry out screening detection and counting, and finally outputs various types of digital signals. The infrared single photon detection system with the parallel APD array structure can effectively overcome the post-pulse effect and improve the working frequency and the repetition count rate of single photon detection.
The N APD devices in the parallel APD array all work in a high-gain avalanche state, namely in a Geiger mode, the direct-current bias voltage circuit 11 provides direct-current reverse bias voltage for the parallel APD array, the high-speed pulse gating time sequence signal circuit 12 provides high-speed pulse gating signals with smaller jitter and channel time sequence switching signals for the parallel APD array, the parallel APD array works in the Geiger mode under the gating signals, the channel time sequence switching function is realized, the high-speed gate pulse time sequence signal circuit provides N high-speed gate pulse signals, the N gate pulses are mutually provided with a phase difference of 1/N periods in sequence, the multi-channel optical switch 13 provides a channel switching function, a single photon signal is switched from one channel in the parallel APD array to the next channel, the number of channels is determined by the number N of the APD devices, and the working principle is that when the first APD device in the parallel APD array detects the single photon signal, the input signal enters dead time, the multi-channel optical switch 13 switches the input signal from the APD which cannot respond to the APD device, namely the first channel is in the first channel to the receiving state, and the N channel is in the second channel receiving state, and the APD channel is continuously switched from the first channel to the second channel receiving state, and the APD channel receiving state is finished, and the channel receiving system is completed after the channel receiving state is completed sequentially. The N channels formed by N APD devices are used for detection, the N times of detection rate can be increased, the efficiency is mainly dependent on the light path switching speed and the channel number N, the performance index required by each APD can be greatly reduced, and the requirements of a high-speed single photon detection system above GHz can be completely met by using the existing APD devices, so that the contradiction between the reduction of dead time, the improvement of the count repetition rate and the reduction of dark counts after the reduction of pulse probability is solved.
The direct-current bias voltage circuit 11 provides direct-current high-voltage reverse bias signals for the parallel APD array, and normally the output voltage is controlled through a digital interface, and the output voltage range is 40-50V.
The high-speed pulse gating timing signal circuit 12 supplies a high-speed pulse gating signal and a gating timing signal to the parallel APD array, supplies the pulse gating signal to the parallel APD array using a high-frequency power signal source and a high-frequency power amplifier, and generates N high-speed gating timing signals divided by N by the pulse gating signal, which are sequentially 1/N period phase differences with each other, as a channel switching timing control signal to the parallel APD array, and simultaneously as a synchronization reference signal to the multi-channel optical switch 13.
The multi-channel optical switch 13 is implemented by a high-speed electro-optical modulator and a field programmable logic device FPGA circuit, where the number N of channels is typically 4, 8, 16, 32, etc. The time sequence signal of the multichannel optical switch 13 is obtained by a synchronous reference signal output by the high-speed pulse gating time sequence signal circuit 12, and the switching function of channels is realized through an FPGA circuit and an electro-optical modulator.
The multistage low-pass filter circuit 21 is a multistage LC passive microwave low-pass filter, the cut-off frequency is about 10% lower than the frequency of the high-speed pulse gating signal, the insertion loss is less than 6dB, and the out-of-band attenuation is greater than 80dB. The high-speed broadband amplifier used by the high-speed broadband amplifying circuit 22 is an inverting amplifier with a bandwidth of 100 MHz-3GHz, the gain is more than 30dB, and the maximum output power is 10dBm.
The high-speed comparator 30 uses a high-speed comparator for comparing avalanche signals, and converts the electric signals amplified by the signal detection circuit 20 into digital signals after comparison by the high-speed comparator, wherein the highest turnover frequency is 5GHz, and the comparison level is adjustable within the range of-10 mV to-1V.
The digital signal discrimination circuit uses a high-speed discriminator for discriminating avalanche signals, and the discrimination level is digital and continuously adjustable; the counter counts the avalanche signal using a counter above 200 MHz.
The digital signal output circuit provides various types of digital signal outputs such as TTL, NIM and the like.
Example 1
The parallel APD array consists of 8 discrete InGaAs/InP APD devices, i.e., the channel number N is 8. APDs in the parallel APD array are InGaAs/InP APDs of ETX40 model of JDSU corporation, with a minimum bandwidth of 1.6GHz and an avalanche voltage of 46.2V.
The high-speed pulse gating timing signal circuit 12 provides a high-speed pulse gating signal and a gating timing signal to the parallel APD array, the high-frequency power signal source adopts a high-frequency signal source of model N5181A, the signal is amplified in power by using a 12.5GHz broadband power amplifier of model 5865, the pulse gating signal is provided to the parallel APD array, the pulse repetition frequency is 1.6GHz, the pulse width is about 310ps, and the output amplitude is 6.2Vp-p. And meanwhile, N frequency division is carried out on the pulse gating signals to generate N high-speed gating time sequence signals, the N gating time sequence signals are mutually and sequentially provided with 1/N period phase difference, and because the channel number N is 8, the gating time sequence signals provided for the parallel APD array are 8 high-speed gating pulse signals with smaller jitter, the 8 gating pulse signals are mutually and sequentially provided with 1/8 period phase difference, and the phase difference is used as a time sequence control signal for channel switching and is simultaneously provided for the multi-channel optical switch 13 as a synchronous reference signal.
The multi-channel optical switch 13 is realized by a high-speed electro-optical modulator and a field programmable logic device FPGA circuit, an LTA series multi-channel high-speed electro-optical modulator M360, an FPGA device with the model of EP1C6T144C8N and a peripheral circuit are adopted to finish, the time sequence signal of the multi-channel optical switch 13 is obtained by a synchronous reference signal output by a high-speed pulse gate control time sequence signal circuit 12, and the channel switching function is realized by the FPGA circuit and the electro-optical modulator. In the experiment, the number of channels N is 8, so the multi-channel optical switch 13 provides an 8-channel optical switch time sequence switching control function.
The multi-stage low-pass filter circuit 21 in the signal detection circuit 20 is a multi-stage LC passive microwave low-pass filter, a 2×15-stage LC passive microwave low-pass filter is adopted, the 1dB turning frequency is 1.45GHz, the insertion loss is less than 5dB, and the attenuation at the 1.6GHz position is 103dB.
The high-speed broadband amplifier used by the high-speed broadband amplifying circuit 22 in the signal detecting circuit 20 is an adjustable gain broadband amplifier ADL5330, the bandwidth is 10MHz-3ghz, the 60db gain adjustable range is [email protected], and the maximum output power is 5dBm.
The high-speed comparator circuit 30 uses a high-speed comparator to convert the electric signal amplified by the signal detection circuit 20 into a digital signal, and adopts the high-speed comparator ADCMP573, the propagation delay 150 ps and the minimum pulse width 80 ps.
The digital signal discrimination circuit uses a high-speed discriminator to discriminate avalanche signals, adopts a discriminator with the model of 9307, has the minimum pulse width of 400ps and the discrimination level of-200 mV and the highest turning frequency of 5GHz, and has the discrimination level adjustable within the range of-10 mV to-1V. Which outputs TTL or NIM levels with a pulse width of 10ns.
The avalanche signal is counted with a counter model 9308.
The digital signal output circuit provides various types of digital signal outputs such as TTL, NIM and the like.
Example parameters: the pulse gating signal frequency of 1.6GHz is used for measurement, the repetition frequency of the infrared single photon detection system of the parallel APD array structure of 8 channels is 1000MHz, and the detection efficiency is 10.0%.
In summary, the parallel APD array formed by a plurality of discrete APD devices is used to convert a single photon signal into an avalanche electric signal, the parallel APD array is operated in a geiger mode by using the direct-current bias voltage circuit 11, and the channel time sequence switching function of the parallel APD array is realized by using the high-speed pulse gate time sequence signal circuit 12 and the multi-channel optical switch 13, so that the dead time of the APD devices is reduced; the infrared single photon detection system with the parallel APD array structure overcomes the post-pulse effect of the detector and effectively improves the working frequency and the detection efficiency of the detector.
Claims (6)
1. An infrared single photon detection system of a parallel avalanche photodiode array structure, which is characterized in that: the device comprises a parallel APD array driving circuit (10) for driving a parallel APD array, wherein the output end of the parallel APD array driving circuit is connected with the control input end of the parallel APD array, the output end of the parallel APD array is connected with the input end of a signal detection circuit (20) for converting single photon signals output by the parallel APD array into avalanche electric signals and extracting the avalanche electric signals, the output end of the signal detection circuit (20) is connected with the input end of an analog-to-digital conversion circuit for converting the extracted avalanche electric signals into digital signals, the output end of the signal analog-to-digital conversion circuit is connected with the input end of a signal processing circuit (40) for screening detection and counting of the converted digital signals, and the output end of the signal processing circuit (40) is connected with the input end of a digital signal output circuit;
the parallel APD array is formed by a plurality of APD devices in a separated mode to form a parallel array structure, or a plurality of APD chips are integrated on the same chip to be packaged into a device; the parallel APD array comprises two control input ends and an output end, wherein a direct-current bias voltage signal is input as a first control input end, an alternating-current gate bias signal is input as a second control input end, and an avalanche electric signal is output as an output end;
the parallel APD array driving circuit (10) consists of a direct-current bias voltage circuit (11), a high-speed pulse gating time sequence signal circuit (12) and a multi-channel optical switch (13), the signal detection circuit (20) consists of a multi-stage low-pass filter circuit (21) and a high-speed broadband amplifying circuit (22), the analog-digital conversion circuit adopts a high-speed comparison circuit (30), and the signal processing circuit (40) consists of a digital signal discrimination circuit and a counter; the output end of the direct current bias voltage circuit (11) is connected with a first control input end of the parallel APD array, the output end of the high-speed pulse gating time sequence signal circuit (12) is connected with a second control input end of the parallel APD array, the output end of the parallel APD array is connected with a first input end of the multi-channel optical switch (13), the output end of the high-speed pulse gating time sequence signal circuit (12) is also connected with a second input end of the multi-channel optical switch (13), the output end of the multi-channel optical switch (13) is connected with the input end of the multi-stage low-pass filter circuit (21), the output end of the multi-stage low-pass filter circuit (21) is connected with the input end of the high-speed broadband amplifying circuit (22), the output end of the high-speed broadband amplifying circuit (22) is connected with the input end of the high-speed comparison circuit (30), the output end of the high-speed comparison circuit (30) is connected with the input end of the digital signal discrimination circuit, the output end of the digital signal discrimination circuit is connected with the input end of the counter, and the output end of the counter is connected with the input end of the digital signal discrimination circuit.
2. The infrared single photon detection system of a parallel avalanche photodiode array structure of claim 1, wherein: the direct current bias voltage circuit (11) comprises a chip U3, a MOS transistor T1, a fast rectifying diode D1, a filter inductor L8, resistors R51-R57, capacitors C62-C64 and filter capacitors C65-C70, wherein the chip U3 is a PWM switch control chip UC3845, the resistor R53 is connected with the capacitor C62 in parallel, two ends of the parallel end are respectively connected with 1 and 2 pins of the chip U3, the 2 pins of the chip U3 are respectively connected with one end of the resistor R51 and one end of the resistor R52, the 4 pin of the chip U3 is connected with one end of the resistor R54, the 3 pin of the chip U3 is grounded through the capacitor C64, the 8 pin of the chip U3 is grounded through the filter capacitor C65, the 7 pin of the chip U3 is respectively grounded through the filter capacitor C66 and the filter capacitor C67, the 6 pin of the chip U3 is connected with the 4 pin of the MOS transistor T1 through the resistor R56, the 5 pin of the chip U3 is respectively connected with the 1, the 2 pins of the MOS transistor T1, the 3 pin of the diode T6 and the diode D5 are respectively connected with the fast rectifying diode D1, the fast rectifying diode D1 is connected with the parallel end of the filter diode D1, and the fast rectifying diode D1 is connected with the fast rectifying diode D1, and the fast rectifying diode is connected with the fast rectifying diode is stable.
3. The infrared single photon detection system of a parallel avalanche photodiode array structure of claim 1, wherein: the high-speed pulse gate control time sequence signal circuit (12) comprises a chip U5, a resistor R50, power supply filter capacitors C56-C59 and signal coupling capacitors C60-C61, wherein the chip U5 is a 12.5GHz broadband power amplifier, and a 1 foot of the chip U5 is grounded through the power supply filter capacitors C56 and C59 which are connected in parallel; the 3 pin is grounded through parallel power supply filter capacitors C57 and C58; the 7 pin of the power supply is grounded; the 8 pin of the high-speed pulse gate-controlled optical switch is respectively connected with one end of a signal coupling capacitor C60 and one end of a resistor R50, the other end of the signal coupling capacitor C60 is connected with a high-frequency signal source signal provided by the outside, the other end of the resistor R50 is grounded, the 9 pin of the chip U5 is connected with one end of a signal coupling capacitor C61, and the other end of the signal coupling capacitor C61 is used as an output end of a high-speed pulse gate-controlled time sequence signal circuit (12) and is respectively connected with a second control input end of a parallel APD array and a second input end of a multichannel optical switch (13).
4. The infrared single photon detection system of a parallel avalanche photodiode array structure of claim 1, wherein: the multichannel optical switch (13) comprises a chip U4, an active crystal oscillator Y40, filter inductors L6-L7, power supply filter capacitors C40-C55 and resistors R40-R45, wherein the chip U4 adopts a programmable FPGA controller with the model of EP1C6T144C8N, the chip U4 comprises a chip U4A and a chip U4B, a 10 pin of the chip U4A is connected with a 3 pin of the active crystal oscillator Y40 through the resistor R40, a 2 pin of the active crystal oscillator Y40 is grounded, a 4 pin of the active crystal oscillator Y40 is respectively connected with one end of the resistor R44 and one end of the power supply filter capacitor C55, the other end of the power supply filter capacitor C55 is grounded, the power supply filter capacitors C40, C42 and C44 are connected in parallel, the parallel end of the chip U4A is respectively connected with one end of the filter inductor L6, the other end of the filter inductor L6 is connected with one end of the power supply filter capacitor C46, and the other end of the power supply filter capacitor C46 is grounded; the power supply filter capacitors C41, C43 and C45 are connected in parallel, and a parallel end of the power supply filter capacitors C41, C43 and C45 is respectively connected with the pin 29 of the chip U4A and one end of the filter inductor L7, the other end of the filter inductor L7 is connected with one end of the power supply filter capacitor C47, and the other end of the power supply filter capacitor C47 is grounded; the power supply filter capacitors C52, C53 and C54 are connected in parallel, one end of the parallel end is connected with the pin 81 of the chip U4B, and the other end is grounded; pin 73 of the chip U4B is used as a first input end of the multichannel optical switch (13) and is connected with an output end of the parallel APD array, pin 105 of the chip U4B is used as a second input end of the multichannel optical switch (13) and is connected with an output end of the high-speed pulse gate control time sequence signal circuit (12), and pins 61, 62 and 67-72 of the chip U4B are used as output ends of the multichannel optical switch (13) and are connected with an input end of the multistage low-pass filter circuit (21).
5. The infrared single photon detection system of a parallel avalanche photodiode array structure of claim 1, wherein: the multistage low-pass filter circuit (21) comprises 15 stages of LC passive microwave low-pass filters LPF 1-LPF 2, a resistor R1, an inductor L1 and capacitors C1-C2, the high-speed broadband amplifying circuit (22) comprises a chip U1, inductors L2-L3, resistors R2-R3 and capacitors C3-C19, the chip U1 adopts an adjustable gain broadband amplifier ADL5330, the 1 foot of the adjustable gain broadband amplifier is respectively connected with one ends of the capacitors C19 and C3, and the other ends of the capacitors C19 and C3 are grounded; the 24 pins are respectively connected with one ends of the resistors R2 and R3, and the other end of the resistor R3 is grounded; the pin 16 is respectively connected with one end of an inductor L2 and one end of a capacitor C17, the other end of the capacitor C17 is used as an output end of a high-speed broadband amplifying circuit (22), the other end of the capacitor C17 is connected with an input end of a high-speed comparison circuit (30), the capacitors C11 and C12 are connected in parallel, the other end of the inductor L2 is respectively connected with one end parallel end of an inductor L3 and one end parallel end of the capacitors C11 and C12, and the other ends of the capacitors C11 and C12 are grounded in parallel; the 15 pin is respectively connected with one end of the inductor L3 and one end of the capacitor C18, and the other end of the capacitor C18 is grounded; the input end of the 15-stage LC passive microwave low-pass filter LPF1 is connected with one end of a capacitor C2, the other end of the capacitor C2 is connected with one end of an inductor L1, the inductor C2 is used as the input end of a multi-stage low-pass filter circuit (21) and is connected with the output end of a multi-channel optical switch (13), the other end of the inductor L1 is grounded through a resistor R1 and the capacitor C1 in sequence, the output end of the 15-stage LC passive microwave low-pass filter LPF1 is connected with the input end of the 15-stage LC passive microwave low-pass filter LPF2, and the output end of the 15-stage LC passive microwave low-pass filter LPF2 is connected with the 3 pin of the chip U1 through a capacitor C4 and a capacitor C6 in sequence.
6. The infrared single photon detection system of a parallel avalanche photodiode array structure of claim 1, wherein: the high-speed comparison circuit (30) comprises a chip U2, an inductor L4, resistors R5-R11 and capacitors C21-C31, wherein the chip U2 adopts a high-speed comparator ADCMP573, the pin 2 of the high-speed comparison circuit is used as the input end of the high-speed comparison circuit (30) and is respectively connected with one end of the resistor R5 and the output end of the high-speed broadband amplifying circuit (22), and the other end of the resistor R5 is grounded; the 3 pin is respectively connected with one end of an inductor L4 and one end of a capacitor C22, the inductor L4 is grounded through a capacitor C21, and the other end of the capacitor C22 is grounded; the 11 pin is used as the output end of the high-speed comparison circuit (30) and is connected with the input end of the digital signal discrimination circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610247486.8A CN107271055B (en) | 2016-04-20 | 2016-04-20 | Infrared single photon detection system of parallel avalanche photodiode array structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610247486.8A CN107271055B (en) | 2016-04-20 | 2016-04-20 | Infrared single photon detection system of parallel avalanche photodiode array structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107271055A CN107271055A (en) | 2017-10-20 |
| CN107271055B true CN107271055B (en) | 2023-04-25 |
Family
ID=60052976
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610247486.8A Active CN107271055B (en) | 2016-04-20 | 2016-04-20 | Infrared single photon detection system of parallel avalanche photodiode array structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107271055B (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108168717B (en) * | 2017-12-13 | 2020-06-23 | 中国科学院光电技术研究所 | Photon number resolution balance detector |
| US10775486B2 (en) | 2018-02-15 | 2020-09-15 | Velodyne Lidar, Inc. | Systems and methods for mitigating avalanche photodiode (APD) blinding |
| CN109100018B (en) * | 2018-07-26 | 2021-08-03 | 传周半导体科技(上海)有限公司 | Large-dynamic-range weak light detection system based on avalanche photodiode array chip |
| CN109347544B (en) * | 2018-07-26 | 2021-12-07 | 传周半导体科技(上海)有限公司 | Optical fiber time domain reflectometer based on ultra-low noise near-infrared single photon detection system |
| CN109253807B (en) * | 2018-10-11 | 2020-10-13 | 传周半导体科技(上海)有限公司 | Low-noise single photon detection chip and system based on standard integrated circuit process |
| CN109799496B (en) * | 2018-11-14 | 2024-06-14 | 光微信息科技(合肥)有限公司 | Concurrency detection circuit, photon detector, pulse TOF sensor and implementation method thereof |
| CN109391251B (en) * | 2018-11-21 | 2024-04-19 | 深圳市亚派光电器件有限公司 | Avalanche photodiode driving circuit and device |
| CN109688671B (en) * | 2018-12-25 | 2020-04-10 | 重庆门里科技有限公司 | Light control method |
| CN110779683B (en) * | 2019-10-18 | 2022-03-08 | 成都成电光信科技股份有限公司 | SPAD (spatial temporal mapping) based on OTDR (optical time Domain reflectometer) gated optical detection and control method |
| CN111006661B (en) * | 2019-12-18 | 2021-09-07 | 中国科学院武汉物理与数学研究所 | Measurement method and measurement device for eliminating dead time of cold atom interferometer |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101170362A (en) * | 2007-11-08 | 2008-04-30 | 华东师范大学 | APD single photon detection circuit module |
| JP2009238935A (en) * | 2008-03-26 | 2009-10-15 | Nec Corp | Optical detecting circuit and optical detector, device and system using the same, and control method for bias power source |
| CN101650228A (en) * | 2009-09-21 | 2010-02-17 | 安徽问天量子科技股份有限公司 | Gigahertz impulse gate-control low-pass filtering ultrared single-photon detector |
| CN102590159A (en) * | 2011-01-11 | 2012-07-18 | 中国科学院物理研究所 | Transient fluorescence lifetime measurement method and measurement system based on single photon counting |
-
2016
- 2016-04-20 CN CN201610247486.8A patent/CN107271055B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101170362A (en) * | 2007-11-08 | 2008-04-30 | 华东师范大学 | APD single photon detection circuit module |
| JP2009238935A (en) * | 2008-03-26 | 2009-10-15 | Nec Corp | Optical detecting circuit and optical detector, device and system using the same, and control method for bias power source |
| CN101650228A (en) * | 2009-09-21 | 2010-02-17 | 安徽问天量子科技股份有限公司 | Gigahertz impulse gate-control low-pass filtering ultrared single-photon detector |
| CN102590159A (en) * | 2011-01-11 | 2012-07-18 | 中国科学院物理研究所 | Transient fluorescence lifetime measurement method and measurement system based on single photon counting |
Non-Patent Citations (1)
| Title |
|---|
| 刘俊良 ; 李永富 ; 张春芳 ; 王祖强 ; 方家熊 ; .基于APD-PIN结电容平衡电路的门控单光子探测器.红外与激光工程.2015,第44卷(第11期),全文. * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107271055A (en) | 2017-10-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107271055B (en) | Infrared single photon detection system of parallel avalanche photodiode array structure | |
| CN102735351B (en) | Single-photon detector circuit and detection method thereof | |
| CN102155998B (en) | Fully-integrated high-speed single photon detecting system and detecting method | |
| CN106940221B (en) | Avalanche signal discrimination method and device and infrared single-photon detector | |
| CN101650228A (en) | Gigahertz impulse gate-control low-pass filtering ultrared single-photon detector | |
| CN107014495A (en) | The high-speed low-noise single-photon detector of ultrashort pulse gate | |
| CN102230828B (en) | Method for detecting gigahertz single photon with low time jitter and low noise | |
| CN107167251A (en) | A kind of single-photon detector based on high frequency sinusoidal gate pulse pattern | |
| CN103115688B (en) | Gigahertz sine gating near-infrared single photon detector with tunable frequency | |
| CN103759840A (en) | Semiconductor infrared single-photon detector snow slide signal screening device and method | |
| CN112556841B (en) | Near-infrared single-photon detector integrating gating passive quenching technology and active quenching technology | |
| CN108168717B (en) | Photon number resolution balance detector | |
| CN205642637U (en) | Parallel avalanche photodiode array structure's infrared single -photon detection system | |
| CN201497580U (en) | GHz pulse door control low-pass filter infrared single-photon detector | |
| CN107036722A (en) | The high-speed low-noise single-photon detection system of ultrashort pulse gate | |
| CN114264383B (en) | High-efficiency single photon detection system and method applied to surface array up-conversion camera | |
| CN104990632A (en) | Gate control difference single-photon detection system | |
| CN111351586B (en) | Integrated low-delay active quenching near-infrared single-photon detector | |
| Acconcia et al. | 37ps-precision time-resolving active quenching circuit for high-performance single photon avalanche diodes | |
| CN109521282A (en) | Microwave list quantum detector based on Microwave Optics modulator | |
| Liang et al. | Room-temperature single-photon detector based on InGaAs/InP avalanche photodiode with multichannel counting ability | |
| Cova et al. | Semiconductor-based detectors | |
| CN110987201A (en) | Method and device for realizing single photon detector dead time control circuit | |
| CN206804152U (en) | A kind of single-photon detector of frequency-tunable | |
| CN209542712U (en) | Microwave list quantum detector based on Microwave Optics modulator |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |