CN212906039U

CN212906039U - Low-voltage and low-power-consumption reference circuit

Info

Publication number: CN212906039U
Application number: CN202021871879.4U
Authority: CN
Inventors: 许建超; 孙添平; 戴贵荣; 戴庆田
Original assignee: Shenzhen Aixiesheng Technology Co Ltd
Current assignee: Shenzhen Aixiesheng Technology Co Ltd
Priority date: 2020-08-29
Filing date: 2020-08-29
Publication date: 2021-04-06
Anticipated expiration: 2030-08-29

Abstract

The utility model discloses a low pressure, low-power consumption reference circuit, belong to reference circuit technical field, it meets with the VCC to produce the circuit including PTAT, PTAT produces the circuit and meets with MP2, MP2 one end meets with the VCC, the other end and VREF, resistance R2 and resistance R3 are parallelly connected, resistance R2 meets with the BJT pipe Q1's of ground connection base and collecting electrode, resistance R3 ground connection, this structure can export the zero temperature coefficient reference voltage who is less than 1V, this structure can work under lower mains voltage simultaneously, can be close to a Vbe minimum, about 0.6V, the restriction that minimum working power supply voltage received zero temperature reference voltage has been eliminated, output voltage's temperature coefficient and voltage absolute value's calibration method and corresponding flow have still been given simultaneously.

Description

Low-voltage and low-power-consumption reference circuit

Technical Field

The utility model relates to a reference circuit technical field, in particular to low pressure, low-power consumption reference circuit.

Background

The reference voltage and current, which are modules essential to almost all chips, are critical to their function. The circuit always operates based on some reference (voltage reference, i.e. reference voltage; current reference, i.e. reference current; clock reference, usually a crystal oscillator). In some battery-powered devices, low power consumption, small area, and as low an operating voltage as possible are always desired, and therefore high demands are placed on the design of each module. The particularity of the reference voltage and reference current generating module is generally designed to work when being powered on and cannot be turned off, so that the requirements on low power consumption and low voltage are more strict. In the design of these low power consumption chips, a reference circuit implemented by using MOS transistors operating in a sub-threshold region is widely used.

As shown in fig. 1 and 2, as shown in fig. 1. In the prior art, a low-power reference circuit implemented based on a sub-threshold region MOS transistor generally generates a current proportional to absolute temperature, which is called a PTAT current, and then copies the PTAT current and flows through a resistor R2 and a BJT Q1 connected in series to generate a zero temperature coefficient reference voltage VREF.

The principle of generating VREF can be explained by the following equation:

wherein

N is the scaling factor (usually 4) of the NMOS current mirror (not shown in the figure) in the circuit;

where N is the scaling factor (usually 4) of the NMOS current mirror (not shown) in the circuit, assuming that MP1 and MP2 are mirrored at a ratio of 1: 1.

In this expression, the first term Vbe, which is the Vbe voltage of the BJT transistor, can be written as:

Vbe＝Vg0-αT

where Vg0 is referred to as the forbidden band voltage, is a physical constant associated with silicon materials, approximately 1.2V, independent of PVT. α is the temperature coefficient of Vbe, which is approximately-2 mV/deg.C.

Second item

Is a positive temperature coefficient term, proportional to absolute temperature, called PTAT term. By adjusting the ratio

The size of the positive temperature coefficient can be adjusted; in particular when

With 0.6V, the positive temperature coefficient of the second term is approximately +2 mV/deg.C, just canceling out the negative temperature coefficient of Vbe. After temperature compensation, the expression of VREF is:

VREF＝V_g0-αT+αT≈1.2V

if a zero temperature coefficient reference voltage is generated, the reference voltage must be around 1.2V, otherwise it is not a zero temperature coefficient. If the reference output is 1.2V, the minimum supply voltage is increased by at least one overdrive voltage Vod (about 0.2V), i.e. 1.4V, of the PMOS transistor. The existing architecture is certainly not feasible if we want to achieve a minimum operating supply voltage below 1V, while at the same time want to be able to output an arbitrary zero temperature coefficient reference voltage of less than 1V.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a low pressure, low-power consumption reference circuit has eliminated minimum operating power supply voltage and has received zero temperature reference voltage's restriction, and this structure can export the zero temperature coefficient reference voltage that is less than 1V to this structure can work under lower mains voltage, the temperature coefficient of output voltage and the calibration method and the corresponding flow of voltage absolute value simultaneously, with the problem of proposing in solving above-mentioned background art.

In order to achieve the above object, the utility model provides a following technical scheme: a low-voltage and low-power consumption reference circuit comprises a PTAT generating circuit connected with VCC, a MP2, a MP2 with one end connected with VCC and the other end connected with VREF, a resistor R2 and a resistor R3 in parallel, a resistor R2 connected with the base and collector of a BJT Q1 which is grounded, and a resistor R3 grounded.

Preferably, the PTAT generation circuit includes a resistor R1 and a current mirror, and the output node column current conservation equation is:

solving to obtain:

VREF expression is multiplied by a resistance voltage division ratio

Thus, it is possible to achieve arbitrary scaling of the voltage, by design, by selection

The ratio, the expression in brackets is designed as zero temperature coefficient, which is about 1.2V according to the previous theory; if the 0.8V reference needs to be output, the reference can be taken

R3 is 2R2, and a plurality of reference voltages can be output by selecting different taps using R3 resistors.

Compared with the prior art, the beneficial effects of the utility model are that:

the utility model provides a low pressure, low-power consumption reference circuit, this structure can export the zero temperature coefficient reference voltage that is less than 1V, this structure can work under lower mains voltage simultaneously, can be close to a Vbe minimum, about 0.6V, eliminated minimum operating power supply voltage and received zero temperature reference voltage's restriction, this structure can export the zero temperature coefficient reference voltage that is less than 1V, and this structure can work under lower mains voltage, the calibration method and corresponding flow of the temperature coefficient and the voltage absolute value of output voltage simultaneously.

Drawings

FIG. 1 is a prior art reference voltage with zero temperature coefficient generated by a PTAT current;

FIG. 2 is a schematic of a prior art PTAT current generating a zero temperature coefficient reference voltage;

FIG. 3 is a low voltage and low power reference circuit structure of the present invention;

FIG. 4 illustrates a method of outputting one or more lower reference voltages according to the present invention;

fig. 5 is a detailed structural diagram of a first embodiment of the present invention;

fig. 6 is a structural view of a second embodiment of the present invention;

fig. 7 is a graph showing the variation of VREF with temperature T according to the present invention;

fig. 8 is a specific structural diagram of a second embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

The first embodiment is as follows:

referring to fig. 3, a low voltage and low power consumption reference circuit includes a PTAT generating circuit connected to VCC, a PTAT generating circuit connected to MP2, a MP2 having one end connected to VCC and the other end connected in parallel to VREF, a resistor R2 and a resistor R3, a resistor R2 connected to the drain and gate of a BJT Q1, and a resistor R3 connected to ground.

Referring to fig. 4, the PTAT generation circuit includes a resistor R1 and a current mirror, and the conservation equation for the output node column current is:

solving to obtain:

VREF expression is multiplied by a resistance voltage division ratio

Thus enabling arbitrary scaling of the voltage. In design, by selection

If a lower reference voltage or a plurality of reference voltages are to be output, the R3 is 2R2, and only voltages need to be taken from different taps of the R3 resistor. For example, as shown in fig. 4, if R3 is split into 3 resistors of R3/3 resistance value connected in series and tap voltages V1 and V2 are taken out from the middle, V1 is 1/3VREF and V2 is 2/3 VREF; if VREF is 0.9V, V1 is 0.3V, and V2 is 0.6V. Any other voltage may be generated by appropriate division of R3.

Referring to fig. 5, a low voltage, low power consumption reference voltage generation circuit is provided by adding R3.

MN0 and MN1 are NMOS current mirrors with a typical ratio of 4:1, and need to be designed to operate in the subthreshold region (W/L is large enough, e.g., MN0 is 20u/1u, MN1 is 20u/1u x4, and the current is 500 nA).

The lowest working power voltage of the PTAT current generation part is extremely low, and the PTAT current generation part can normally work (about 0.6V) just under the threshold voltage of one MOS tube, so the PTAT current generation part is not a bottleneck. The lowest operating supply voltage is limited to the output, i.e., the generating branch of VREF. If VREF is 0.8V and Vod of MP2 is 0.2V, the lowest operating power voltage is 0.8+0.2 is 1.0V, which is greatly reduced compared to the prior art.

Referring to fig. 7, generally, the deviation of the temperature coefficient is mainly caused by fixed factors such as Model misalignment, chip stress, material characteristics, etc., and is not greatly affected by process deviation and device mismatch. Therefore, the deviation of the temperature coefficient usually appears as one integral deviation, and the dispersion is small. This means that if the correct temperature coefficient can be found, this temperature coefficient can be approximated for all chips (at least chips of this batch).

Example two:

is an adoption the utility model provides a new technology increases adjustable resistance R3's low pressure, low-power consumption reference voltage and produces the circuit.

Referring to FIG. 8, MN0 and MN1 are NMOS current mirrors with a typical ratio of 4:1, designed to operate in the subthreshold region (W/L is large enough, e.g., MN0 is 20u/1u, MN1 is 20u/1u x4, current is 500 nA).

Wherein R2 and R3 have a digital programming interface. Adopt the utility model provides a calibration method can be zero temperature coefficient with the calibration of output reference voltage to the absolute value is the default, is less than 1.2V's arbitrary voltage.

In summary, the following steps: the utility model discloses a low pressure, low-power consumption reference circuit, this structure can export the zero temperature coefficient reference voltage that is less than 1V, this structure can work simultaneously under lower mains voltage, can be close to a Vbe minimum, about 0.6V, eliminated minimum operating source voltage and received the restriction of zero temperature reference voltage, this structure can export the zero temperature coefficient reference voltage that is less than 1V, and this structure can work under lower mains voltage, the calibration method and the corresponding flow of the temperature coefficient and the voltage absolute value of output voltage simultaneously.

The above description is only the specific implementation manner of the preferred embodiment of the present invention, but the protection scope of the present invention is not limited thereto, and any person skilled in the art can substitute or change the technical solution of the present invention and the design of the present invention within the technical scope of the present invention.

Claims

1. A low-voltage and low-power consumption reference circuit is characterized by comprising a PTAT generating circuit connected with VCC, a MP2, an MP2 with one end connected with VCC and the other end connected with VREF, a resistor R2 and a resistor R3 in parallel, a resistor R2 connected with the drain and the gate of a BJT Q1 which is grounded, and a resistor R2 grounded.