CN212447387U

CN212447387U - Novel domain controller

Info

Publication number: CN212447387U
Application number: CN202020678746.9U
Authority: CN
Inventors: 孙博苗; 田锋; 付玉堂; 李智华; 陈晓钿; 陆津池; 曾广慧; 关锐; 李良淼; 金勇�; 徐康; 靳云昭; 黄龙杰
Original assignee: Inbo Supercomputing Nanjing Technology Co Ltd
Current assignee: Inbo Supercomputing Nanjing Technology Co Ltd
Priority date: 2020-04-28
Filing date: 2020-04-28
Publication date: 2021-02-02
Anticipated expiration: 2030-04-28

Abstract

The utility model discloses a novel domain controller relates to on-vehicle electron technical field, including CPU module, clock module, power module, interface module, MCU module and CPLD module, the CPU module links to each other with MCU module and CPLD module and camera, ultrasonic radar, millimeter wave radar sensor respectively, and the level nonconformity problem that exists when this kind of novel domain controller can solve the controller (CPU MCU) two liang of interconnections of a plurality of different levels. The CPLD device is introduced, so that the design is more convenient and flexible; the CPLD can be used for software encryption, so that the security of the system is higher; in addition, the CPLD is adopted to uniformly manage the power supply clock of the whole system, so that the design is better overall, the IP core inside the CPLD is utilized to carry out level conversion of high-speed signals, the delay is smaller, the design is more convenient and flexible, the integrity and the safety are better, and in addition, the delay of the whole system can be reduced.

Description

Novel domain controller

Technical Field

The utility model relates to an on-vehicle electron technical field specifically is a novel domain controller.

Background

At present, with the improvement of living standard of people and the development of electronic technology, the number of automobiles increases year by year, and the safety problem brought by the automobiles is also particularly prominent. In order to solve the safety problem, the advanced driver assistance system ADAS proposed recently senses the surrounding environment by using various sensors mounted on the vehicle, collects, analyzes and processes data, and makes related warning information to enhance the safety and comfort of the user in the driving process.

The voltage of the existing domain controller in the automobile electronic field is mostly 12V/5V/3.3V, the voltage of the automobile controller is reduced to 1.8V more and even lower because the automobile industry pursues lower power consumption, if old version controller multi-link interconnection is needed, a plurality of level conversion chips are needed to realize, if high-speed signal interconnection is needed, a conversion chip is needed, the price is high, the delay is large, the safety is low, and only one level conversion can be realized.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a novel domain controller to when proposing in solving above-mentioned background art can not a plurality of different level control ware (CPU MCU) two liang of interconnections, the level is inconsistent with the big problem of pressure of whole domain controller system.

In order to achieve the above object, the utility model provides a following technical scheme: a novel domain controller comprises a CPU module, a clock module, a power supply module, an interface module, an MCU module and a CPLD module, wherein the CPU module is respectively connected with the MCU module, the CPLD module, a camera, an ultrasonic radar and a millimeter wave radar sensor, and the CPLD module is interconnected with the CPU, the MCU and the power supply clock module.

Preferably, the interface module comprises an ECU interface, a camera, an ultrasonic radar and a millimeter wave radar sensor.

Preferably, the power supply module is connected with the CPLD module.

Preferably, the CPLDs are classified into BANK1, BANK2, and BANK 3.

Compared with the prior art, the beneficial effects of the utility model are that: the novel domain controller can solve the problem of inconsistent level existing when a plurality of controllers (CPU/MCU) with different levels are connected with each other in pairs. The CPLD device is introduced, so that the design is more convenient and flexible; the CPLD can be used for software encryption, so that the security of the system is higher; in addition, the CPLD is adopted to uniformly manage the power supply clock of the whole system, so that the design is better overall, the IP core inside the CPLD is utilized to carry out level conversion of high-speed signals, the delay is smaller, the design is more convenient and flexible, the integrity and the safety are better, and in addition, the delay of the whole system can be reduced.

Drawings

FIG. 1 is a schematic structural view of the present invention;

FIG. 2 is a detailed block diagram of the present invention;

fig. 3 is a detailed block diagram of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

In the present invention, unless otherwise expressly stated or limited, the terms "disposed," "mounted," "connected," "fixed," "sleeved," and the like are to be construed broadly, e.g., as either a fixed connection, a removable connection, or an integral part; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, can be connected inside two elements or can be in an interaction relationship between the two elements, and the specific meaning of the terms in the present invention can be understood according to specific situations by those skilled in the art

Referring to fig. 1-3, the present invention provides a technical solution: a novel domain controller comprises a CPU module, a clock module, a power supply module, an interface module, an MCU module and a CPLD module, wherein the CPU module is respectively connected with the MCU module, the CPLD module, a camera, an ultrasonic radar and a millimeter wave radar sensor; secondly, encrypting the data communicated between the CPU and the MCU through the CPLD; thirdly, uniformly managing the power supply clock of the whole system by adopting a CPLD; fourthly, level conversion of high-speed signals is carried out by utilizing an IP core inside the CPLD, and delay is smaller; and fourthly, the newly introduced CPLD can be used as an expanded IO, can be externally connected with a VCU module together with an IO port, and can also be newly provided with universal interfaces such as I2C/SPI and the like.

Referring to fig. 2, the interface module includes an ECU interface, a camera, an ultrasonic radar, and a millimeter wave radar sensor, and mainly performs related analysis and integration processing by combining data of the sensor and vehicle body information sent from the MCU, and then sends the data to the MCU. The CPU module receives the camera information and the millimeter wave radar information, analyzes and processes the camera information and the millimeter wave radar information, and can realize the APA function of automatic parking by combining the vehicle body information transmitted by the MCU; according to the camera, the integration of the laser radar millimeter wave radar and the vehicle body data, the ADAS function of self-homing can be realized.

Referring to fig. 3, the power module is connected to the CPLD module, the CPLD module is divided into BANK1, BANK2 and BANK3, the MCU module mainly functions to send car body data to the CPU, perform related execution operations on instructions issued by the CPU, interact with information of the CPU, and may pass through a channel of the MCU-CPU; or through MCU-CPLD-CPU channel.

The working principle is as follows: firstly, when the levels of the interconnection signals of the CPU and the MCU are consistent, the design scheme of fig. 2 is adopted, and the CPLD mainly has the functions of controlling the time sequence of the whole system, simultaneously realizing the information conversion between the CPU and the MCU and encrypting data; in the second scenario, when a plurality of controllers (CPU/MCU) with different levels need to be interconnected two by two, the design scheme of fig. 3 can be adopted, which is more flexible and convenient than the use of level conversion chip, and the price is cheaper.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims

1. A novel domain controller comprises a CPU module, a clock module, a power module, an interface module, an MCU module and a CPLD module, and is characterized in that: the CPU module is respectively connected with the MCU module, the CPLD module, the camera, the ultrasonic radar and the millimeter wave radar sensor, and the CPLD module is interconnected with the CPU, the MCU and the power supply clock module.

2. A new domain controller according to claim 1, characterized by: the interface module comprises an ECU interface, a camera, an ultrasonic radar and a millimeter wave radar sensor.

3. A new domain controller according to claim 1, characterized by: and the power supply module is connected with the CPLD module.

4. A new domain controller according to claim 1, characterized by: the CPLDs are classified into BANK1, BANK2, and BANK 3.