CN211788997U

CN211788997U - TFT array substrate and display panel

Info

Publication number: CN211788997U
Application number: CN202020219723.1U
Authority: CN
Inventors: 董欣; 陈海雷; 张东琪; 柳发霖; 张泽鹏; 马亮
Original assignee: Truly Renshou High end Display Technology Ltd
Current assignee: Truly Renshou High end Display Technology Ltd
Priority date: 2020-02-27
Filing date: 2020-02-27
Publication date: 2020-10-27
Anticipated expiration: 2030-02-27

Abstract

The application discloses a TFT array substrate and a display panel, wherein the TFT array substrate comprises a glass substrate, and a plurality of scanning lines and data lines which are arranged on the glass substrate and positioned in a display area; an insulating layer is arranged between the scanning line and the data line; the scanning line is electrically connected with the GOA driving circuit; each scanning line comprises a plurality of sections of first gate lines, the plurality of sections of first gate lines are connected through second gate lines, and the first gate lines and the second gate lines are respectively located on different layers. The application also discloses a display panel comprising the TFT array substrate. This application is through setting up the scanning line into multistage multilayer metal, and the messenger is located the first GATE line on GATE layer and is multistage metal wire, and in the process of the manufacture procedure, the length of every section first GATE line is shorter, and induction capacitance is little, and the response static of production is little, and then reaches the effect that prevents the static electric shock of manufacture procedure and injures GOA circuit.

Description

TFT array substrate and display panel

Technical Field

The utility model relates to a show technical field, more specifically relate to a TFT array substrate and display panel.

Background

In the process of manufacturing a display product by using glass as a substrate, when the glass is in contact with equipment, static electricity is easily generated. When the static electricity is accumulated to a certain degree, the static electricity is released, and a large circuit current is generated, so that the device is burnt. As shown in fig. 1 and 2, a GATE layer, an insulating layer 40, and an SD layer are sequentially stacked on the glass substrate 10, wherein the GATE layer includes a plurality of scan lines 20 (GATE lines), and the SD layer includes a plurality of data lines 30. Most of the current ultra-narrow frame display products use the GOA driving circuit 50 to drive the GATE voltage, and the AA area scan line (GATE line) is a strip-shaped metal line, which is easy to accumulate static electricity during the manufacturing process. In the process of manufacturing, the anti-static circuit is not yet in action, the scanning line is directly connected with the GOA circuit device, and the GOA device is directly damaged when static electricity is released, so that poor display is caused.

SUMMERY OF THE UTILITY MODEL

In order to solve the above problems, the present invention provides a TFT array substrate, which includes a display area and a non-display area, wherein the non-display area includes a GOA driving circuit;

the TFT array substrate comprises a glass substrate, and a plurality of scanning lines and data lines which are arranged on the glass substrate and positioned in a display area; an insulating layer is arranged between the scanning line and the data line;

the scanning line is electrically connected with the GOA driving circuit; it is characterized in that the preparation method is characterized in that,

each scanning line comprises a plurality of sections of first gate lines, the plurality of sections of first gate lines are connected through second gate lines, and the first gate lines and the second gate lines are respectively positioned on different layers.

Further, the first gate line and the second gate line which are positioned at different layers are electrically connected through the via hole.

Furthermore, a first wiring layer, an insulating layer and a second wiring layer are sequentially stacked on the glass substrate, the first gate line is located on the first wiring layer, and the data line is located on the second wiring layer.

Further, the data line and the second gate line are disposed at the same layer.

Furthermore, the first routing layer and the insulating layer are sequentially stacked on the glass substrate, the first gate line and the data line are located on the first routing layer, and the second gate line is located on the insulating layer.

Further, the lengths of the plurality of first gate lines of each scan line are the same or different.

Further, the lengths of the second gate lines between the plurality of segments of the first gate lines are the same or different.

Further, the scan lines extend in a first direction, and the data lines extend in a second direction, the first direction being different from the second direction.

The utility model also provides a display panel, a serial communication port, display panel includes as above arbitrary the TFT array substrate.

Further, the display panel includes an IC, and the data line is electrically connected to the IC.

Compared with the prior art, the beneficial effects of the utility model are as follows:

the scanning lines are arranged into a plurality of sections of first gate lines, the plurality of sections of first gate lines are connected through second gate lines, and the first gate lines and the second gate lines are located on different layers respectively. The scanning lines are arranged into multiple sections of multilayer metal, so that the first GATE lines on the GATE layer are multiple sections of metal lines, and in the process of manufacturing, the length of each section of first GATE line is shorter, the induction capacitance is small, the generated induction static is small, and the effect of preventing the GOA circuit from being damaged by the static shock of the manufacturing process is achieved.

Drawings

Fig. 1 is a schematic structural diagram of a TFT array substrate of the background art;

FIG. 2 is a partial cross-sectional view of FIG. 1;

fig. 3 is a schematic structural diagram of a TFT array substrate according to a first embodiment of the present disclosure;

FIG. 4 is a partial cross-sectional view of FIG. 3;

fig. 5 is a schematic structural diagram of a TFT array substrate according to a second embodiment of the present application;

fig. 6 is a partial cross-sectional view of fig. 5.

Reference numerals:

10-glass substrate, 20-scanning line, 21-first gate line, 22-second gate line, 23-via hole, 30-data line, 40-insulating layer, 50-GOA drive circuit, 60-IC, 101-display area.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

Fig. 3-6 are drawings of the embodiment of the present invention.

Example one

The embodiment of the utility model provides a TFT array substrate, as shown in FIG. 3, TFT array substrate includes display area 101 and non-display area 101 according to the region. The non-display area 101 includes the GOA driving circuit 50.

As shown in fig. 4, the TFT array substrate includes a glass substrate 10, and a plurality of scan lines 20 (GATE traces) and a plurality of data lines 30 (SD traces) disposed on the glass substrate 10 and located in a display area 101. Wherein an insulating layer 40 is disposed between the scan lines 20 and the data lines 30. The scanning lines 20 are electrically connected to the GOA driving circuit 50.

The plurality of scan lines 20 are parallel and the scan lines 20 extend along a first direction, and the plurality of data lines 30 are parallel and the data lines 30 extend along a second direction. The first direction is different from the second direction, and preferably, the first direction is perpendicular to the second direction, and the plurality of scan lines 20 and the plurality of data lines 30 are in a grid shape.

In the present application, each scan line 20 includes a plurality of segments of first gate lines 21 arranged at intervals. Second gate lines 22 are respectively disposed between the first gate lines 21, and a plurality of segments of the first gate lines 21 are connected by the second gate lines 22. The first gate line 21 and the second gate line 22 are located on different layers.

The present application sets the scanning line 20 as a plurality of segments of first gate lines 21, the plurality of segments of first gate lines 21 are connected by second gate lines 22, and the first gate lines 21 and the second gate lines 22 are respectively located at different layers. In this way, by setting the scanning line 20 as a multi-segment multilayer metal, the first GATE line 21 on the GATE layer is a multi-segment metal line, and during the manufacturing process, because the length of the first GATE line 21 is short, the metal area is small, the inductive capacitance is small, the generated and accumulated inductive static electricity is small, and the amount of the generated and accumulated inductive static electricity cannot reach the amount of damaging the GOA metal, the GOA circuit can be prevented from being damaged by the electrostatic shock in the manufacturing process.

In the present embodiment, a first wiring layer (GATE layer), an insulating layer 40, and a second wiring layer (SD layer) are sequentially stacked on the glass substrate 10, the first GATE line 21 is located on the first wiring layer (GATE layer), and the data line 30 is located on the second wiring layer (SD layer). The first gate line 21 is disposed adjacent to the glass substrate 10. As shown in fig. 4, the data line 30 and the second gate line 22 are disposed on the same layer, and the second gate line 22 is also disposed on the second routing layer (SD layer); it is understood that the second gate line 22 is positioned above the first gate line 21 and is disposed to avoid the data line 30. The first gate line 21 and the second gate line 22 located at different layers are electrically connected through a via 23. The via hole 23 is provided with a conductive substance such as metal therein and thus can be conducted. The two gate lines and the two vias 23 connected thereto form a bridge structure.

The lengths of the plurality of first gate lines 21 of each scan line 20 may be the same or different. The lengths of the second gate lines 22 between the first gate lines 21 may be the same or different.

The manufacturing method of the TFT array substrate comprises the following steps:

first GATE lines 21 of a first routing layer (GATE layer) are formed on a glass substrate 10, and during a manufacturing process, because the first GATE lines 21 are short in length, small in metal area and small in induction capacitance, generated and accumulated induction static electricity is small and cannot reach the amount of damaging the GOA metal, the GOA circuit can be prevented from being damaged by the static electricity during the manufacturing process; thereafter, an insulating layer 40 is formed on the first gate line 21 with a via 23 at a corresponding position of the insulating layer 40; finally, the data line 30 and the second gate line 22 of the SD layer are formed on the insulating layer, and the metal in the via 23 is also formed when the second gate line 22 is formed. When the process of the second routing layer (SD layer) is completed, the first gate line 21 and the second gate line 22 of the scan line 20 are conducted, and the peripheral ESD circuit is also formed as a path, so as to perform the electrostatic discharge function and prevent the devices in the GOA circuit from being damaged.

Example two

Alternatively, the data line 30 and the second gate line 22 may be disposed in different layers. As shown in fig. 5 and 6, unlike the first embodiment, a first wiring layer (GATE layer) and an insulating layer 40 are sequentially stacked on the glass substrate 10, the first GATE line 21 and the data line 30 are located on the first wiring layer, and the second GATE line 22 is stacked on the insulating layer 40. The first gate line 21 is disposed to avoid the data line 30.

The first gate line 21 and the data line 30 are spaced apart from each other. The first gate line 21 and the second gate line 22 located at different layers are electrically connected through a via 23. The second gate line 22 and the two via holes 23 connected thereto form a bridge structure disposed across the data line 30.

It is understood that the bridge structure may span 1 data line 30, or may span multiple data lines 30.

EXAMPLE III

The embodiment also provides a display panel, which comprises the TFT array substrate. The display panel includes an IC60, wherein the data line 30 is electrically connected to an IC 60.

the present application sets the scanning line 20 as a plurality of segments of first gate lines 21, the plurality of segments of first gate lines 21 are connected by second gate lines 22, and the first gate lines 21 and the second gate lines 22 are respectively located at different layers. In this way, the scanning line 20 is formed by multiple multi-layer metal, so that the first GATE line 21 on the GATE layer is formed by multiple metal lines, and in the manufacturing process, the length of each first GATE line 21 is short, the induction capacitance is small, the generated induction static is small, and the effect of preventing the manufacturing process static from damaging the GOA circuit is achieved.

It will be understood that modifications and variations can be made by those skilled in the art in light of the above teachings, and all such modifications and variations are intended to be included within the scope of the appended claims.

Claims

1. A TFT array substrate comprises a display area and a non-display area, wherein the non-display area comprises a GOA driving circuit;

2. The TFT array substrate of claim 1, wherein the first gate line and the second gate line are electrically connected through a via.

3. The TFT array substrate of claim 1, wherein a first wiring layer, an insulating layer, and a second wiring layer are sequentially stacked on the glass substrate, the first gate line is on the first wiring layer, and the data line is on the second wiring layer.

4. The TFT array substrate of claim 3, wherein the data line and the second gate line are disposed in the same layer.

5. The TFT array substrate of claim 3, wherein the first routing layer and the insulating layer are sequentially stacked on the glass substrate, the first gate line and the data line are on the first routing layer, and the second gate line is on the insulating layer.

6. The TFT array substrate of claim 1, wherein the lengths of the plurality of first gate lines of each scan line are the same or different.

7. The TFT array substrate of claim 6, wherein the lengths of the second gate lines between the first gate lines of the plurality of segments are the same or different.

8. The TFT array substrate of claim 1, wherein the scan lines extend in a first direction, and the data lines extend in a second direction, the first direction being different from the second direction.

9. A display panel comprising the TFT array substrate according to any one of claims 1 to 8.

10. The display panel according to claim 9, wherein the display panel includes an IC, and wherein the data line is electrically connected to the IC.