CN211606514U - High-speed serial clock data recovery circuit - Google Patents
High-speed serial clock data recovery circuit Download PDFInfo
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- CN211606514U CN211606514U CN201921096741.9U CN201921096741U CN211606514U CN 211606514 U CN211606514 U CN 211606514U CN 201921096741 U CN201921096741 U CN 201921096741U CN 211606514 U CN211606514 U CN 211606514U
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Abstract
A high-speed serial clock data recovery circuit adopts a charge pump phase-locked loop composed of a bidirectional capture frequency discriminator, a frequency dividing circuit, a CP and an LPF, wherein the external clock frequency is 125MHz, and the phase interval is
The loop is composed of a half-rate numerical control structure guide clock unit, a multiplexing unit, a half-rate phase discriminator and a digital filter. Can realize clock recovery of dataWhen the complex sum data is retimed, the pulse 'burr' phenomenon generated in the transmission process of the traditional CDR circuit is eliminated, meanwhile, the high-speed data stream processing under lower power consumption is realized, the transmission efficiency and the circuit stability are greatly improved, and the method has a good engineering application prospect.
Description
Technical Field
The utility model relates to a data recovery circuit to 2.5 GB/s's high-speed serial transceiver based on high-speed COMS clock designs, the invention belongs to integrated circuit technical field.
Background
The background art is provided only to aid understanding of the technical contents and is not prior art.
In recent years, the performance and scale of a digital integrated circuit are greatly improved, and meanwhile, the rapid development of a network technology brings huge data interaction and information processing work, so that the demand of people for the transmission rate of data is higher and higher, and the problems of communication bandwidth, data bandwidth, power consumption and the like become technical difficulties to be broken through by a data transmission circuit. In addition, data single transmission is often adopted in the existing high-speed data communication, and a synchronous clock signal transmission mode is omitted to reduce hardware cost, however, the method can cause distortion caused by the fact that signal transmission and receiving processes are easily interfered by a plurality of external factors, and meanwhile, pulse 'glitch' phenomena can be generated in the signal transmission process. At present, a traditional clock data recovery circuit is a closed loop system based on analog feedback, and the design has the defects that a feedback link is completed by analog signals, a phase discriminator can be seriously distorted along with the improvement of data flow rate, and a large amount of chip area is consumed by traditional analog circuit devices.
SUMMERY OF THE UTILITY MODEL
The utility model discloses a further optimization improvement to preceding CDR circuit makes its dicyclo half rate CDR circuit that becomes the numerical control source, carries out digital analog hybrid simulation to the circuit via digital filter to the realization is extremely short to the quick accurate phase discrimination of the multiplexing data of external input, level transition time among the pulse processing process, and has eliminated the influence of metastability to the circuit by a wide margin.
The utility model discloses a following technical scheme realizes:
a high-speed serial clock data recovery circuit, characterized by: the circuit adopts a bidirectional capture frequency discriminator, a frequency dividing circuit, a CP and an LPF to form a charge pump phase-locked loop, the external clock frequency is 125MHz, and the phase interval is
The loop is composed of a half-rate numerical control structure guide clock unit, a multiplexing unit, a half-rate phase discriminator and a digital filter.
Preferably, the input quantity is input from the input end of the two-way capture type frequency discriminator, the output end of the two-way capture type frequency discriminator is connected with the input end of the charge pump filter, the output end of the charge pump filter is connected with the input end of the voltage-controlled oscillator, the output end of the voltage-controlled oscillator is connected with the input end of the phase-locked loop, and the output end of the phase-locked loop is connected with the other input end of the two-way capture type frequency discriminator; a multiphase reference clock is arranged between the voltage-controlled oscillator and the phase-locked loop and is input into the quadrature clock generator; the digital filter inputs a phase selection signal to the quadrature clock generator; the clock frequency of the quadrature clock generator is the external clock frequency.
Preferably, the quadrature clock generator inputs the modulated clock signal into a 1:2 demultiplexing circuit, the difference 1:2 demultiplexing circuit has a signal input half-rate phase discriminator, and the other path of signal is input into a serial-parallel conversion circuit; the quadrature clock generator inputs the modulated clock signal into the input serial-parallel conversion circuit; the serial-parallel conversion circuit outputs data and a clock. The circuit units are in work division and cooperation, and phase selection of a reference clock, multiplexing, detection, processing and serial-parallel conversion of input data are achieved together.
Preferably, the digital controlled delay unit (DCD) of the circuit employs a "phase interpolation and selection" scheme, i.e., a clock signal of the PLL loop is interpolated by two, and a quadrature clock and a complementary clock matched in phase are selected by a digital filter to retime the input data.
The demultiplexing unit firstly carries out serial difference 1:2 demultiplexing on an input modulated clock signal, divides the input modulated clock signal into a retiming data signal and a clock complementary signal, simultaneously carries out logic frequency reduction by adopting a CML (constant current level) of a primary current mode, and simultaneously reduces the load pressure of a rear circuit. In the serial-parallel conversion link, the feedback logic is controlled by the data latch to complete dual-mode frequency division and clock duty ratio adjustment, so that the digital CMOS demultiplexing circuit with the selectable mode is realized.
PD and PF are combined data processing units, mainly finish the clock, data after multiplexing the regulation carry on the corrective function. Wherein the PD unit generates a leading or lagging pulse output based on the phase error of the data and the clock. The DF unit is responsible for processing the leading or lagging pulse output by the PD, and outputs a new control signal through the DCD unit after the depth phase selection is carried out.
The circuit adopts a full digital structure and carries out pure phase adjustment mainly by using a phase discriminator. In addition, in order to eliminate the influence of noise on pulse output, a pipeline output Mealy type state machine is arranged in the PD unit, digital-analog hybrid simulation is carried out on the circuit through a digital filter, so that rapid and accurate phase discrimination of externally input multiplexing data is realized, the level conversion time is extremely short in the pulse processing process, and the influence of a metastable state on the circuit is greatly eliminated.
The DF unit circuit selects a random loitering type filter, and is additionally provided with a control circuit and a decoding circuit to generate three groups of nine-bit selection signals. The phase selection algorithm is "binary, sequential lookup" and writes the data signal as a Gray code to filter out the effects of noise. The encoding circuit performs loitering counting of the pulse signal by an up-down counter: the up and down counting is completed in the leading and lagging pulses, respectively, the pulse difference value N is set, and when the difference value between the leading signal and the lagging signal is greater than N, the counting reset control signals out1 and out2 are output.
The utility model has the advantages that:
2. The pulse 'glitch' phenomenon generated in the transmission process of the traditional CDR circuit is eliminated.
3. The high-speed data stream processing under low power consumption is realized, the transmission efficiency and the circuit stability are greatly improved, and the method has a good engineering application prospect.
Drawings
Fig. 1 is a CDR circuit structure diagram of the present invention.
Fig. 2 is a circuit block diagram of the phase interpolator of the present invention.
Detailed Description
A high-speed serial clock data recovery circuit adopts a charge pump phase-locked loop composed of a bidirectional capture frequency discriminator, a frequency dividing circuit, a CP and an LPF, wherein the external clock frequency is 125MHz, and the phase interval is
The loop is composed of a half-rate numerical control structure guide clock unit, a multiplexing unit, a half-rate phase discriminator and a digital filter.
The input quantity is input from the input end of the two-way capture type frequency discriminator, the output end of the two-way capture type frequency discriminator is connected with the input end of the charge pump filter, the output end of the charge pump filter is connected with the input end of the voltage-controlled oscillator, the output end of the voltage-controlled oscillator is connected with the input end of the phase-locked loop, and the output end of the phase-locked loop is connected with the other input end of the two-way capture type frequency discriminator; a multiphase reference clock is arranged between the voltage-controlled oscillator and the phase-locked loop and is input into the quadrature clock generator; the digital filter inputs a phase selection signal to the quadrature clock generator; the clock frequency of the quadrature clock generator is the external clock frequency.
The quadrature clock generator inputs the modulated clock signal into a 1:2 demultiplexing circuit, the difference 1:2 demultiplexing circuit has a signal input half-rate phase discriminator, and the other path of signal is input into a serial-parallel conversion circuit; the quadrature clock generator inputs the modulated clock signal into the input serial-parallel conversion circuit; the serial-parallel conversion circuit outputs data and a clock. The circuit units are in work division and cooperation, and phase selection of a reference clock, multiplexing, detection, processing and serial-parallel conversion of input data are achieved together.
The digital control delay unit (DCD) of the circuit adopts a 'phase interpolation and selection' scheme, namely, the clock signal of a PLL loop is interpolated by two parts, and a quadrature clock and a complementary clock which are matched in phase are selected by a digital filter to retime input data.
The demultiplexing unit firstly carries out serial difference 1:2 demultiplexing on an input modulated clock signal, divides the input modulated clock signal into a retiming data signal and a clock complementary signal, simultaneously carries out logic frequency reduction by adopting a CML (constant current level) of a primary current mode, and simultaneously reduces the load pressure of a rear circuit. In the serial-parallel conversion link, the feedback logic is controlled by the data latch to complete dual-mode frequency division and clock duty ratio adjustment, so that the digital CMOS demultiplexing circuit with the selectable mode is realized.
PD and PF are combined data processing units, mainly finish the clock, data after multiplexing the regulation carry on the corrective function. Wherein the PD unit generates a leading or lagging pulse output based on the phase error of the data and the clock. The DF unit is responsible for processing the leading or lagging pulse output by the PD, and outputs a new control signal through the DCD unit after the depth phase selection is carried out.
The circuit adopts a full digital structure and carries out pure phase adjustment mainly by using a phase discriminator. In addition, in order to eliminate the influence of noise on pulse output, a pipeline output Mealy type state machine is arranged in the PD unit, digital-analog hybrid simulation is carried out on the circuit through a digital filter, so that rapid and accurate phase discrimination of externally input multiplexing data is realized, the level conversion time is extremely short in the pulse processing process, and the influence of a metastable state on the circuit is greatly eliminated.
The DF unit circuit selects a random loitering type filter, and is additionally provided with a control circuit and a decoding circuit to generate three groups of nine-bit selection signals. The phase selection algorithm is "binary, sequential lookup" and writes the data signal as a Gray code to filter out the effects of noise. The encoding circuit performs loitering counting of the pulse signal by an up-down counter: the up and down counting is completed in the leading and lagging pulses, respectively, the pulse difference value N is set, and when the difference value between the leading signal and the lagging signal is greater than N, the counting reset control signals out1 and out2 are output.
Claims (3)
1. A high-speed serial clock data recovery circuit, characterized by: the circuit adopts a bidirectional capture frequency discriminator, a frequency dividing circuit, a CP and an LPF to form a charge pump phase-locked loop, the external clock frequency is 125MHz, and the phase interval is
The loop consists of a half-rate numerical control structure guide clock unit, a multiplexing unit, a half-rate phase discriminator and a digital filter; the input quantity is input from the input end of the two-way capture type frequency discriminator, the output end of the two-way capture type frequency discriminator is connected with the input end of the charge pump filter, the output end of the charge pump filter is connected with the input end of the voltage-controlled oscillator, the output end of the voltage-controlled oscillator is connected with the input end of the phase-locked loop, and the output end of the phase-locked loop is connected with the other input end of the two-way capture type frequency discriminator; a multiphase reference clock is arranged between the voltage-controlled oscillator and the phase-locked loop and is input into the quadrature clock generator; the digital filter inputs a phase selection signal to the quadrature clock generator; the clock frequency of the quadrature clock generator is the external clock frequency.
2. A high speed serial clock data recovery circuit as recited in claim 1, wherein: the quadrature clock generator inputs the modulated clock signal into a 1:2 demultiplexing circuit, the difference 1:2 demultiplexing circuit has a signal input half-rate phase discriminator, and the other path of signal is input into a serial-parallel conversion circuit; the quadrature clock generator inputs the modulated clock signal into the input serial-parallel conversion circuit; the serial-parallel conversion circuit outputs data and a clock.
3. A high speed serial clock data recovery circuit as recited in claim 1, wherein: the digital control delay unit (DCD) of the circuit adopts a 'phase interpolation and selection' scheme, namely, the clock signal of a PLL loop is interpolated by two parts, and a quadrature clock and a complementary clock which are matched in phase are selected by a digital filter to retime input data.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201921096741.9U CN211606514U (en) | 2019-07-12 | 2019-07-12 | High-speed serial clock data recovery circuit |
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| CN201921096741.9U CN211606514U (en) | 2019-07-12 | 2019-07-12 | High-speed serial clock data recovery circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113162643A (en) * | 2021-03-01 | 2021-07-23 | 深圳市国微电子有限公司 | Clock recovery circuit and receiving chip |
| CN116112011A (en) * | 2023-04-12 | 2023-05-12 | 南京美辰微电子有限公司 | SYSREF-free distributed clock architecture for software-definable SOC chip |
-
2019
- 2019-07-12 CN CN201921096741.9U patent/CN211606514U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113162643A (en) * | 2021-03-01 | 2021-07-23 | 深圳市国微电子有限公司 | Clock recovery circuit and receiving chip |
| CN116112011A (en) * | 2023-04-12 | 2023-05-12 | 南京美辰微电子有限公司 | SYSREF-free distributed clock architecture for software-definable SOC chip |
| CN116112011B (en) * | 2023-04-12 | 2023-07-04 | 南京美辰微电子有限公司 | SYSREF-free distributed clock architecture for software-definable SOC chip |
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Granted publication date: 20200929 Termination date: 20210712 |