CN211455723U - Chip integrated with DC coupling capacitor - Google Patents
Chip integrated with DC coupling capacitor Download PDFInfo
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- CN211455723U CN211455723U CN202020437179.8U CN202020437179U CN211455723U CN 211455723 U CN211455723 U CN 211455723U CN 202020437179 U CN202020437179 U CN 202020437179U CN 211455723 U CN211455723 U CN 211455723U
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- 239000003990 capacitor Substances 0.000 title claims abstract description 58
- 238000010168 coupling process Methods 0.000 title claims abstract description 28
- 230000008878 coupling Effects 0.000 title claims abstract description 27
- 238000005859 coupling reaction Methods 0.000 title claims abstract description 27
- 238000004806 packaging method and process Methods 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
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Abstract
The application discloses a chip integrated with a DC coupling capacitor. The chip is provided with a first end and a second end, the first end is electrically connected with the first end of the first impedance matching unit, the second end of the first impedance matching unit is connected with one end of the first capacitor, and the other end of the first capacitor is electrically connected with the second end; the first impedance matching unit comprises a first branch I1, the first branch I1 comprises at least one first inductor; one end of the second capacitor is electrically connected with the first end and the first end of the first impedance matching unit, and the other end of the second capacitor is electrically grounded; and one end of the resistor is electrically connected with the second end of the first impedance matching unit and the second end, and the other end of the resistor is electrically grounded. The chip is integrated with a DC coupling structure of the capacitor, so that the packaging size of the chip is reduced, and meanwhile, the broadband impedance of the chip is good in continuity and low in cost.
Description
Technical Field
The application relates to the technical field of chips, in particular to a chip integrated with a DC coupling capacitor.
Background
With the rapid development of optical communication, higher requirements including bandwidth, integration level, low power consumption and the like are put forward on high-speed electric chips. When the chip is applied, the internal and external DC voltages of the chip are not consistent, and at this time, the capacitor is usually used to block the internal and external DC voltages of the chip, as shown in fig. 1, an AC coupling architecture in which the blocking capacitor is configured outside the chip is used, the capacitor C _ PCB is configured on the PCB, the capacitance value of the capacitor C _ PCB is about 100nF, and the volume of the packaged chip is large.
Since the overall electrical chip is broadband, as the bandwidth increases, the capacitance (C _ pcb) must also be broadband, requiring multiple capacitors to be configured for impedance matching, resulting in further simultaneous poor device package size economy. Also the capacitance on the PCB board deteriorates the impedance continuity of the broadband system.
Therefore, a chip having a novel capacitive coupling structure is required.
SUMMERY OF THE UTILITY MODEL
To overcome the above-mentioned drawbacks, the present application aims to: the chip with the integrated DC coupling capacitor is provided, the DC coupling capacitor is integrated on the chip, the packaging size of the chip can be reduced, the impedance continuity is good when the chip is applied to the occasion of broadband (100 KHz-30 GHz), and the economy of the chip is good.
In order to solve the technical problem, the following technical scheme is adopted in the application:
a chip integrated with a DC coupling capacitor, comprising:
a first end and a second end, wherein,
the first end of the first impedance matching unit is electrically connected with the first end of the first capacitor, the second end of the first impedance matching unit is connected with one end of the first capacitor, and the other end of the first capacitor is electrically connected with the second end;
the first impedance matching unit comprises a first branch I1, the first branch I1 comprises at least one first inductor;
one end of the second capacitor is electrically connected with the first end and the first end of the first impedance matching unit, and the other end of the second capacitor is electrically grounded;
and one end of the resistor is electrically connected with the second end of the first impedance matching unit and the second end, and the other end of the resistor is electrically grounded. By the design, the packaging size of the chip (chip module) is reduced, and the impedance continuity is good when the chip is applied to the occasions of broadband (100 KHz-30 GHz).
Preferably, the inductance value of the first inductor ranges from 10pH to 800 pH.
Preferably, the first impedance matching unit comprises a second branch I2, and the second branch I2 comprises: the inductor comprises at least one second inductor and at least one third capacitor, wherein the second inductor is electrically connected with the third capacitor in series.
Preferably, one end of the second inductor is electrically connected to one end of the first inductor and the first end.
Preferably, one end of the third capacitor is electrically connected to one end of the first inductor and the first end.
Preferably, the second inductor and the third capacitor are integrated in a chip. This reduces the chip (chip module) package size.
Preferably, the first capacitor is integrated in the chip. This reduces the chip (chip module) package size.
Advantageous effects
For the scheme among the prior art, the beneficial effect of this application:
according to the chip integrated with the DC coupling capacitor, the DC coupling capacitor is integrated on the chip, so that the chip does not need to be provided with a large-size broadband capacitor on a PCB, the packaging size of the chip (chip module) is effectively reduced, and the continuity of broadband impedance is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without inventive efforts, wherein:
FIG. 1 is a schematic topology of an AC coupling method in which a DC blocking capacitor is configured outside a conventional chip;
FIG. 2 is a schematic view of a chip topology using an integrated capacitive coupling structure according to a first embodiment of the present application;
FIG. 3 is a schematic view of a chip with an integrated capacitive coupling structure according to a second embodiment of the present application;
fig. 4 is a schematic topology diagram of a chip adopting an integrated capacitive coupling structure according to a third embodiment of the present application.
Detailed Description
The above-described scheme is further illustrated below with reference to specific examples. It should be understood that these examples are for illustrative purposes and are not intended to limit the scope of the present application. The conditions used in the examples may be further adjusted according to the conditions of the particular manufacturer, and the conditions not specified are generally the conditions in routine experiments.
In the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements and circuits that are well known to those skilled in the art have not been described in detail so as not to obscure the present disclosure. The drawings include schematic drawings, and the scale and the aspect ratio of each component may be different from those of the actual components
The present application proposes a chip configured to integrate a DC coupling capacitance. By the implementation structure, the high bandwidth range (range) can be matched, the capacitor is integrated on the chip, the packaging size of the chip (chip module) is reduced, and the requirement of chip miniaturization is met.
The chip integrated with DC coupling capacitor proposed in the present application will be described in detail with reference to fig. 2 to 4. The drawings include schematic drawings, and the scale and the aspect ratio of each component may be different from those of the actual components.
Referring to fig. 2, fig. 2 is a schematic diagram of a chip topology adopting an integrated capacitive coupling structure according to a first embodiment of the disclosure. The chip has a first terminal (Vin) and a second terminal (Vout),
the first end (Vip) is electrically connected to the first end 11a of the first impedance matching unit 11, the second end 11b of the first impedance matching unit 11 is connected to one end of the first capacitor C _ ac, and the other end of the first capacitor C _ ac is connected to the second end (Vout); the first impedance matching unit 11 comprises a first branch I1, the first branch I1 comprises a first inductor L1, and the inductance value range thereof is 10pH to 800 pH.
One end of the second capacitor C _ pad is electrically connected to the first end (Vip) and the first end 11a of the first impedance matching unit 11, and the other end of the second capacitor C _ pad is electrically grounded.
One end of the resistor R _ rf is electrically connected to the second end 11b and the second end (Vout) of the first impedance matching unit 11. The components (the second capacitor C _ pad, the resistor R _ rf, and the like) in this embodiment are all integrated in a chip (i.e., an electronic component is integrated in an On-chip package) without disposing components On a PCB (printed circuit board). This effectively reduces the package size of the chip while improving the continuity of the broadband impedance.
Fig. 3 shows a variation of the above embodiment, which is a schematic topology diagram of a chip of the second embodiment adopting an integrated capacitive coupling structure;
the difference between this method and the embodiment shown in fig. 2 is that the first impedance matching unit 11 further includes a second branch I2, and the second branch I2 includes a second inductor Lp and a third capacitor C _ p electrically connected in series. The second branch I2 is electrically connected in parallel with the first branch I1 to form an LC matching network, which further improves the flatness of the high frequency impedance when applied to high frequency/ultra high frequency applications. Meanwhile, in the embodiment, the second capacitor C _ pad is integrated in the chip, and in addition, the DC level is isolated by the first capacitor C _ ac in the chip. The reliability of the chip is improved.
Fig. 4 shows a schematic diagram of a third embodiment of a chip with an integrated capacitive coupling structure according to a variation of the embodiment of fig. 3;
this approach differs from the embodiment of fig. 3 in the arrangement of the second inductor Lp and the third capacitor C _ p. In this embodiment, the third capacitor C _ p contacts the signal of the first section Vin first, which further improves the flatness of the high frequency impedance when it is applied to high frequency/ultra high frequency. Meanwhile, the embodiment realizes the isolation of the DC level through the first capacitor C _ ac in the chip. The reliability of the chip is improved.
In an embodiment, the first impedance matching unit is configured as a transmission line. Thus being directly connected by a transmission line.
In one embodiment, the first branch I1 and the second branch I2 are connected in parallel. The first inductor L1, the second inductor Lp, and the third capacitor C _ p may be equivalent, and in a specific embodiment, may be represented by equivalent components.
It should be noted that, in the present application, the terms "upper", "lower", "inner", "middle", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings. These terms are used primarily to better describe the present application and its embodiments, and are not used to limit the indicated devices, elements or components to a particular orientation or to be constructed and operated in a particular orientation. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only.
The above embodiments are merely illustrative of the technical concepts and features of the present application, and the purpose of the embodiments is to enable those skilled in the art to understand the content of the present application and implement the present application, and not to limit the protection scope of the present application. All equivalent changes and modifications made according to the spirit of the present application are intended to be covered by the scope of the present application.
Claims (7)
1. A chip integrated with a DC coupling capacitor, comprising:
a first end and a second end, wherein,
the first end of the first impedance matching unit is electrically connected with the first end of the first capacitor, the second end of the first impedance matching unit is connected with one end of the first capacitor, and the other end of the first capacitor is electrically connected with the second end;
the first impedance matching unit comprises a first branch I1, the first branch I1 comprises at least one first inductor;
one end of the second capacitor is electrically connected with the first end and the first end of the first impedance matching unit, and the other end of the second capacitor is electrically grounded;
and one end of the resistor is electrically connected with the second end of the first impedance matching unit and the second end, and the other end of the resistor is electrically grounded.
2. The integrated DC coupling capacitor chip of claim 1, wherein the first inductor has an inductance value ranging from 10pH to 800 pH.
3. The integrated DC coupling capacitor chip of claim 1, wherein the first impedance matching unit comprises a second branch I2, the second branch I2 comprising:
the inductor comprises at least one second inductor and at least one third capacitor, wherein the second inductor is electrically connected with the third capacitor in series.
4. The integrated DC coupling capacitance chip of claim 3,
one end of the second inductor is electrically connected with one end of the first inductor and the first end.
5. The integrated DC coupling capacitance chip of claim 3,
one end of the third capacitor is electrically connected with one end of the first inductor and the first end.
6. The integrated DC coupling capacitance chip of claim 3,
the second inductor and the third capacitor are integrated in a chip.
7. The integrated DC coupling capacitance chip of claim 1,
the first capacitor is integrated in a chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020437179.8U CN211455723U (en) | 2020-03-30 | 2020-03-30 | Chip integrated with DC coupling capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020437179.8U CN211455723U (en) | 2020-03-30 | 2020-03-30 | Chip integrated with DC coupling capacitor |
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| Publication Number | Publication Date |
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| CN211455723U true CN211455723U (en) | 2020-09-08 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114244308A (en) * | 2021-12-27 | 2022-03-25 | 苏州芈图光电技术有限公司 | kHz-100 GHz on-chip integrated capacitor DC coupling circuit |
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- 2020-03-30 CN CN202020437179.8U patent/CN211455723U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114244308A (en) * | 2021-12-27 | 2022-03-25 | 苏州芈图光电技术有限公司 | kHz-100 GHz on-chip integrated capacitor DC coupling circuit |
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