CN211453476U - Full-waveform ultrasonic flaw detector - Google Patents

Abstract

The utility model provides a full waveform ultrasonic flaw detector, including ARM treater, field programmable gate array and SRAM buffer module, the ARM treater carries out data transmission through FMC interface and field programmable gate array and realizes communication, adopts parallel interface transmission between field programmable gate array and the SRAM buffer module; the field programmable gate array sends a pulse control signal, high-voltage sharp pulses are output through the power amplification circuit, the ultrasonic probe converts an electric signal into an acoustic signal, the ultrasonic probe is used for receiving the acoustic signal and converting the acoustic signal into the electric signal, the electric signal is subjected to low-noise amplification through the variable gain amplifier, the amplified echo signal is sent to the ADC module to realize the process of converting the analog signal into a digital signal, and the field programmable gate array is used for controlling the operation processing of the signal and the signal. The utility model discloses can save the full wave form of ultrasonic inspection to realize subsequent processing and analysis.

Description

Full-waveform ultrasonic flaw detector

Technical Field

The utility model relates to an ultrasonic flaw detection technical field, concretely relates to full waveform ultrasonic flaw detector.

Background

As a nondestructive testing technology, the ultrasonic flaw detector is widely applied to the industrial field by the advantages of high detection efficiency, safety, no radiation, less consumption of consumables, low comprehensive use cost and the like. Limited to the cache capability and the screen display capability, the conventional hyperdetection method extracts waveforms, for example, 128K data points are collected and displayed on a screen, only 320 points or 640 points (which is the same as the display resolution of the screen) are displayed, and the digital ultrasonic flaw detection method only stores the extracted points during storing flaw detection waveforms, so that a large amount of waveform information is lost. Because many defect types are judged according to waveforms, and only amplitude information is reserved after extraction, a circuit architecture capable of saving the full waveform of ultrasonic flaw detection needs to be designed to realize subsequent processing and analysis.

SUMMERY OF THE UTILITY MODEL

In view of this, the utility model aims to solve the problem of providing a full waveform ultrasonic flaw detector.

In order to solve the technical problem, the utility model discloses a technical scheme is: a full-waveform ultrasonic flaw detector comprises an ARM processor, a field programmable gate array and an SRAM cache module, wherein the ARM processor is communicated with the field programmable gate array through data transmission through an FMC interface, and the field programmable gate array and the SRAM cache module are transmitted through parallel interfaces; the field programmable gate array and the ADC module realize data transmission through a parallel interface, the field programmable gate array sends a pulse control signal, the power amplification circuit outputs high-voltage sharp pulses to convert an electric signal into an acoustic signal, the ultrasonic probe is used for receiving the acoustic signal and converting the acoustic signal into the electric signal, the electric signal realizes low-noise amplification of the signal through a variable gain amplifier, the amplified echo signal is sent into the ADC module to realize the process of converting the analog signal into a digital signal, the field programmable gate array is used for controlling the operational processing of the signal and the signal, and the processed signal is displayed through the display screen.

In the utility model discloses, preferably, what the model of ARM treater adopted is STM32F767VIT6, the ARM treater pass through the LCD interface with the display screen links to each other, the ARM treater with SRAM cache module adopts 16bit parallel interface, the D0-D15 terminal of field programmable gate array is as the data line, the A0-A18 of field programmable gate array is as the address line, the/WR _ BUF terminal of field programmable gate array,/CS _ BUF,/RD _ BUF terminal is as the control line, the/WR _ BUF terminal of field programmable gate array is as writing signal, the/CS _ BUF terminal of field programmable gate array is as the chip select signal, the/RD _ BUF terminal of field programmable gate array is as reading signal.

The utility model discloses in, preferably, the BOOTO terminal of ARM treater passes through resistance R65 ground connection, the VREF + terminal of ARM treater, VBAT terminal, VDDA terminal, VDD terminal all link 3.3V DC voltage, the VREF + terminal of ARM treater passes through electric capacity C36 ground connection, the VCAP _1 terminal of ARM treater passes through electric capacity C54 ground connection, the VCAP _2 terminal of ARM treater passes through electric capacity C55 ground connection, the VDDA terminal of ARM treater passes through electric capacity C45 ground connection, the VDD terminal of ARM treater passes through electric capacity C46 ground connection.

In the present invention, preferably, the D0-D9 terminals of the field programmable gate array are respectively connected to the ADD0-ADD9 terminals of the ADC module, the CLK terminal of the field programmable gate array is connected to the ENCODE terminal of the ADC module, and the PWRDN terminal of the field programmable gate array is connected to the PWRDN terminal of the ADC module.

In the utility model discloses in, preferably, the ARM treater even has the EMMC memory through EMMC bus protocol, the VDDI terminal of EMMC memory is through parallelly connected electric capacity C67 and electric capacity C68 ground connection, the RFU/VSS4 of ARM treater is through resistance R68 ground connection, the RFU/VSS5 of ARM treater is through resistance R69 ground connection, the VCC1-VCC4 terminal of ARM treater all links 3.3V DC voltage, the VCC1 terminal of ARM treater is through having pole capacitance C69 ground connection, and the VCC1 terminal of ARM treater links to each other through resistance R115 and the VCCQ1 of ARM treater, the VCC1 terminal of ARM treater links to each other through resistance R117 and the CQ VCVCVCC 1 of ARM treater.

The utility model discloses in, preferably, the ARM treater adopts USB interface connection to have the PC, the ARM treater uploads data the PC carries out further analysis and processing.

In the present invention, it is preferable that the model of the field programmable gate array is EP4CE22F17C 8N.

In the present invention, preferably, the model of the SRAM cache module IS61LV 51216.

In the present invention, it is preferable that the variable gain amplifier is an AD 8332.

In the present invention, preferably, the model of the EMMC memory is set to KLMCG8 GEAC-B001.

The utility model has the advantages and positive effects that: through the mutual matching among the ARM processor, the field programmable gate array and the SRAM cache module, the ARM + FPGA + SRAM framework is established to be capable of capturing and storing full waveforms of flaw detection waves instead of extracted waveforms, so that the characteristic identification and search of flaw waves in the whole flaw detection range are facilitated; the full-waveform defect waves scanned and stored on site can be stored in an EMMC memory, and can be led into a PC through a USB data line to be stored and reprocessed after returning to a laboratory; the reproduction of the data and the extraction processing of the stored data can be finished in the ARM without passing through a field programmable gate array; the capacity of the EMMC can be 64G or even higher, and the memory capacity is very strong.

Drawings

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention, and together with the description serve to explain the invention and not to limit the invention. In the drawings:

fig. 1 is a schematic signal transmission diagram of a field programmable gate array of a full waveform ultrasonic flaw detector according to the present invention;

fig. 2 is a block diagram of the overall structure of a full-waveform ultrasonic flaw detector of the present invention;

fig. 3 is a schematic circuit diagram of a field programmable gate array of a full waveform ultrasonic flaw detector according to the present invention;

fig. 4 is a schematic circuit diagram of an ultrasonic probe of a full waveform ultrasonic flaw detector according to the present invention;

FIG. 5 is a schematic circuit diagram of an ARM processor of a full waveform ultrasonic flaw detector of the present invention;

fig. 6 is a pin diagram of a field programmable gate array of a full waveform ultrasonic flaw detector according to the present invention;

fig. 7 is a schematic circuit diagram of a display screen of a full-waveform ultrasonic flaw detector according to the present invention;

fig. 8 is a schematic circuit diagram of an EMMC memory of a full-waveform ultrasonic flaw detector according to the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When a component is referred to as being "connected" to another component, it can be directly connected to the other component or intervening components may also be present. When a component is referred to as being "disposed on" another component, it can be directly on the other component or intervening components may also be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

As shown in fig. 1 to 8, the utility model provides a full waveform ultrasonic flaw detector, including ARM treater, field programmable gate array and SRAM buffer module, the ARM treater carries out data transmission through FMC interface and field programmable gate array and realizes the communication, adopts parallel interface transmission between field programmable gate array and the SRAM buffer module; the field programmable gate array and the ADC module realize data transmission through a parallel interface, the field programmable gate array sends a pulse control signal, high-voltage sharp pulses are output through the power amplification circuit, the ultrasonic probe converts an electric signal into an acoustic signal, the ultrasonic probe is used for receiving the acoustic signal and converting the acoustic signal into the electric signal, the electric signal realizes low-noise amplification of the signal through a variable gain amplifier, the amplified echo signal is sent to the ADC module to realize the process of converting an analog signal into a digital signal, the field programmable gate array is used for operation processing of the control signal and the signal, and the processed signal is displayed through the display screen. A 16-bit parallel interface is adopted between the field programmable gate array and the SRAM cache module, an address line is A0-A18, a data line is D0-D15, a control line is respectively a chip selection signal, read permission and write permission, an addressing space is 512K 16 bits, an interface between the field programmable gate array and the ARM processor adopts an FMC interface, and the data width is 16 bits; the ARM processor directly drives the display screen through the LCD interface, the display screen adopts a color liquid crystal screen with 640 x 480 resolution, and in the scanning process of the ultrasonic detector, data transmitted from the field programmable gate array to the ARM are extracted, and the data volume is less than 2K bytes; the data which is frozen and transmitted from the FPGA to the ARM processor is a complete flaw detection waveform which is not extracted at the freezing moment, the data quantity is about 1M Byte, rich flaw information is fully stored, the 1M Byte data is transmitted to the ARM processor for only tens of milliseconds at most, no new data quantity comes in the frozen state, a display screen does not refresh the display, the transmission link is not felt by a user, the data reproduction and the data storage extraction can be completed in the ARM processor without passing through the FPGA, and the flaw wave in the whole flaw detection range can be conveniently identified and searched. The ADC module is AD9215 in a model, single power supply is adopted for supplying power, and a high-performance sampling holding amplifier and a reference voltage source are arranged in the ADC module. The AD9215 adopts a multi-stage differential pipeline structure and is internally provided with output error correction logic, 10-bit precision can be provided at a 105MSPS data rate, and no code loss is ensured in the whole working temperature range. With the wide bandwidth, true differential sample and hold amplifier of the AD9215, a variety of input ranges and offsets, including single ended applications, can be selected when in use. The device is also suitable for a multiplexing system for switching full-scale levels in a continuous channel, sampling single-channel input by using a frequency far exceeding a Nyquist range, controlling all internal conversion periods by using a single-ended clock input, and compensating large clock duty ratio fluctuation by using a duty ratio stabilizer while maintaining excellent performance; the digital output data format is standard binary or complement binary.

The ARM processor and the field programmable gate array transmit data and send instructions through an FMC interface, and the ARM processor comprises five control lines and 16 data lines. The field programmable gate array and the ADC module adopt a 10-bit parallel interface for data transmission, the ENCODE is used as a synchronous signal and connected with a CLK pin of the ADC module, the ADC module starts conversion at the falling edge, and the conversion result of the ADC module at the rising edge is transmitted to a bus and read by the field programmable gate array; PWRDN is connected with the PWRDN pin of ADC module as the power supply control signal, and when this signal is pulled high, ADC module enters power saving state. A parallel interface is also adopted between the field programmable gate array and the SRAM cache module for data transmission, and the parallel interface comprises three control lines, 19 address lines and 16 data lines.

In this embodiment, further, the model of the ARM processor is STM32F767VIT6, the ARM processor is connected to the display screen through the LCD interface, the ARM processor and the SRAM cache module use a 16-bit parallel interface, the D0-D15 terminals of the field programmable gate array are used as data lines, the a0-a18 of the field programmable gate array are used as address lines, the/WR _ BUF,/CS _ BUF,/RD _ BUF terminals of the field programmable gate array are used as control lines, the/WR _ BUF terminals of the field programmable gate array are used as write signals, the/CS _ BUF terminals of the field programmable gate array are used as chip select signals, and the/RD _ BUF terminals of the field programmable gate array are used as read signals. The ARM processor of the type is packaged into a 100-pin flat square package, integrates an LCD interface in an RGB mode, has the highest main frequency of 216MHz, has the instruction processing capability of 462DMIPS, has the program and data FLASH of 2MBFLASH, has the memory of 512+16+4KB RAM, has the USB OTG HS/FS interface capability, and is internally provided with a self-adaptive real-time accelerator and an FPU (floating point processor), so that the adopted microprocessor has strong interface capability and control capability and strong data processing capability.

In this embodiment, further, the BOOTO terminal of the ARM processor is grounded through a resistor R65, the VREF + terminal of the ARM processor, the VBAT terminal, the VDDA terminal, the VDD terminal are all connected with a 3.3V dc voltage, the VREF + terminal of the ARM processor is grounded through a capacitor C36, the VCAP _1 terminal of the ARM processor is grounded through a capacitor C54, the VCAP _2 terminal of the ARM processor is grounded through a capacitor C55, the VDDA terminal of the ARM processor is grounded through a capacitor C45, and the VDD terminal of the ARM processor is grounded through a capacitor C46.

In the embodiment, the terminals D0-D9 of the field programmable gate array are respectively connected with the terminals ADD0-ADD9 of the ADC module, the terminal CLK of the field programmable gate array is connected with the terminal ENCODE of the ADC module, and the terminal PWRDN of the field programmable gate array is connected with the terminal PWRDN of the ADC module. The ARM microprocessor is used as a main controller of the ultrasonic flaw detector, when the ARM processor sends a starting command to the field programmable gate array through the FMC interface, the field programmable gate array outputs a clock signal of 105MHz to the ADC module through an ENCODE signal line, and the ultrasonic probe acquires data and converts an acoustic signal into an electric signal. The data volume of one time sampling is sampling rate measuring range 2/sound velocity, the data volume is not more than 1 Mbyte through the calculation, the data is pressed into the SRAM cache module to cache the data while the field programmable gate array controls the ADC module to collect the data, and the field programmable gate array samples, detects, calculates envelope, identifies simple characteristics and the like the cache data in the SRAM cache module in the interval after the current collection is completed and before the next collection is completed. If the ARM processor does not send out the freezing instruction, the field programmable gate array transmits the extracted data to the ARM processor, and then the next round of acquisition is carried out; and if the freezing instruction is sent, the field programmable gate array stops data acquisition and transmits the full waveform data in the SRAM cache module to the ARM processor.

In this embodiment, further, the ARM processor is connected to the EMMC memory through an EMMC bus protocol, a VDDI terminal of the EMMC memory is grounded through a parallel capacitor C67 and a capacitor C68, an RFU/VSS4 of the ARM processor is grounded through a resistor R68, an RFU/VSS5 of the ARM processor is grounded through a resistor R69, VCC1-VCC4 terminals of the ARM processor are connected to a 3.3V dc voltage, a VCC1 terminal of the ARM processor is grounded through an active capacitor C69, a VCC1 terminal of the ARM processor is connected to a VCCQ1 of the ARM processor through a resistor R115, and a VCC1 terminal of the ARM processor is connected to a VCCQ1 of the ARM processor through a resistor R117.

In this embodiment, the ARM processor is further connected to a PC through a USB interface, and the ARM processor uploads the data to the PC for further analysis and processing.

In the present embodiment, furthermore, the model of the field programmable gate array is EP4CE22F17C 8N. The FBGA-256 package is adopted for the field programmable gate array because the number of available I/O ports is larger, which is considered to be suitable for the situation that the number of pins used in the ultrasonic flaw detector is larger, and the requirement of practical use can be met.

In this embodiment, further, the model of the SRAM cache module IS61LV51216, which has a space of 1 mbyte, the operable frequency IS higher than 125MHz, the sampling clock of the ADC module IS configured to be 100MHz, and the SRAM cache module can meet the requirement of fast cache.

In the embodiment, further, the model of the variable gain amplifier is AD8332, and LCR passive devices are used for filtering. The variable gain amplifier can solve the problem that the dynamic range of an ultrasonic echo signal is too wide, when an analog signal is converted into a digital signal, if the dynamic range of the signal is too wide, the resolution of an analog-to-digital converter is possibly insufficient to capture all useful information, the variable gain amplifier can amplify an input signal with the amplitude smaller than the lowest resolution, and attenuate a signal with the amplitude larger than the maximum peak value, so that the analog-to-digital converter is prevented from being saturated.

In this embodiment, further, the model number of the EMMC memory is set to KLMCG8 GEAC-B001.

The utility model discloses a theory of operation and working process as follows: the ARM processor is communicated with the field programmable gate array through data transmission between the FMC interface and the SRAM cache module through a parallel interface; the field programmable gate array and the ADC module realize data transmission through a parallel interface, the field programmable gate array sends a pulse control signal, high-voltage sharp pulses are output through the power amplification circuit, the ultrasonic probe converts an electric signal into an acoustic signal, the ultrasonic probe is used for receiving the acoustic signal and converting the acoustic signal into the electric signal, the electric signal realizes low-noise amplification of the signal through a variable gain amplifier, the amplified echo signal is sent to the ADC module to realize the process of converting an analog signal into a digital signal, the field programmable gate array is used for operation processing of the control signal and the signal, and the processed signal is displayed through the display screen. The model of the variable gain amplifier in this embodiment is AD8332, which is a single-channel, linear dB variable gain amplifier, and is optimized for the ultrasonic detector in particular during product design, and has the characteristic of ultra-low noise. The AD8332 can be used as a low-noise variable gain amplifier in an ultrasonic detector, and is internally provided with an ultra-low-noise preamplifier, a variable gain amplifier with a gain range of 48dB and a selectable gain post-amplifier with an adjustable output limiting function, and a field programmable gate array is used as a logic device for controlling LNA (low noise preamplifier), VGA (variable gain amplifier) and AAF (anti-aliasing filter) in an ultrasonic transmitting circuit and an ultrasonic receiving circuit. The ARM microprocessor is used as a main controller of the ultrasonic flaw detector, and when the ARM processor sends a starting command to the field programmable gate array through the FMC interface, the field programmable gate array outputs a clock signal of 105MHz to the ADC module through the ENCODE signal line. In the ultrasonic detection process, the electric oscillation pulse of ultrasonic frequency generated by the ultrasonic detection transmitting circuit is converted into mechanical vibration through the probe, is transmitted to an object to be detected in the form of ultrasonic waves, is reflected by the defect to form an ultrasonic signal, and is received by the ultrasonic probe and converted into an electric signal. The ultrasound probe functions to actually convert between electrical and acoustic signals.

The data volume of one time sampling is sampling rate measuring range 2/sound velocity, the data volume is not more than 1 Mbyte through the calculation, the data is pressed into the SRAM cache module to cache the data while the field programmable gate array controls the ADC module to collect the data, and the field programmable gate array samples, detects, calculates envelope, identifies simple characteristics and the like the cache data in the SRAM cache module in the interval after the current collection is completed and before the next collection is completed. If the ARM processor does not send out the freezing instruction, the field programmable gate array transmits the extracted data to the ARM processor, and then the next round of acquisition is carried out; and if the freezing instruction is sent, the field programmable gate array stops data acquisition and transmits the full waveform data in the SRAM cache module to the ARM processor.

The utility model is characterized in that: through the mutual matching among the ARM processor, the field programmable gate array and the SRAM cache module, the ARM + FPGA + SRAM framework is established to be capable of capturing and storing full waveforms of flaw detection waves instead of extracted waveforms, so that the characteristic identification and search of flaw waves in the whole flaw detection range are facilitated; the full-waveform defect waves scanned and stored on site can be stored in an EMMC memory, and can be led into a PC through a USB data line to be stored and reprocessed after returning to a laboratory; the reproduction of the data and the extraction processing of the stored data can be finished in the ARM without passing through a field programmable gate array; the capacity of the EMMC can be 64G or even higher, and the memory capacity is very strong.

The embodiments of the present invention have been described in detail, but the present invention is only the preferred embodiments of the present invention, and the present invention is not to be considered as limiting the scope of the present invention. All equivalent changes and modifications made within the scope of the present invention should be covered by the present patent.

Claims (10)

1. The full-waveform ultrasonic flaw detector is characterized by comprising an ARM processor, a field programmable gate array and an SRAM cache module, wherein the ARM processor is communicated with the field programmable gate array through data transmission through an FMC interface, and the field programmable gate array and the SRAM cache module are transmitted through parallel interfaces; the field programmable gate array and the ADC module realize data transmission through a parallel interface, the field programmable gate array sends a pulse control signal, the power amplification circuit outputs high-voltage sharp pulses to convert an electric signal into an acoustic signal, the ultrasonic probe is used for receiving the acoustic signal and converting the acoustic signal into the electric signal, the electric signal realizes low-noise amplification of the signal through a variable gain amplifier, the amplified echo signal is sent into the ADC module to realize the process of converting the analog signal into a digital signal, the field programmable gate array is used for controlling the operational processing of the signal and the signal, and the processed signal is displayed through the display screen.

2. The full-waveform ultrasonic flaw detector of claim 1, wherein the model of the ARM processor is STM32F767VIT6, the ARM processor is connected with the display screen through an LCD interface, the ARM processor and the SRAM cache module adopt a 16-bit parallel interface, the D0-D15 terminals of the field programmable gate array are used as data lines, the a0-a18 of the field programmable gate array are used as address lines, the/WR _ BUF terminals,/CS _ BUF,/RD _ BUF terminals of the field programmable gate array are used as control lines, the/WR _ BUF terminals of the field programmable gate array are used as write signals, the/CS _ BUF terminals of the field programmable gate array are used as chip select signals, and the/RD _ BUF terminals of the field programmable gate array are used as read signals.

3. The full-waveform ultrasonic flaw detector of claim 1, wherein the BOOTO terminal of the ARM processor is grounded through a resistor R65, the VREF + terminal, the VBAT terminal, the VDDA terminal and the VDD terminal of the ARM processor are all connected with a 3.3V DC voltage, the VREF + terminal of the ARM processor is grounded through a capacitor C36, the VCAP _1 terminal of the ARM processor is grounded through a capacitor C54, the VCAP _2 terminal of the ARM processor is grounded through a capacitor C55, the VDDA terminal of the ARM processor is grounded through a capacitor C45, and the VDD terminal of the ARM processor is grounded through a capacitor C46.

4. The full-waveform ultrasonic flaw detector of claim 1, wherein the terminals D0-D9 of the field programmable gate array are connected with the terminals ADD0-ADD9 of the ADC module, respectively, the terminal CLK of the field programmable gate array is connected with the terminal ENCODE of the ADC module, and the terminal PWRDN of the field programmable gate array is connected with the terminal PWRDN of the ADC module.

5. The full-waveform ultrasonic flaw detector of claim 1, wherein the ARM processor is connected with the EMMC memory through an EMMC bus protocol, VDDI terminals of the EMMC memory are connected with the ground through a parallel capacitor C67 and a capacitor C68, RFU/VSS4 of the ARM processor is connected with the ground through a resistor R68, RFU/VSS5 of the ARM processor is connected with the ground through a resistor R69, VCC1-VCC4 terminals of the ARM processor are connected with a 3.3V dc voltage, VCC1 terminal of the ARM processor is connected with the ground through an active capacitor C69, VCC1 terminal of the ARM processor is connected with VCCQ1 of the ARM processor through a resistor R115, and VCC1 terminal of the ARM processor is connected with VCCQ1 of the ARM processor through a resistor R117.

6. The full-waveform ultrasonic flaw detector of claim 1 wherein the ARM processor is connected to the PC through a USB interface, and the ARM processor uploads data to the PC for further analysis and processing.

7. The full waveform ultrasonic flaw detector of claim 1 wherein the field programmable gate array is of the type EP4CE22F17C 8N.

8. The full-waveform ultrasonic flaw detector of claim 1, wherein the model of the SRAM cache module IS IS61LV 51216.

9. The full-waveform ultrasonic flaw detector of claim 1, wherein the variable gain amplifier is of the type AD 8332.

10. The full waveform ultrasonic flaw detector of claim 5 wherein the EMMC memory is model number KLMCG8 GEAC-B001.

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