CN110687858A

CN110687858A - Synchronous acquisition and transmission system of multichannel pulse signal

Info

Publication number: CN110687858A
Application number: CN201911100121.2A
Authority: CN
Inventors: 刘勇; 贾宝安; 袁中健; 朱明龙; 张保全
Original assignee: Tianjin Jinhang Computing Technology Research Institute
Current assignee: Tianjin Jinhang Computing Technology Research Institute
Priority date: 2019-11-12
Filing date: 2019-11-12
Publication date: 2020-01-14

Abstract

The invention discloses a synchronous acquisition and transmission system of a multichannel pulse signal, which comprises a pulse signal conditioning module, a parallel ADC module and a signal processing module, wherein the signal processing module is integrated in an FPGA (field programmable gate array), the parallel ADC module comprises a 32-channel ADC (analog to digital converter) and an FPGA (field programmable gate array) interface, the pulse signal conditioning module performs low-pass filtering and scaling on an input differential signal to complete signal conditioning, the conditioned signal is output to the FPGA through LVDS (low voltage differential signaling) parallel-serial conversion through the 32-channel ADC and the FPGA interface, and the signal processing module realizes serial-parallel conversion and data processing of sampling data. The invention not only can record and analyze the pulse waveform of each time point, but also can longitudinally compare the phase relation of a plurality of pulses; the method adopts the means of combining the analog baseband filtering, the digital filter and the digital comparator, greatly inhibits interference signals and improves the compression ratio of data.

Description

Synchronous acquisition and transmission system of multichannel pulse signal

Technical Field

The invention belongs to the technical field of aviation tests, and relates to a synchronous acquisition and transmission system of a multi-channel pulse signal, which is applied to an aviation data acquisition recorder.

Background

The aircraft parameter acquisition and recording system comprises installation equipment and ground guarantee equipment, wherein the installation equipment is used for completing high-speed real-time acquisition of pulse signals of an airborne weapon and an avionic system and performing real-time compression and storage on acquired data, and the ground guarantee equipment is mainly used for completing ground information reproduction of the acquired data and providing a reliable basis for XX model scientific research adjustment and identification trial flight.

The invention relates to an analog signal acquisition and storage device, which is used for acquiring and storing external analog signals, and the analog signal acquisition and storage device comprises a microcontroller, an analog voltage acquisition circuit, a limiting circuit, a filter circuit, a frequency selection circuit, a liquid crystal display module, a data storage module, a power module and an auxiliary circuit, wherein the microcontroller is respectively and electrically connected with the liquid crystal display module, the power module, the data storage module, the analog voltage acquisition circuit and the auxiliary circuit to respectively control the work of the liquid crystal display module, the power module, the data storage module, the analog voltage acquisition circuit and the auxiliary circuit, the analog voltage acquisition module is electrically connected with the frequency selection circuit, and the filter circuit is respectively and electrically connected with the frequency selection circuit and the limiting circuit. The device is based on the STM32 single chip microcomputer, has good reliability, simple function and higher precision, is easy to combine with other data filtering algorithms compared with other signal acquisition devices, realizes effective processing of data, and can be applied to various simple analog signal acquisition environments. The method also realizes signal conditioning, acquisition and storage, but adopts a singlechip to realize, so that multichannel synchronous acquisition and storage cannot be realized in the true sense, compression is not carried out according to signal characteristics, and multichannel concurrent acquisition transmission processing cannot be ensured.

The invention discloses a multi-channel signal synchronous acquisition and storage system which comprises a multi-channel signal acquisition unit, a signal processing unit and a signal storage unit, wherein each signal acquisition unit comprises a signal input circuit and a signal conditioning circuit, the signal input circuit is connected with the signal conditioning circuit, the signal processing unit adopts a DSC controller, and each signal conditioning circuit is respectively connected with the DSC controller; the signal storage unit comprises an ECC (error correction code) checking module and a storage chip, wherein the ECC checking module and the storage chip are respectively connected with the DSC controller. The invention adopts the DSC controller, combines the signal input circuit and the conditioning circuit, simultaneously adopts the flash memory chip to realize the acquisition and the rapid storage of the multi-channel signals, and can rapidly read the stored data; in the data acquisition and transmission process, the method has good reliability and stability. The method realizes multi-channel signal conditioning, but adopts a DSC controller, only a time-sharing multiplexing processor can be used, multi-channel signal parallel processing cannot be realized, and the processing capacity of the controller cannot finish multi-channel large-batch data processing.

Disclosure of Invention

Objects of the invention

The purpose of the invention is: aiming at the problems existing in the prior art, a synchronous acquisition and transmission system of multi-channel pulse signals is provided.

(II) technical scheme

In order to solve the technical problems, the invention provides a synchronous acquisition and transmission system of a multichannel pulse signal, which comprises a pulse signal conditioning module, a parallel ADC module and a signal processing module, wherein the signal processing module is integrated in an FPGA, the parallel ADC module comprises a 32-channel ADC and an FPGA interface, the pulse signal conditioning module performs low-pass filtering and scaling on an input differential signal to complete signal conditioning, the conditioned signal is output to the FPGA through LVDS parallel-to-serial conversion through the 32-channel ADC and the FPGA interface, and the signal processing module realizes serial-to-parallel conversion and data processing of sampling data.

The signal processing module comprises five sub-modules, namely an ADC (analog to digital converter) acquisition module, a digital filter module, a digital comparator shaping module, a data compression framing module and a PCIe (peripheral component interface express) transmission module, the ADC acquisition module performs serial-parallel conversion on sampled data, and the digital filter module filters to filter interference signals; the threshold value of the shaping module of the digital comparator can be matched to finish waveform shaping; the data compression framing module compresses the shaped data by adopting an RLE compression method and inserts a relative time scale according to the requirement; the PCIe transmission module is realized by an FPGA hard core, and transmits data compressed by 32 channels to a mainboard in a DMA mode, and the mainboard is responsible for recording the data to a hard disk.

The parallel ADC module comprises 4 high-integration ADC chips, each chip integrates 8-channel parallel ADCs, and a serial interface is selected between each ADC chip and the FPGA; the ADC chip adopts a 1-wire LVDS differential bus to transmit ADC data, and 2 connecting wires are needed for one ADC chip.

The digital filter module adopts a 7-order FIR filter, and the filter adopts a window function with the coefficient of 1.

The digital comparator shaping module comprises a digital comparator with a hysteresis function, the threshold value is 1-9V adjustable, and the stepping precision is 50 mV.

When the data is compressed by adopting an RLE compression method in the data compression framing module, the data is regarded as a linear sequence, and the organization mode of the linear data sequence is divided into two conditions: one is a continuous repeating data block, and the other is a continuous non-repeating data block; the continuous repeated data adopts one byte to represent the repeated times of the data block, and then the corresponding data byte is stored behind the attribute byte of the repeated data; for a data sequence which is not repeated continuously, the representation method is the same as that of a repeated data block sequence which is repeated continuously, and the content of the attribute byte of the previous data repeated is 1; in practical implementation, the data format is as follows:

the sampling data is data acquired by an ADC chip and is represented by a complement, and the range of the repetition times of a single field is 0x 1-0 x7 fff.

The PCIe transmission module and the sampled and compressed data are isolated by FIFO buffering, the data are stored in the FIFO after being compressed, each channel corresponds to an independent FIFO, the 32 channels are designed with the FIFOs with 32 different addresses to realize data caching, and when the compressed data reach 1MB, the PCIe module sends an interrupt message to the mainboard to prompt the mainboard to read the FIFO of the corresponding address.

After the data are transmitted to the mainboard, the data are written into the solid state disk by utilizing a reading process and a writing process respectively for subsequent analysis and processing of the ground platform.

(III) advantageous effects

Compared with the prior art, the synchronous acquisition and transmission system of the multi-channel pulse signals provided by the technical scheme realizes the parallel acquisition and recording of multiple channels in a real sense; the invention not only can record and analyze the pulse waveform of each time point, but also can longitudinally compare the phase relation of a plurality of pulses; by adopting the means of combining the analog baseband filtering, the digital filter and the digital comparator, the interference signal is greatly inhibited, and the compression ratio of the data is improved.

Drawings

FIG. 1 is a schematic block diagram of a system according to the present invention.

Fig. 2 shows the frequency characteristic of the digital filter according to the present invention.

Detailed Description

In order to make the objects, contents, and advantages of the present invention clearer, the following detailed description of the embodiments of the present invention will be made in conjunction with the accompanying drawings and examples.

Referring to fig. 1, the multi-channel pulse signal synchronous acquisition and transmission system of the present invention includes a pulse signal conditioning module, a parallel ADC module, and a signal processing module, wherein the signal processing module is integrated in an FPGA, the parallel ADC module includes a 32-channel ADC and an FPGA interface, the pulse signal conditioning module performs low-pass filtering and scaling on an input differential signal to complete signal conditioning, the conditioned signal is output to the FPGA through LVDS parallel-to-serial conversion through the 32-channel ADC and the FPGA interface, and the signal processing module implements serial-to-parallel conversion of sampling data and data processing.

The signal processing module comprises five sub-modules, namely an ADC (analog to digital converter) acquisition module, a digital filter module, a digital comparator shaping module, a data compression framing module and a PCIe (peripheral component interface express) transmission module, the ADC acquisition module performs serial-parallel conversion on sampled data, and the digital filter module is formed by a 7-order FIR (finite impulse response) filter and filters interference signals; the threshold value of the shaping module of the digital comparator can be matched to finish waveform shaping; the data compression framing module compresses the shaped data by adopting an RLE compression algorithm and inserts a relative time scale according to the requirement; the PCIe transmission module is realized by an FPGA hard core, and transmits data compressed by 32 channels to a mainboard in a DMA mode, and the mainboard is responsible for recording the data to a hard disk.

The pulse signal conditioning module adopts a differential operational amplifier to realize a proportional link, and as the amplitude of an input signal is 10V at most, a proportional factor is set to be 10; meanwhile, a low-pass filter is adopted to filter the high-frequency interference, and the cut-off frequency is set to be 3MHz according to the pulse characteristics.

The parallel ADC module consists of a 32-channel ADC and an FPGA interface, the system adopts the high-integration ADC, one chip integrates the 8-channel parallel ADC, and 4 chips are used for completing 32-channel signal acquisition. The serial interface is selected between the ADC and the FPGA because the higher the precision of the ADC, the more the number of channels and the more the connection with the FGPA. According to the analysis of the 12-Bit precision ADC, at least 12 data lines are needed for one ADC, if the system needs 32 channels, the number of the connecting lines is 12 x 32 to 384, so that not only are a large number of FPGA interface resources occupied, but also crosstalk is easily generated by parallel routing. The method adopts a 1-wire LVDS differential bus to transmit ADC data, one ADC only needs 2 connecting wires, the number of the connecting wires is 2 x 32-64, and the number of the connecting wires is far smaller than 384 parallel buses. In addition, the LVDS adopts a differential mode, voltage swing is small, power consumption is greatly reduced compared with a single-ended parallel interface, and meanwhile, the LVDS adopts a current mode for transmission, so that the anti-interference capability is strong.

The operation of the sub-modules in the signal processing module is realized in the FPGA, and each module works in parallel according to the number of pulse signal channels, namely each sub-module is instantiated for 32 times, so that real parallel processing is realized.

The digital filter module is formed by a 7-order FIR filter, the filter is realized by a window function with the coefficient of 1, and the digital filter module has the advantages of simple realization and saving a large number of precious hardware multipliers. In addition, the FIR filter has the main characteristic of no feedback loop, so that the instability problem does not exist; meanwhile, the amplitude characteristic can be set randomly, the accurate linear phase position is guaranteed, and the waveform cannot be distorted. The frequency domain of the digital filter corresponds to that shown in fig. 2, with out-of-band attenuation around 15 dB.

The digital comparator shaping module is used for designing a digital comparator with a hysteresis function according to signal characteristics, the threshold value is 1-9V adjustable, the stepping precision is 50mV, and the digital comparator can well meet the requirements and effectively filter interference signals. The threshold of the comparator comprises a positive threshold and a negative threshold, and the thresholds can be flexibly set according to the input signal and the interference characteristics. Compared with a comparator built by a hardware circuit, the method is flexible and good in stability. The threshold value can be set through a mainboard or read from a configuration file.

The data compression framing module compresses data by adopting an RLE compression method and inserts relative time scales according to system requirements. The pulse signal is typically triggered only when there is a particular action, and is held low for most of the time. It is this feature that for multi-channel parallel data, RLE compression algorithms can be employed. The RLE (Run Length Encoding) algorithm is a simple and efficient lossless data compression algorithm, and the basic idea is to consider data as a linear sequence, and the organization modes of the data sequences are divided into two cases: one is a continuous block of repeated data and the other is a continuous block of non-repeated data. The compression strategy adopted for the continuous repeated data block is to use one byte (which is called as data repetition attribute) to represent the number of times of data block repetition, and then store the corresponding data byte itself behind the data repetition attribute byte, for example, a certain file has the following data sequence AAAAA, which occupies 5 bytes before being uncompressed, but only occupies two bytes after being compressed to 5A, and for the continuous and non-repeated data sequence, the representation method is the same as that of the continuous repeated data block sequence, but the content of the previous data repetition attribute byte is 1. In practical implementation, the data format is as follows:

the sampling data is data acquired by an ADC chip and is represented by a complement, and the range of the repetition times of a single field is 0x 1-0 x7 fff. The ADC precision used in the method is 12 bits, 2 bytes are used for storage, and sampling data and the number of times of repetition are distinguished through the highest Bit. The highest bit is '1' to represent the sample data, such as 0x8_ x _ x _ x; the highest bit is '0' to represent the repetition times, the maximum value of the repetition times is 0x7fff, the field is added after the 0x7fff is counted, and the recording is continued from 1 until the data changes.

Where the numbers following 0x0000 represent relative time stamps which are second pulses generated using a three-way local clock to record the offset of the sampled data from the absolute time stamp. The FPGA is adopted to realize the process, and the compression rate is about 4 percent.

The PCIe transmission module is realized by an FPGA hard core and transmits 32 channel data in a DMA mode. PCIe hard cores are generated by using self resources of the FPGA, and data of 32 channels are transmitted in series in a DAM mode. FIFO buffer isolation is adopted between the sampled and compressed data and the PCIe module. Data are compressed and then stored in the FIFOs, each channel corresponds to an independent FIFO, and therefore 32 FIFOs with different addresses are designed for 32 channels to achieve data caching. When the compressed data reaches 1MB, the PCIe module sends an interrupt message to the mainboard to prompt the mainboard to read the FIFO of the corresponding address.

According to the technical scheme, the data acquired by the method are used for ground playback and analysis; the concurrent pulses are emitted by an airborne weapon, an avionics system, but are not limited to the above systems; the method can realize synchronous acquisition and recording of 32 paths of signals, but is not limited to parallel processing of the multi-path data of the number; the acquisition method can be used for one daughter card and can also be used for a plurality of daughter cards to realize acquisition of more channels; the pulse signal conditioning module filters and scales an input signal to complete signal conditioning; the ADC parallel acquisition module is acquired by a 32-channel parallel ADC and is connected with the FPGA through an LVDS interface; the digital filter module is formed by an FIR filter; the digital comparator module realizes digital comparators by using gate array resources, and the threshold value of each comparator can be configured independently; the data compression framing module compresses data by adopting an RLE compression algorithm and inserts a relative time scale according to system requirements; the concurrent acquisition and transmission is realized by each channel signal through an independent hardware circuit or FPGA; the PCIe transmission module is realized by an FPGA hard core and transmits 32 channel data in a DMA mode.

The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.

Claims

1. The synchronous acquisition and transmission system of the multichannel pulse signals is characterized by comprising a pulse signal conditioning module, a parallel ADC module and a signal processing module, wherein the signal processing module is integrated in an FPGA (field programmable gate array), the parallel ADC module comprises a 32-channel ADC (analog to digital converter) and an FPGA (field programmable gate array) interface, the pulse signal conditioning module performs low-pass filtering and scaling on input differential signals to complete signal conditioning, conditioned signals are output to the FPGA through LVDS (low voltage differential signaling) parallel-serial conversion through the 32-channel ADC and the FPGA interface, and the signal processing module realizes sampling data serial-parallel conversion and data processing.

2. The system for synchronously acquiring and transmitting the multichannel pulse signals according to claim 1, wherein the signal processing module comprises five sub-modules, namely an ADC acquisition module, a digital filter module, a digital comparator shaping module, a data compression framing module and a PCIe transmission module, the ADC acquisition module carries out serial-to-parallel conversion on the sampled data, and the digital filter module filters the sampled data to filter out interference signals; the threshold value of the shaping module of the digital comparator can be matched to finish waveform shaping; the data compression framing module compresses the shaped data by adopting an RLE compression method and inserts a relative time scale according to the requirement; the PCIe transmission module is realized by an FPGA hard core, and transmits data compressed by 32 channels to a mainboard in a DMA mode, and the mainboard is responsible for recording the data to a hard disk.

3. The system for synchronously acquiring and transmitting the multi-channel pulse signals according to claim 2, wherein the parallel ADC module comprises 4 high-integration ADC chips, each chip integrates 8-channel parallel ADCs, and a serial interface is selected between the ADC chips and the FPGA; the ADC chip adopts a 1-wire LVDS differential bus to transmit ADC data, and 2 connecting wires are needed for one ADC chip.

4. The system for synchronous acquisition and transmission of multichannel pulse signals as claimed in claim 3, characterized in that said digital filter module uses a 7-order FIR filter using a window function with a coefficient of 1.

5. The system for synchronously acquiring and transmitting the multi-channel pulse signals as claimed in claim 4, wherein the digital comparator shaping module comprises a digital comparator with a hysteresis function, the threshold value is 1-9V adjustable, and the stepping precision is 50 mV.

6. The system for synchronously acquiring and transmitting multi-channel pulse signals according to claim 5, wherein when the data is compressed by the RLE compression method in the data compression framing module, the data is regarded as a linear sequence, and the linear data sequence organization mode is divided into two cases: one is a continuous repeating data block, and the other is a continuous non-repeating data block; the continuous repeated data adopts one byte to represent the repeated times of the data block, and then the corresponding data byte is stored behind the attribute byte of the repeated data; for a data sequence which is not repeated continuously, the representation method is the same as that of a repeated data block sequence which is repeated continuously, and the content of the attribute byte of the previous data repeated is 1; in practical implementation, the data format is as follows:

7. The system for synchronously acquiring and transmitting the multichannel pulse signals according to claim 6, wherein the PCIe transmission module is isolated from the sampled and compressed data by FIFO buffer, the data is stored in the FIFO after being compressed, each channel corresponds to an independent FIFO, 32 FIFOs with different addresses are designed for 32 channels to realize data cache, and when the compressed data reaches 1MB, the PCIe module sends an interrupt message to the mainboard to prompt the mainboard to read the FIFO with the corresponding address.

8. The system for synchronously acquiring and transmitting multi-channel pulse signals according to claim 7, wherein after the data is transmitted to the motherboard, the data is written into the solid state disk by a reading process and a writing process respectively for subsequent analysis and processing by the ground platform.