CN211046907U - 用于fpga芯片的高速串并转换接口字同步电路 - Google Patents
用于fpga芯片的高速串并转换接口字同步电路 Download PDFInfo
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- CN211046907U CN211046907U CN201922452678.4U CN201922452678U CN211046907U CN 211046907 U CN211046907 U CN 211046907U CN 201922452678 U CN201922452678 U CN 201922452678U CN 211046907 U CN211046907 U CN 211046907U
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- 238000006243 chemical reaction Methods 0.000 title claims abstract description 93
- 230000001360 synchronised effect Effects 0.000 title description 10
- 238000005070 sampling Methods 0.000 claims abstract description 88
- 230000000630 rising effect Effects 0.000 claims abstract description 58
- 238000000034 method Methods 0.000 claims abstract description 25
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- 238000010586 diagram Methods 0.000 description 11
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- 230000003111 delayed effect Effects 0.000 description 2
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Abstract
Description
slip执行的操作 | 输出模式(1:7) |
初始 | [6][5][4][3][2][1][0] |
1 | [0][6][5][4][3][2][1] |
2 | [4][3][2][1][0][6][5] |
3 | [5][4][3][2][1][0][6] |
4 | [2][1][0][6][5][4][3] |
5 | [3][2][1][0][6][5][4] |
6 | [0][6][5][4][3][2][1] |
7 | [1][0][6][5][4][3][2] |
8 | [5][4][3][2][1][0][6] |
9 | [6][5][4][3][2][1][0] |
slip执行的操作 | 输出模式(1:7) |
初始 | [6][5][4][3][2][1][0] |
1 | [1][0][6][5][4][3][2] |
2 | [3][2][1][0][6][5][4] |
3 | [5][4][3][2][1][0][6] |
4 | [0][6][5][4][3][2][1] |
5 | [2][1][0][6][5][4][3] |
6 | [4][3][2][1][0][6][5] |
7 | [6][5][4][3][2][1][0] |
Claims (5)
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CN201922452678.4U CN211046907U (zh) | 2019-12-30 | 2019-12-30 | 用于fpga芯片的高速串并转换接口字同步电路 |
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CN211046907U true CN211046907U (zh) | 2020-07-17 |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113364468A (zh) * | 2021-06-24 | 2021-09-07 | 成都纳能微电子有限公司 | 串并转换对齐电路及方法 |
CN113517894A (zh) * | 2021-07-14 | 2021-10-19 | 上海安路信息科技股份有限公司 | 串并转换电路 |
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2019
- 2019-12-30 CN CN201922452678.4U patent/CN211046907U/zh active Active
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113364468A (zh) * | 2021-06-24 | 2021-09-07 | 成都纳能微电子有限公司 | 串并转换对齐电路及方法 |
CN113517894A (zh) * | 2021-07-14 | 2021-10-19 | 上海安路信息科技股份有限公司 | 串并转换电路 |
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GR01 | Patent grant | ||
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PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of utility model: High speed serial parallel conversion interface word synchronization circuit for FPGA chip Effective date of registration: 20220329 Granted publication date: 20200717 Pledgee: Pudong Development Bank of Shanghai Limited by Share Ltd. Xi'an branch Pledgor: XI'AN INTELLIGENCE SILICON TECHNOLOGY, Inc. Registration number: Y2022610000115 |
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Date of cancellation: 20230328 Granted publication date: 20200717 Pledgee: Pudong Development Bank of Shanghai Limited by Share Ltd. Xi'an branch Pledgor: XI'AN INTELLIGENCE SILICON TECHNOLOGY, Inc. Registration number: Y2022610000115 |
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PC01 | Cancellation of the registration of the contract for pledge of patent right | ||
PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of utility model: High speed serial parallel conversion interface word synchronization circuit for FPGA chips Effective date of registration: 20230331 Granted publication date: 20200717 Pledgee: Pudong Development Bank of Shanghai Limited by Share Ltd. Xi'an branch Pledgor: XI'AN INTELLIGENCE SILICON TECHNOLOGY, Inc. Registration number: Y2023610000233 |
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PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
PC01 | Cancellation of the registration of the contract for pledge of patent right |
Granted publication date: 20200717 Pledgee: Pudong Development Bank of Shanghai Limited by Share Ltd. Xi'an branch Pledgor: XI'AN INTELLIGENCE SILICON TECHNOLOGY, Inc. Registration number: Y2023610000233 |