CN210955072U - Integrated circuit computing device and computing processing system - Google Patents
Integrated circuit computing device and computing processing system Download PDFInfo
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- CN210955072U CN210955072U CN201922450992.9U CN201922450992U CN210955072U CN 210955072 U CN210955072 U CN 210955072U CN 201922450992 U CN201922450992 U CN 201922450992U CN 210955072 U CN210955072 U CN 210955072U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The utility model discloses an integrated circuit computing device, include: the first processing module is used for receiving and processing the RISC-V instruction set instruction; the second processing module is connected with the first processing module; a first bus connecting the first processing module and the second processing module; and a first port connected to the first processing module and a second port connected to the second processing module. The embodiment of the utility model provides a through embedding RISC-V framework treater hardcore in the FPGA chip for FPGA chip development personnel can be nimble as required adjust the treater kernel, thereby strengthened the computing power of FPGA chip and guaranteed that equipment area is little, the low power dissipation, low in manufacturing cost.
Description
Technical Field
The utility model belongs to system level chip design field, concretely relates to integrated circuit computing device and calculation processing system.
Background
Currently, in an FPGA (Field Programmable Gate Array) design, a processor hard core or a processor soft core is usually embedded, that is, an ASIC (application specific Integrated Circuit) Circuit of a processor is embedded inside an FPGA chip, or a processor is implemented on a Programmable logic of an FPGA in a manner of an HDL (Hardware description language) program code.
However, FPGAs with embedded processor hardcores are commercial IP cores such as ARM (Advanced RISC Machine), PowerPC, etc., and the use of commercial IP greatly increases the use cost of the FPGA user, on one hand, the cost of the FPGA itself is increased, and on the other hand, when the user wants to convert the design on the FPGA into an ASIC (Application specific integrated Circuit) design, the user still needs to pay extra IP use cost; secondly, the internal design details of most commercial IP cores (internal Property cores) are invisible, which cannot meet the requirements of application scenes (such as security scenes of national defense and military industry) with the requirement that the chips are completely safe and controllable; third, commercial IPs have poor design flexibility and, once a certain IP is selected, subsequent product upgrades are limited by IP capabilities. The FPGA using the soft core needs to occupy logic resources on the FPGA when the soft core is implemented, and occupies a large power consumption, a large area, and a lower computing power compared with the hard core, so that the FPGA cannot meet application requirements of high precision and high real-time performance, and is relatively poor in practicability.
SUMMERY OF THE UTILITY MODEL
In order to solve the above-mentioned problem that exists among the prior art, the utility model provides an integrated circuit computing device and computational processing system. The to-be-solved technical problem of the utility model is realized through following technical scheme:
an embodiment of the utility model provides an integrated circuit computing device, include:
the first processing module is used for receiving and processing the RISC-V instruction set instruction;
the second processing module is connected with the first processing module;
a first bus connecting the first processing module and the second processing module;
and a first port connected to the first processing module and a second port connected to the second processing module.
In one embodiment, the first processing module comprises:
RISC-V instruction set processor, memory cell, peripheral extension unit; and the RISC-V instruction set processor is used for interconnecting the storage unit and the peripheral extension unit through a second bus interface.
In one embodiment, the apparatus further comprises:
and the debugging port is connected with the first processing module and the second processing module.
In one embodiment, the first processing module further comprises: and the first test access interface is connected with the RISC-V instruction set processor and the debugging port.
In one embodiment, the first test access interface is a JTAG interface.
In one embodiment, the second processing module comprises:
the programmable logic gate array is connected with the configuration block, the configuration block is connected with the second test access interface, and the second test access interface is connected with the debugging port.
In one embodiment, the second test access interface is a JTAG interface.
In one embodiment, the first bus interface protocol and the second bus interface protocol each include an AMBA protocol or a TileLink protocol.
In one embodiment, the RISC-V instruction set processor includes a CPU, GPU, DSP, or hardware accelerator.
An embodiment of the utility model provides a calculation processing system is provided simultaneously, including the host computer, still including the coupling to above-mentioned integrated circuit computing device on the host computer.
Compared with the prior art, the beneficial effects of the utility model are that:
the embodiment of the utility model provides a through embedding RISC-V framework hard core processor in the FPGA chip for FPGA chip development personnel can be nimble as required adjust the treater kernel, thereby strengthened the computing power of FPGA chip and guaranteed that equipment area is little, the low power dissipation, low in manufacturing cost.
Drawings
Fig. 1 is a block diagram of an integrated circuit computing device module according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a design of an integrated circuit computing device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the present invention is not limited thereto.
Example one
Referring to fig. 1, fig. 1 is a block diagram of an integrated circuit computing device module according to an embodiment of the present invention, including:
the first processing module 1 is used for receiving and processing the instruction of the RISC-V instruction set;
the second processing module 2 is connected with the first processing module;
a first bus 3 connecting the first processing module and the second processing module;
and a first port 4 connected to the first process module 1 and a second port 5 connected to the second process module 2.
With continued reference to fig. 2, in one embodiment, the first processing module 1 includes:
RISC-V instruction set processor 11, memory unit 12, peripheral extension unit 13; the risc processor 11 interconnects the memory unit 12 and the peripheral expansion unit 13 via a second bus interface 14.
RISC-V is an open source instruction set architecture which has emerged in recent years, the RISC-V is completely open source, the architecture is simple, the performance is superior, the lifting space is large, and the RISC-V processor has a complete tool chain, the architecture of the RISC-V processor can be flexibly adjusted according to different applications, for example, a multiplication instruction set (RV32M), a single-precision floating-point operation instruction set (RV32F), a double-precision floating-point operation instruction set (RV32D) and the like can be added on the RV32I basic instruction set of the RISC-V.
The first processing module is a system on chip using RISC-V instruction set for the core processor, which can be CPUBlock, and the inner part is integrated with RISC-V instruction set processor hard core. The second processing module is an FPGA Block. Of course, in other embodiments, the processor in the first processing module may also be a circuit such as a GPU, a DSP, or a hardware accelerator that employs a RISC-V architecture.
In one embodiment, the apparatus further comprises:
a debug port 6 connecting said first processing module 1 and said second processing module 2. Of course, the first processing module and the second processing module may be accessed or debugged through the same port, or may be accessed or debugged through different ports.
In a specific embodiment, the first processing module 1 further includes: a first test access interface 15 connecting the risc processor 11 and the debug port 6.
In one embodiment, the first test access interface 15 is a JTAG interface.
In a specific embodiment, the second processing module 2 includes:
the device comprises a programmable logic gate array 21, a configuration block 22 and a second test access interface 23, wherein the programmable logic gate array 21 is connected with the configuration block 22, the configuration block 22 is connected with the second test access interface 23, and the second test access interface 23 is connected with the debugging port 6.
In one embodiment, the second test access interface 23 is a JTAG interface (Joint test action Group).
In a specific embodiment, the first bus 3 interface protocol and the second bus 4 interface protocol each include an AMBA protocol bus or a TileLink protocol bus.
In one application scenario, the host is coupled to a debug port 6 of the FPGA chip via a wire. After the FPGA is powered on, the host computer uses FPGA development software to write configuration data of the FPGA into the configuration block 22 through the test access interface 23, and the configuration block 22 rewrites programmable logic of the FPGA to a state specified by a user by using the configuration data. In addition, the host writes programs (instructions) to be executed by the RISC-V instruction set processor 11 to the memory unit 12 through the test access interface 15. The program executed here may be a complicated program such as a floating point operation and a signal processing, or may be a simple program for controlling the peripheral extension unit 13. The RISC-V instruction set processor 11 may be a dedicated processor designed, optimized and adjusted for a specific program, and can efficiently complete various control or calculation functions required by a user while ensuring low power consumption and cost.
After the configuration of the configuration block 22 and the writing to the memory unit 12 are completed, the RISC-V instruction set processor 11 reads the instruction held in the memory unit 12 and executes it. The various control or calculation functions required by the user will be implemented by the first processing module 1 alone or by the first processing module 1 and the array of programmable logic gates 21 together, depending on the actual situation.
The embodiment of the utility model provides a through embedding RISC-V framework treater hardcore in the FPGA chip for the FPGA chip can be as required nimble adjust the treater kernel, thereby has strengthened computing power and has guaranteed that equipment area is little, the low power dissipation, and has reduced chip use cost.
An embodiment of the utility model provides a calculation processing system is provided simultaneously, including the host computer, still including the coupling to above-mentioned integrated circuit computing device on the host computer.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically limited otherwise.
While the present application has been described in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a review of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, apparatus (device), or computer program product. Accordingly, this application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects that may all generally be referred to herein as a "module" or "system. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein. A computer program stored/distributed on a suitable medium supplied together with or as part of other hardware, may also take other distributed forms, such as via the Internet or other wired or wireless telecommunication systems.
The foregoing is a more detailed description of the present invention, taken in conjunction with the specific preferred embodiments thereof, and it is not intended that the invention be limited to the specific embodiments shown and described. To the utility model belongs to the technical field of ordinary technical personnel, do not deviate from the utility model discloses under the prerequisite of design, can also make a plurality of simple deductions or replacement, all should regard as belonging to the utility model discloses a protection scope.
Claims (10)
1. An integrated circuit computing device, comprising:
the first processing module is used for receiving and processing the RISC-V instruction set instruction;
the second processing module is connected with the first processing module;
a first bus connecting the first processing module and the second processing module;
and a first port connected to the first processing module and a second port connected to the second processing module.
2. The integrated-circuit computing device of claim 1, wherein the first processing module comprises:
RISC-V instruction set processor, memory cell, peripheral extension unit; and the RISC-V instruction set processor is used for interconnecting the storage unit and the peripheral extension unit through a second bus interface.
3. The integrated-circuit computing device of claim 1, wherein the device further comprises:
and the debugging port is connected with the first processing module and the second processing module.
4. The integrated-circuit computing device of claim 3, wherein the first processing module further comprises: and the first test access interface is connected with the RISC-V instruction set processor and the debugging port.
5. The integrated circuit computing device of claim 4, wherein the first test access interface is a JTAG interface.
6. The integrated circuit computing device of claim 3, wherein the second processing module comprises:
the programmable logic gate array is connected with the configuration block, the configuration block is connected with the second test access interface, and the second test access interface is connected with the debugging port.
7. The integrated circuit computing device of claim 6, wherein the second test access interface is a JTAG interface.
8. The integrated circuit computing device of claim 2, wherein the first bus interface protocol and the second bus interface protocol each comprise an AMBA protocol or a TileLink protocol.
9. The integrated-circuit computing device of claim 1, wherein RISC-V instruction set processor comprises a CPU, GPU, DSP, or hardware accelerator.
10. A computing processing system comprising a host, further comprising the integrated circuit computing device of any of claims 1-9 coupled to the host.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922450992.9U CN210955072U (en) | 2019-12-30 | 2019-12-30 | Integrated circuit computing device and computing processing system |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922450992.9U CN210955072U (en) | 2019-12-30 | 2019-12-30 | Integrated circuit computing device and computing processing system |
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| Publication Number | Publication Date |
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| CN210955072U true CN210955072U (en) | 2020-07-07 |
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| CN201922450992.9U Active CN210955072U (en) | 2019-12-30 | 2019-12-30 | Integrated circuit computing device and computing processing system |
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Denomination of utility model: Integrated circuit computing equipment and computing processing system Effective date of registration: 20220329 Granted publication date: 20200707 Pledgee: Pudong Development Bank of Shanghai Limited by Share Ltd. Xi'an branch Pledgor: XI'AN INTELLIGENCE SILICON TECHNOLOGY, Inc. Registration number: Y2022610000115 |
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Date of cancellation: 20230328 Granted publication date: 20200707 Pledgee: Pudong Development Bank of Shanghai Limited by Share Ltd. Xi'an branch Pledgor: XI'AN INTELLIGENCE SILICON TECHNOLOGY, Inc. Registration number: Y2022610000115 |
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Denomination of utility model: An integrated circuit computing device and computing processing system Effective date of registration: 20230331 Granted publication date: 20200707 Pledgee: Pudong Development Bank of Shanghai Limited by Share Ltd. Xi'an branch Pledgor: XI'AN INTELLIGENCE SILICON TECHNOLOGY, Inc. Registration number: Y2023610000233 |
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| PC01 | Cancellation of the registration of the contract for pledge of patent right |
Granted publication date: 20200707 Pledgee: Pudong Development Bank of Shanghai Limited by Share Ltd. Xi'an branch Pledgor: XI'AN INTELLIGENCE SILICON TECHNOLOGY, Inc. Registration number: Y2023610000233 |