CN210835776U - DC level adjusting circuit - Google Patents
DC level adjusting circuit Download PDFInfo
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- CN210835776U CN210835776U CN201921942598.0U CN201921942598U CN210835776U CN 210835776 U CN210835776 U CN 210835776U CN 201921942598 U CN201921942598 U CN 201921942598U CN 210835776 U CN210835776 U CN 210835776U
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Abstract
The embodiment of the utility model provides a direct current level control circuit, including MOS pipe S, triode Q and PWM signal generation module, wherein: the base electrode, the collector electrode and the emitter electrode of the triode Q are respectively and correspondingly connected with the output end of the PWM signal generation module, the grid electrode of the MOS tube S and the ground end GND, and the base electrode and the emitter electrode are also connected through a first resistor R1; the source electrode and the drain electrode of the MOS tube S are respectively and correspondingly connected to an external power supply and the output end of the direct-current level regulating circuit, and the source electrode and the grid electrode of the MOS tube S are also connected through a second resistor R2; the triode Q is correspondingly in a conducting state, an amplifying state or a cut-off state according to the PWM signal provided by the PWM signal generating module, and the MOS tube S is correspondingly in an incomplete conducting state when the triode Q is in the amplifying state. In the embodiment, the MOS transistor S and the triode Q are arranged, and the duty ratio of the PWM signal is changed to realize the dynamic adjustment of the direct current level; and the circuit elements are few, so that the production cost is reduced.
Description
Technical Field
The embodiment of the utility model provides a relate to current regulation circuit technical field, especially relate to a direct current level control circuit.
Background
At present, in a streaming media electronic rearview mirror system, the transmittance and the reflectivity of electronic rearview mirror glass need to be adjusted by adjusting different direct current level values, so that the automatic anti-dazzle function is realized. The required power current of control circuit of anti-dazzle glass is generally great, can't use singlechip direct drive control, therefore current regulating circuit includes integrated chip usually, presets the resistance value of pin through adjusting integrated chip to change the direct current level value of integrated chip output, but current integrated chip's cost is generally higher, has increased manufacturing cost.
SUMMERY OF THE UTILITY MODEL
The embodiment of the utility model provides a technical problem that will solve lies in, provides a direct current level control circuit, can effective reduce cost.
In order to solve the technical problem, an embodiment of the utility model provides a following technical scheme: the utility model provides a direct current level control circuit, includes MOS pipe S, triode Q and PWM signal generation module, wherein:
the base electrode, the collector electrode and the emitter electrode of the triode Q are respectively and correspondingly connected with the output end of the PWM signal generation module, the grid electrode of the MOS tube S and the ground end GND, and the base electrode and the emitter electrode are also connected through a first resistor R1;
the source electrode and the drain electrode of the MOS tube S are respectively and correspondingly connected to an external power supply and the output end of the direct current level regulating circuit, and the source electrode and the grid electrode of the MOS tube S are also connected through a second resistor R2;
the triode Q is correspondingly in a conducting state, an amplifying state or a cut-off state according to the PWM signal provided by the PWM signal generating module, and the MOS tube S is correspondingly in an incomplete conducting state when the triode Q is in the amplifying state.
Further, the dc level adjusting circuit further includes a first capacitor C1 connected in parallel with the second resistor R2.
Further, the drain of the MOS transistor S is also connected to the ground GND through a second capacitor C2.
Further, the base of the transistor Q is connected to the output end of the PWM signal generating module through a third resistor R3.
Further, the collector of the triode Q is also connected to the gate of the MOS transistor S through a fourth resistor R4.
Further, the PWM signal generation module is a PWM chip.
After the technical scheme is adopted, the embodiment of the utility model provides an at least, following beneficial effect has: the embodiment of the utility model provides a through the base with triode Q, collecting electrode and projecting pole correspond the output of connecting PWM signal generation module respectively, MOS pipe S ' S grid and earthing terminal GND, and MOS pipe S ' S source electrode and drain electrode correspond connection external power source and output respectively, only need to send suitable PWM control signal through PWM signal generation module and can make triode Q work at the enlarged state, and, can make MOS pipe S also correspond work at incomplete conducting state this moment, during PWM control signal duty cycle dynamic change, triode Q ' S base current and collecting electrode current also can synchronous dynamic change thereupon, and then make MOS pipe S ' S grid and source electrode within a definite time pressure drop also dynamic change, finally make MOS pipe S ' S the voltage of drain electrode output also can synchronous dynamic change, thereby the dynamic adjustment of the direct current level of output has been realized. The embodiment of the utility model provides a circuit element who adopts is few, has effectively reduced manufacturing cost.
Drawings
Fig. 1 is a circuit diagram of an alternative embodiment of the dc level regulator of the present invention.
Detailed Description
The present application will now be described in further detail with reference to the accompanying drawings and specific examples. It is to be understood that the following illustrative embodiments and description are only intended to illustrate the present invention, and are not intended to limit the present invention, and features in the embodiments and examples may be combined with each other in the present application without conflict.
As shown in fig. 1, an optional embodiment of the present invention provides a dc level adjusting circuit, which includes a MOS transistor S, a transistor Q, and a PWM signal generating module 1, wherein:
the base electrode, the collector electrode and the emitter electrode of the triode Q are respectively and correspondingly connected with the output end of the PWM signal generation module 1, the grid electrode of the MOS tube S and the ground end GND, and the base electrode and the emitter electrode are also connected through a first resistor R1;
the source electrode and the drain electrode of the MOS tube S are respectively and correspondingly connected to an external power supply 3 and the output end of the direct current level regulating circuit, and the source electrode and the grid electrode of the MOS tube S are also connected through a second resistor R2;
the triode Q is correspondingly in a conducting state, an amplifying state or a cut-off state according to the PWM signal provided by the PWM signal generating module 1, and the MOS tube S is correspondingly in an incomplete conducting state when the triode Q is in the amplifying state.
The embodiment of the utility model provides a through the base with triode Q, collecting electrode and projecting pole correspond the output of connecting PWM signal generation module 1 respectively, MOS pipe S ' S grid and earthing terminal GND, and MOS pipe S ' S source electrode and drain electrode correspond respectively and connect external power source 3 and output, only need to send suitable PWM control signal through PWM signal generation module 1 and can make triode Q work at the enlarged state, and, can make MOS pipe S also correspond work at incomplete conducting state this moment, during PWM control signal duty cycle dynamic change, triode Q ' S base current and collecting electrode current also can synchronous dynamic change thereupon, and then make MOS pipe S ' S grid and source electrode within a definite time also dynamic change, finally make MOS pipe S ' S the voltage of drain electrode output also can synchronous dynamic change, thereby the dynamic adjustment of the direct current level of output has been realized. The embodiment of the utility model provides a circuit element who adopts is few, has effectively reduced manufacturing cost.
The embodiment of the utility model provides a concrete theory of operation as follows: when the PWM control signal is at a high level and a low level, the on and off of the triode Q are correspondingly controlled; when the triode Q is conducted and works in the amplification region, when the duty ratio of the PWM control signal is increased, the base voltage of the triode Q is increased, the base current is also increased, and according to the principle of the triode Q, the collector current of the triode Q is also increased along with the base current, so that the voltage drop on a collector is increased, and finally the collector voltage of the triode is reduced, namely the input voltage of an S grid electrode of an MOS (metal oxide semiconductor) tube is reduced; according to the working principle of the MOS transistor S, the voltage input by the external power supply 3 is output to the gate of the MOS transistor S after the voltage drop is generated by the third resistor R3, and when the voltage difference between the gate and the source of the MOS transistor S dynamically changes within the predetermined threshold range of the voltage difference between the gate and the source when the MOS transistor S is not completely turned on, the voltage input by the external power supply 3 will generate a voltage drop in the MOS transistor S and be output from the drain of the MOS transistor S, and the voltage drop generated in the MOS transistor S will dynamically change with the voltage difference between the gate and the source of the MOS transistor S, that is, the voltage output by the drain of the MOS transistor S dynamically changes; however, the voltage of the source electrode of the MOS transistor S is always constant, so that the input voltage of the grid electrode of the MOS transistor S is controlled by changing the duty ratio of the PWM control signal, and the dynamic adjustment of the direct current level is realized; and the circuit elements are few, so that the production cost is reduced.
In an optional embodiment of the present invention, the dc level adjusting circuit further comprises a first capacitor C1 connected in parallel with the second resistor R2. In this embodiment, the first capacitor C1 is further connected in parallel to the two ends of the second resistor R2, so that the ac component in the external power supply 3 is effectively filtered, and the stability of the circuit is improved.
In yet another optional embodiment of the present invention, the drain of the MOS transistor S is further connected to the ground GND through a second capacitor C2. The drain electrode of the MOS transistor S is connected to the ground end GND through the second capacitor C2, noise waves can be effectively filtered through the second capacitor C2, the reliability of the circuit is improved, and the stability of the output direct current level is guaranteed.
In another optional embodiment of the present invention, the base of the transistor Q is connected to the output terminal of the PWM signal generating module 1 through a third resistor R3. In this embodiment, by providing the third resistor R3, the third resistor R3 not only can effectively limit the current of the circuit, but also can adjust the amplitude of the PWM control signal inputted to the base of the transistor Q.
In yet another optional embodiment of the present invention, the collector of the transistor Q is further connected to the gate of the MOS transistor S through a fourth resistor R4. In this embodiment, by providing the fourth resistor R4, the fourth resistor R4 can effectively control the amplitude of the PWM control signal inputted to the gate of the MOS transistor S.
In an optional embodiment of the present invention, the PWM signal generation module 1 is a PWM chip. The PWM signal generating module 1 of this embodiment uses a PWM chip, which is beneficial to simplifying the circuit structure and has relatively low cost.
The embodiments of the present invention have been described with reference to the accompanying drawings, but the present invention is not limited to the above-mentioned embodiments, which are only illustrative and not restrictive, and those skilled in the art can make many forms without departing from the spirit and scope of the present invention, and these forms are within the scope of the present invention.
Claims (6)
1. The utility model provides a direct current level control circuit which characterized in that, includes MOS pipe S, triode Q and PWM signal generation module, wherein:
the base electrode, the collector electrode and the emitter electrode of the triode Q are respectively and correspondingly connected with the output end of the PWM signal generation module, the grid electrode of the MOS tube S and the ground end GND, and the base electrode and the emitter electrode are also connected through a first resistor R1;
the source electrode and the drain electrode of the MOS tube S are respectively and correspondingly connected to an external power supply and the output end of the direct current level regulating circuit, and the source electrode and the grid electrode of the MOS tube S are also connected through a second resistor R2;
the triode Q is correspondingly in a conducting state, an amplifying state or a cut-off state according to the PWM signal provided by the PWM signal generating module, and the MOS tube S is correspondingly in an incomplete conducting state when the triode Q is in the amplifying state.
2. The dc level adjustment circuit of claim 1, further comprising a first capacitor C1 connected in parallel with the second resistor R2.
3. The dc level adjustment circuit of claim 1, wherein the drain of the MOS transistor S is further connected to a ground terminal GND through a second capacitor C2.
4. The dc level adjustment circuit of claim 1, wherein the base of the transistor Q is connected to the output terminal of the PWM signal generation module through a third resistor R3.
5. The dc level adjustment circuit of claim 1, wherein the collector of the transistor Q is further connected to the gate of the MOS transistor S through a fourth resistor R4.
6. The dc level adjustment circuit of claim 1, wherein the PWM signal generation module is a PWM chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921942598.0U CN210835776U (en) | 2019-11-11 | 2019-11-11 | DC level adjusting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921942598.0U CN210835776U (en) | 2019-11-11 | 2019-11-11 | DC level adjusting circuit |
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| Publication Number | Publication Date |
|---|---|
| CN210835776U true CN210835776U (en) | 2020-06-23 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201921942598.0U Active CN210835776U (en) | 2019-11-11 | 2019-11-11 | DC level adjusting circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110687961A (en) * | 2019-11-11 | 2020-01-14 | 深圳市豪恩汽车电子装备股份有限公司 | DC level adjusting circuit |
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2019
- 2019-11-11 CN CN201921942598.0U patent/CN210835776U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110687961A (en) * | 2019-11-11 | 2020-01-14 | 深圳市豪恩汽车电子装备股份有限公司 | DC level adjusting circuit |
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