CN210609074U - Rail-to-rail operational amplifier capable of correcting offset voltage - Google Patents
Rail-to-rail operational amplifier capable of correcting offset voltage Download PDFInfo
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- CN210609074U CN210609074U CN201921800453.7U CN201921800453U CN210609074U CN 210609074 U CN210609074 U CN 210609074U CN 201921800453 U CN201921800453 U CN 201921800453U CN 210609074 U CN210609074 U CN 210609074U
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Abstract
The utility model discloses a correctable offset voltage's rail to rail operational amplifier, including starting circuit, band gap core circuit, biasing circuit, rail to rail input circuit, offset voltage correction circuit, intermediate level circuit, rail to rail output circuit. The starting circuit is used for avoiding a zero current state; the band gap core circuit is used for generating a reference current; the bias circuit is used for generating bias voltage for working of each stage; the rail-to-rail input circuit is used for expanding the dynamic input range of signals; the offset voltage correction circuit is used for correcting errors of offset voltage caused by influences of factors such as processes, devices, input stage voltage and the like; the intermediate stage circuit is used for amplifying the signal voltage; the rail-to-rail output circuit is used for providing the rail-to-rail output swing. The circuit has the characteristics of low offset, high precision and rail-to-rail input and output.
Description
Technical Field
The utility model relates to an analog integrated circuit field, concretely relates to correctable offset voltage's rail-to-rail operational amplifier.
Background
The operational amplifier is the most extensive and basic device in an analog integrated circuit, and the performance of the operational amplifier directly determines the performance of analog systems such as a digital-analog/analog-digital converter, a low-dropout linear stabilizer, a phase-locked loop and the like.
With the increasing maturity and rapid development of semiconductor technology, the feature size of modern technology is continuously reduced, the gate oxide thickness is continuously reduced, in order to avoid the breakdown of a gate, ensure the reliability of a microelectronic device and force the power supply voltage to be further reduced, and therefore, a rail-to-rail operational amplifier is required to realize a large input/output swing under low voltage.
The rail-to-rail operational amplifier can keep a high signal-to-noise ratio to a certain extent, but in the manufacturing process of an integrated circuit, offset voltage is introduced due to the influence of factors such as process and device mismatch, the precision of digital-to-analog or analog-to-digital conversion is directly influenced, the signal-to-noise ratio is reduced, and therefore the input offset voltage needs to be corrected.
SUMMERY OF THE UTILITY MODEL
The utility model discloses an aim at utilizing input voltage to influence offset voltage and rail to rail input/output can increase the characteristics of dynamic amplitude of oscillation, provide a take offset voltage correction circuit and rectify the high rail to rail operational amplifier of precision. Compared with the prior art, the utility model uses the rail-to-rail input and output structure, improves the dynamic range of the operational amplifier while improving the signal-to-noise ratio; in addition, the offset voltage correction circuit adopts a digital logic control technology to adjust the resistance value of the resistor, and has the characteristics of convenience in correction and high precision.
The technical scheme of the utility model as follows:
the rail-to-rail operational amplifier capable of correcting offset voltage comprises a common starting circuit, a band gap core circuit, a biasing circuit, a rail-to-rail input circuit, an intermediate stage circuit and a rail-to-rail output circuit, and also comprises an offset voltage correcting circuit. The offset voltage correction circuit comprises a resistor RC1、RC2、RC3、RC4、RP1、RP2、RP3And RP4Switch S1、S2、S3、S4、K1、K2、K3And K4(ii) a Resistance RC1、RC2、RC3And RC4The first terminal of the resistor is connected with a power supply VDD and a resistor RC1Second terminal and switch S1Is connected to the first terminal of resistor RC2Second terminal and switch S2Is connected to the first terminal of resistor RC3Second terminal and switch S3Is connected to the first terminal of resistor RC4Second terminal and switch S4Is connected to the first terminal of, switch S1、S2、S3And S4Is connected to a first correction output signal Control 1; resistance RP1、RP2、RP3And RP4The first terminal of the resistor is connected with a power supply VDD and a resistor RP1Second terminal of and switch K1Is connected to the first terminal of resistor RP2Second terminal of and switch K2Is connected to the first terminal of resistor RP3Second terminal of and switch K3Is connected to the first terminal of resistor RP4Second terminal of and switch K4Is connected to the first terminal of the switch K1、K2、K3And K4Is connected to the second correction output signal Control 2.
Additionally, the utility model also provides an optimized rail-to-rail input circuit, rail-to-rail input circuit includes NMOS pipe N10、N11And N12PMOS tube P11、P12And P13Resistance R3、R4And R5(ii) a PMOS tube P11The source electrode of the PMOS transistor is connected with a power supply VDD and a PMOS tube P11And a first bias voltage Vb1Connected, PMOS tube P11Drain electrode of (1) and PMOS tube P12、P13Source electrode of (1) is connected with a PMOS tube P12Grid and NMOS transistor N10And the second input signal V of the operational amplifier-Connected, PMOS tube P13Grid and NMOS transistor N11Gate of and operational amplifier first input signal V+Connected, PMOS tube P12Drain electrode of (1), resistor R3First terminal of and PMOS differential pair transistor second current IP-Connected, PMOS tube P13Drain electrode of (1), resistor R5First terminal of (1) and PMOS differential pair transistor first current IP+Connected, NMOS tube N10Drain electrode of the NMOS differential pair transistor, and NMOS differential pair transistor first current In+NMOS transistor N connected to the first correction output signal Control111Drain electrode of the NMOS differential pair transistor, and second current I of the NMOS differential pair transistorn-NMOS transistor N connected to the second correction output signal Control210、N11Source electrode and NMOS transistor N12Drain electrode of (1) NMOS tube N12Gate and resistor R of4Is connected to the first terminal of resistor R4And a second terminal of the second bias voltage Vb2Connected, NMOS tube N12Source electrode, resistance R3Second terminal and resistor R5Is grounded.
Drawings
FIG. 1 is a connection diagram of a start-up circuit according to an embodiment.
FIG. 2 is a diagram of an embodiment bandgap core circuit connection.
FIG. 3 is a diagram of the bias circuit and rail-to-rail input circuit according to one embodiment.
FIG. 4 is a diagram of the connection between the intermediate stage circuit and the rail-to-rail output circuit in the embodiment.
FIG. 5 is a diagram of an embodiment of an offset voltage calibration circuit.
FIG. 6 is a circuit diagram of an embodiment of a rail-to-rail operational amplifier.
Detailed Description
A specific embodiment is provided below to illustrate the technical solution and advantages of the present invention in detail.
FIG. 1 shows a start-up circuitWay including NMOS transistor N1、N2PMOS tube P1、P2、P3、P4、P5、P6(ii) a At the moment of power-up, P1、P4Opening, P1、P4After partial pressure is P3Providing a starting voltage, P3Is conducted to connect Vu1Is pulled down by the voltage P6The conduction injects the starting current into the band gap core circuit. With the normal operation of the bandgap core circuit, VN1Voltage drop of P5Is conducted to connect Vu1The voltage at is pulled up to power VDD, causing P to be6When the work is cut off, the band gap core circuit keeps a stable working state.
FIG. 2 shows a bandgap core circuit including NMOS transistor N3、N4、N5、N6PMOS tube P7、P8、P9Resistance R1、R2(ii) a At a potential VN2The voltage is:
from which the current I can be derived1Equal to:
will VN2Substituting the voltage of (a):
simultaneously deriving the current I2The following were used:
since Vgs has a negative temperature coefficient and △ Vgs has a positive temperature coefficient, I is shown by equation 2.41Is a current with positive temperature coefficient, as shown in formula 3.3, I2Is a current with a negative temperature coefficient, and at the point M, the following can be known by the KCL theorem:
（4）。
reference current IRIs composed of a current I with positive temperature coefficient1And a current I having a negative temperature coefficient2Superimposed, reference current IRThe zero-temperature-coefficient working current can remove the influence of temperature and realize the zero-temperature-coefficient working current, and therefore the reference current generated by the band gap core circuit has a good zero-drift effect.
FIG. 3 shows a bias circuit and a rail-to-rail input circuit; the bias circuit comprises an NMOS transistor N8、N9PMOS tube P10(ii) a Band gap core circuit generates reference current IREFBy N8And N9，P10And P11The two pairs of current mirrors respectively formed provide bias voltage for the rear-stage circuit.
The rail-to-rail input circuit comprises an NMOS transistor N10、N11、N12PMOS tube P11、P12、P13Resistance R3、R4、R5(ii) a NMOS tube N10、N11And PMOS transistor P12、P13Forming a rail-to-rail input structure, MOS transistor P11And N12As a current source for supplying current to the rail-to-rail input structure, inputting the differential pair N10And N11The input common mode voltage can approach or even exceed the power supply VDD, but after the input common mode voltage is reduced to a certain degree, the NMOS differential input pair cannot work due to the non-ideality of the bias current source and the threshold voltage of the MOS transistor. PMOS input differential pair P12And P14The input common mode voltage can be close to the power ground GND, but when the input common mode voltage rises to a certain degree, the PMOS input differential pair cannot work due to the non-ideality of the bias current source and the existence of the threshold voltage of the MOS transistor. After the two input differential pairs are used in parallel, the rail-to-rail input common-mode voltage can be realized by utilizing the complementarity of the input common-mode voltages of the two input differential pairs.
FIG. 4 shows an intermediate stage circuit including an NMOS transistor N and a class AB output circuit13、N14、N15、N16、N17、N18PMOS tube P14、P15、P16、P17、P18、P19Resistance R6、R7Capacitor C1、C2、C3、C4(ii) a The intermediate stage circuit is mainly composed of P17、P18And N13、N14The common gate circuit is used as core to amplify the input signal and bias voltage (V) generated by the bias circuitb1、Vb2) By P14、P15、P16And N16、N17、N18Providing a bias voltage for the mid-stage circuit. At point P, N15Source and N13Gate of and N14Is connected to a first bias voltage (V)b1) Let P15And N15Conducting at point P, N13And N14Providing a bias voltage VbpWhen the PMOS differential pair transistors of the input stage work, N is ensured13And N14The formed common gate circuit works normally. At point N, P19Source and P of17Gate and P of18Is connected to a second bias voltage (V)b1) Make N18And P19Conducting at point N and P17And P18Providing a bias voltage VbnWhen the NMOS differential pair transistor of the input stage works, P is ensured17And P18The formed common grid circuit works normally.
At point P, bias voltage VbpEqual to:
at point N, bias voltage VbnEqual to:
P15、N15and R6Formed a path other than N13And N14Is provided with a bias, N15The grid of the positive feedback loop is connected with the output end of the intermediate stage circuit to form a positive feedback loop. When the PMOS differential pair transistors of the input stage are working, N13And N14As an input point of the common-gate amplifier circuit, P14、P16、P17And P18And a cascode structure is formed to be used as a load of the common-gate amplifier circuit, and the gain of the circuit is as follows:
but N is15The grid of the intermediate stage circuit is connected with the output end of the intermediate stage circuit, the amplification factor of the intermediate stage circuit is increased by a positive feedback loop formed by the grid of the intermediate stage circuit, and the gain of introducing the positive feedback is as follows:
also, when the NMOS differential pair transistor of the input stage is operated, R7、P19And N17Formed a path other than P17And P18In addition to the gate providing the bias voltage, P19The grid of the positive feedback loop is connected with the output end of the intermediate stage circuit to form a positive feedback loop. The structure design not only provides bias voltage for normal operation of the core structure of the intermediate stage circuit, but also improves the gain of the intermediate stage amplifying circuit
Is expanded in magnitude to
The gain of the whole intermediate-stage circuit is improved while the normal work of the intermediate-stage circuit is ensured.
The rail-to-rail output circuit comprises an NMOS tube N19、N20PMOS tube P20、P21(ii) a The output circuit adopts an active load differential structure to realize rail-to-rail output, and the rail-to-rail output is realized while the output current variable quantity equivalent to the output of double ends can be obtained through the connection method of double-end input and single-end output. Four capacitors are connected between the input end of the intermediate stage circuit and the output end of the whole operational amplifier as Miller compensation,the overall performance of the operational amplifier is guaranteed.
Due to the influence of factors such as process defects, device mismatch, input stage voltage and the like, the offset voltage is overlarge, and the precision of a digital-analog or analog-digital converter is further influenced. In order to reduce the offset voltage, a correction circuit needs to be designed to correct the offset voltage to be close to an ideal value. FIG. 5 shows an offset voltage calibration circuit, which includes a resistor RC1、RC2、RC3、RC4、RP1、RP2、RP3、RP4Switch S1、S2、S3、S4、K1、K2、K3、K4(ii) a Offset voltage correction circuit-replacement of resistor R in FIG. 3CThe second offset voltage correction circuit replaces the resistor R in FIG. 3P。
When switching on (S)1～S4) A resistor (R) connected to it when conductingC1～RC4) In the access circuit, when switching on/off (S)1～S4) A resistor (R) connected to it when turned offC1～RC4) Not connected into the circuit. By controlling the on/off of the switch through digital logic, when the logic correction signal controls the switch S1Closed, only RC1Accessing into the circuit; when the logic correction signal controls the switch S2Closed, only RC2Accessing into the circuit; when the logic correction signal controls the switch S3Closed, only RC3Accessing into the circuit; when the logic correction signal controls the switch S4Closed, only RC4Accessing into the circuit; when switch (K)1～K4) A resistor (R) connected to it when conductingP1～RP4) In the access circuit, when the switch (K)1～K4) A resistor (R) connected to it when turned offP1～RP4) Not connected into the circuit. The switch K is controlled by the logic correction signal when the switch is turned on or off by the digital logic control1Closed, only RP1Accessing into the circuit; when the logic correction signal controls the switch K2Closed, only RP2Accessing into the circuit; when the logic correction signal controls the switch K3The closing process is carried out in a closed mode,only RP3Accessing into the circuit; when the logic correction signal controls the switch K4Closed, only RP4And accessing into the circuit. By controlling the on and off of the switch through digital logic, one resistor is connected into the circuit independently, two resistors are connected into the circuit in parallel, three resistors are connected into the circuit in parallel or four resistors are connected into the circuit in parallel, and then the resistor R in the figure 3CThere will be 15 possible resistances, and similarly, the resistor RPThere will also be 15 possible resistances, by judicious choice of RCAnd RPThe resistance value of the operational amplifier and the resistance for regulating the offset voltage have 225 choices, and the offset voltage of the operational amplifier can be corrected to be close to an ideal value with high precision through the circuit design.
As shown in fig. 6, the circuit is a complete circuit of an embodiment of a rail-to-rail operational amplifier capable of correcting offset voltage, and includes a start-up circuit, a bandgap core circuit, a bias circuit, a rail-to-rail input circuit, an offset voltage correction circuit, an intermediate stage circuit, and a rail-to-rail output circuit.
Claims (2)
1. A track-to-track operational amplifier capable of correcting offset voltage comprises an offset voltage correction circuit and is characterized in that: the offset voltage correction circuit comprises a resistor RC1、RC2、RC3、RC4、RP1、RP2、RP3And RP4Switch S1、S2、S3、S4、K1、K2、K3And K4(ii) a Resistance RC1、RC2、RC3And RC4The first terminal of the resistor is connected with a power supply VDD and a resistor RC1Second terminal and switch S1Is connected to the first terminal of resistor RC2Second terminal and switch S2Is connected to the first terminal of resistor RC3Second terminal and switch S3Is connected to the first terminal of resistor RC4Second terminal and switch S4Is connected to the first terminal of, switch S1、S2、S3And S4Is connected to a first correction output signal Control 1; resistance RP1、RP2、RP3And RP4First end ofThe sub-connection power supply VDD and the resistor RP1Second terminal of and switch K1Is connected to the first terminal of resistor RP2Second terminal of and switch K2Is connected to the first terminal of resistor RP3Second terminal of and switch K3Is connected to the first terminal of resistor RP4Second terminal of and switch K4Is connected to the first terminal of the switch K1、K2、K3And K4Is connected to the second correction output signal Control 2.
2. The rail-to-rail operational amplifier of claim 1, further comprising a rail-to-rail input circuit comprising an NMOS transistor N10、N11And N12PMOS tube P11、P12And P13Resistance R3、R4And R5(ii) a PMOS tube P11The source electrode of the PMOS transistor is connected with a power supply VDD and a PMOS tube P11And a first bias voltage Vb1Connected, PMOS tube P11Drain electrode of (1) and PMOS tube P12、P13Source electrode of (1) is connected with a PMOS tube P12Grid and NMOS transistor N10And the second input signal V of the operational amplifier-Connected, PMOS tube P13Grid and NMOS transistor N11Gate of and operational amplifier first input signal V+Connected, PMOS tube P12Drain electrode of (1), resistor R3First terminal of and PMOS differential pair transistor second current IP-Connected, PMOS tube P13Drain electrode of (1), resistor R5First terminal of (1) and PMOS differential pair transistor first current IP+Connected, NMOS tube N10Drain electrode of the NMOS differential pair transistor, and NMOS differential pair transistor first current In+NMOS transistor N connected to the first correction output signal Control111Drain electrode of the NMOS differential pair transistor, and second current I of the NMOS differential pair transistorn-NMOS transistor N connected to the second correction output signal Control210、N11Source electrode and NMOS transistor N12Drain electrode of (1) NMOS tube N12Gate and resistor R of4Is connected to the first terminal of resistor R4And a second terminal of the second bias voltage Vb2Connected, NMOS tube N12The source electrode of,Resistance R3Second terminal and resistor R5Is grounded.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112332786A (en) * | 2020-10-30 | 2021-02-05 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Chip-level fully-integrated low-gain temperature-drift radio frequency amplifier |
| CN117176083A (en) * | 2023-08-11 | 2023-12-05 | 深圳高铂科技有限公司 | Pre-amplifying circuit for detecting voltage level of high-speed large-swing signal |
-
2019
- 2019-10-25 CN CN201921800453.7U patent/CN210609074U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112332786A (en) * | 2020-10-30 | 2021-02-05 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Chip-level fully-integrated low-gain temperature-drift radio frequency amplifier |
| CN112332786B (en) * | 2020-10-30 | 2023-09-05 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Chip-level fully-integrated low-gain temperature drift radio frequency amplifier |
| CN117176083A (en) * | 2023-08-11 | 2023-12-05 | 深圳高铂科技有限公司 | Pre-amplifying circuit for detecting voltage level of high-speed large-swing signal |
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Effective date of registration: 20240703 Address after: Room 308, science and technology building, 149 Yanchang Road, Jing'an District, Shanghai 200072 Patentee after: SHANGHAI CANRUI TECHNOLOGY Co.,Ltd. Country or region after: China Address before: 541004 No. 15 Yucai Road, Qixing District, Guilin, the Guangxi Zhuang Autonomous Region Patentee before: Guangxi Normal University Country or region before: China |