CN210273824U - High-speed drive circuit of field control type power electronic device - Google Patents
High-speed drive circuit of field control type power electronic device Download PDFInfo
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- CN210273824U CN210273824U CN201921579443.5U CN201921579443U CN210273824U CN 210273824 U CN210273824 U CN 210273824U CN 201921579443 U CN201921579443 U CN 201921579443U CN 210273824 U CN210273824 U CN 210273824U
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Abstract
The utility model discloses a high-speed drive circuit of field control type power electronic device relates to power electronic technology field. The circuit comprises a signal isolation sub-circuit, an amplification sub-circuit and a switch sub-circuit which are connected in sequence; the switch sub-circuit comprises a first capacitor and a second capacitor which are connected to the amplification sub-circuit, the first capacitor is connected to a first diode and a second diode through a first resistor, the first capacitor is further connected with a PMOS (P-channel metal oxide semiconductor) tube, the second capacitor is connected to a third diode and a fourth diode through a second resistor, the second capacitor is further connected with an NMOS (N-channel metal oxide semiconductor) tube, and the PMOS tube and the NMOS tube are respectively connected to the power electronic device through a third resistor and a fourth resistor; the PMOS tube is connected to a first power voltage, and the NMOS tube is grounded. The utility model discloses the drive speed of circuit is faster, can adapt to the drive needs of higher frequency.
Description
Technical Field
The utility model relates to a power electronic technology field especially relates to a high-speed drive circuit of power electronic device.
Background
The totem pole circuit is generally used for driving a power MOS Transistor (Metal Oxide Semiconductor) or an IGBT (Insulated Gate Bipolar Transistor) to provide sufficient sinking current and sourcing current for the power MOS Transistor or the IGBT.
In a conventional totem-pole circuit, the circuit is generally formed by connecting an NMOS tube with a PMOS tube, the source electrode of the NMOS tube is connected with the source electrode of the PMOS tube, the drain electrode of the NMOS tube is connected with a power supply voltage, and the drain electrode of the PMOS tube is grounded or negative voltage. The circuit has the advantage that one control signal can be simultaneously applied to the gates of the NMOS transistor and the PMOS transistor, so that the NMOS transistor and the PMOS transistor are controlled to be switched on or switched off. When the control signal is at a high level, the NMOS tube is switched on, the PMOS tube is switched off, and the power supply charges the gate emitter capacitor of the power electronic device IGBT through the on-resistance of the NMOS tube; when the control signal is at a low level, the NMOS tube is turned off, the PMOS tube is turned on, and the power supply discharges the gate emitter capacitor of the power electronic device IGBT through the on-resistance of the PMOS tube. The totem pole circuit has the advantages that the charging and discharging resistances of the gate emitter capacitor of the power electronic device IGBT are very small, but the totem pole circuit has the following three defects:
firstly, the rising edge and the falling edge of a control signal cannot be steep at the same time, if the rising edge is made fast, the falling edge is slow, and conversely, if the falling edge is made fast, the rising edge is slow, and the rising edge and the falling edge cannot be ensured to be fast at the same time;
secondly, the control signal changes slowly near the ground potential or near the power supply voltage, so that the circuit can control the IGBT of the power electronic device to be switched on or switched off slowly;
and thirdly, the source electrode voltage of the NMOS tube and the PMOS tube dynamically changes along with the grid electrode voltage, so that the NMOS tube or the PMOS tube is in a critical turn-on state.
SUMMERY OF THE UTILITY MODEL
A primary object of the present invention is to provide a high-speed driving circuit for field-controlled power electronic devices, which is capable of improving the driving speed and output frequency of the driving circuit.
In order to achieve the above object, the present invention provides a high-speed driving circuit of a field-controlled power electronic device, wherein the circuit comprises a signal isolation sub-circuit, an amplification sub-circuit and a switch sub-circuit which are connected in sequence;
the switch sub-circuit comprises a first capacitor and a second capacitor which are connected to the amplification sub-circuit, the first capacitor is connected to a first diode and a second diode through a first resistor, the first capacitor is further connected with a PMOS (P-channel metal oxide semiconductor) tube, the second capacitor is connected to a third diode and a fourth diode through a second resistor, the second capacitor is further connected with an NMOS (N-channel metal oxide semiconductor) tube, and the PMOS tube and the NMOS tube are respectively connected to the power electronic device through a third resistor and a fourth resistor; the PMOS tube is connected to a first power voltage, and the NMOS tube is grounded.
Preferably, one end of the first capacitor is connected to the amplifier sub-circuit, the other end of the first capacitor is connected to the gate of the PMOS transistor and one end of a first resistor, the other end of the first resistor is connected to the cathode of the first diode and the anode of the second diode, and the anode of the first diode and the cathode of the second diode are connected to the first power voltage;
the source electrode of the PMOS tube is connected to the first power supply voltage, the drain electrode of the PMOS tube is connected to one end of the third resistor, and the other end of the third resistor is connected to the grid electrode of the power electronic device;
one end of the second capacitor is connected to the amplifier sub-circuit, the other end of the second capacitor is connected to the grid electrode of the NMOS tube and one end of the second resistor, the other end of the second resistor is connected to the cathode of the third diode and the anode of the fourth diode, and the anode of the third diode and the cathode of the fourth diode are grounded;
the drain electrode of the NMOS tube is connected to one end of the fourth resistor, the other end of the fourth resistor is connected to the grid electrode of the power electronic device, and the source electrode of the NMOS tube is grounded.
Preferably, the switch sub-circuit further comprises a third capacitor and a fifth diode; one end of the third capacitor is connected to the first power voltage and the source electrode of the PMOS tube, and the other end of the third capacitor is grounded;
and the anode of the fifth diode is grounded, and the cathode of the fifth diode is connected to the grid of the power electronic device, the other end of the third resistor and the other end of the fourth resistor.
Preferably, the PMOS transistor and the NMOS transistor are field effect transistors with low threshold voltage.
Preferably, the signal isolation sub-circuit comprises a high-speed optocoupler.
Preferably, the high-speed optical coupling device is TLP 117; a first pin of the TLP117 is a control signal input terminal for connecting a control signal; the fourth pin is grounded; a fifth pin of the amplifier is connected to the amplifying sub-circuit and used for outputting a first control voltage to the amplifying sub-circuit; the sixth pin is connected to the second supply voltage.
Preferably, the amplifying sub-circuit comprises a comparator, a fifth resistor, a sixth resistor, a seventh resistor and a fourth capacitor;
a comparison output end of the comparator is connected to the first capacitor and the second capacitor of the switch sub-circuit through a fifth resistor, a non-inverting input end of the comparator is connected to a fifth pin of the TLP117, an inverting input end of the comparator is connected to one end of the sixth resistor and one end of a seventh resistor, the other end of the sixth resistor is connected to a second power supply voltage, the other end of the seventh resistor is grounded, a voltage end of the comparator is connected to the second power supply voltage, and a ground end of the comparator is grounded;
one end of the fourth capacitor is connected to the second power voltage, and the other end of the fourth capacitor is grounded.
Preferably, the first power voltage has a value of 9V to 20V, and the second power voltage has a value of 4V to 9V.
Preferably, the first power voltage has a value of 15V and the second power voltage has a value of 5V.
The utility model discloses technical scheme's beneficial effect does:
1. the source electrode of the PMOS tube is connected with a power supply, the source electrode of the NMOS tube is grounded or a negative power supply, the drain electrodes of the PMOS tube and the NMOS tube are connected through a third resistor and a fourth resistor, and a driving control signal is output from the middle position of the third resistor and the fourth resistor, so that the PMOS tube or the NMOS tube is in a fully-open or fully-closed state in the working process, and the charging and discharging speed of a capacitor between a grid emitter and a grid source electrode of the field control type power electronic device can be accelerated;
2. the first capacitor connected between the grid of the PMOS tube and the amplification sub circuit can control the change of a high-order signal of the grid of the PMOS tube by using low-order signal voltage, and realize signal transmission among different voltage levels;
3. the second capacitor is connected between the grid of the NMOS tube and the amplifying sub-circuit, and has the advantages that the threshold voltage value of the grid control voltage of the NMOS tube can be enabled to be in the middle of the upper level and the lower level of the grid control signal, the change speed of the middle value is fastest, and therefore the second control voltage V output by the amplifying sub-circuit is enabled to be output2The conduction and the disconnection of the NMOS tube can be accelerated;
4. the grid electrode of the PMOS tube is connected with a charge-discharge branch circuit formed by first power voltage and a charge-discharge branch circuit formed by grounding or negative power of the grid electrode of the NMOS tube, and the charge-discharge branch circuit can keep the grid electrode of the PMOS tube and the grid electrode of the NMOS tube at proper voltage and keep the grid electrode voltage change of the PMOS tube and the NMOS tube within a reasonable range.
Drawings
Fig. 1 is a schematic circuit diagram of a high-speed driving circuit of a field-control power electronic device according to the present invention;
fig. 2 is a schematic circuit diagram of the high-speed driving circuit of the field-control power electronic device according to the present invention.
The objects, features and advantages of the present invention will be further described with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The present invention will be further explained with reference to the accompanying drawings.
The utility model discloses mainly used provides high-speed driving force for field control type power electronic device.
As shown in fig. 1 and fig. 2, an embodiment of the present invention provides a high-speed driving circuit of a field-control power electronic device, where the circuit includes a signal isolation sub-circuit 101, an amplification sub-circuit 102, and a switch sub-circuit 103, which are connected in sequence;
as shown in fig. 2, the switch sub-circuit 103 includes a first capacitor C1 and a second capacitor C2 connected to the amplifier sub-circuit 102, the first capacitor C1 is connected to a first diode D1 and a second diode D2 through a first resistor R1, the first capacitor C1 is further connected to a PMOS transistor M1, the second capacitor C2 is connected to a third diode D3 and a fourth diode D4 through a second resistor R2, the second capacitor C2 is further connected to an NMOS transistor M2, and the PMOS transistor M1 and the NMOS transistor M2 are connected to a power electronic device Q1 through a third resistor R3 and a fourth resistor R4, respectively; the PMOS transistor M1 is connected to a first power voltage VCC1, and the NMOS transistor M2 is connected to GND.
The signal isolation sub-circuit 101 inputs the control signal IinConverted into a first control voltage V1(ii) a The amplifier sub-circuit 102 amplifies the first control voltage V1Amplifying to output a second control voltage V2(ii) a The switch sub-circuit 103 passes a second control voltage V2Generating a third control voltage V3To control the turn on and turn off of the power electronics Q1. The power electronic device Q1 may be an IGBT or a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor).
Because the embodiment of the utility model provides a connect first supply voltage VCC1 with PMOS pipe M1's source, NMOS pipe M2's source ground connection GND or negative supply, PMOS pipe M1 and NMOS pipe M2's drain electrode passes through third resistance R3 and fourth resistance R4 and connects, drive control signal is followed third resistance R3 and fourth resistance R4 intermediate position and is exported, make PMOS pipe M1 or NMOS pipe M2 be in full-on or full-off state in the course of the work, can accelerate field control type power electronic device Q1's grid emitter or the electric capacity charge-discharge speed between the grid source.
The first capacitor C1 connected between the gate of the PMOS transistor M1 and the amplifier sub-circuit 102 can control the change of the high-order signal of the gate of the PMOS transistor M1 by using the low-order signal voltage,and signal transmission among different voltage levels is realized. The second capacitor C2 and the second capacitor C2 connected between the gate of the NMOS transistor M2 and the amplifying sub-circuit 102 have the advantage that the threshold voltage value of the gate control voltage of the NMOS transistor M2 can be intermediate between the upper level and the lower level of the gate control signal, and the intermediate value can change at the fastest speed, so that the second control voltage V output by the amplifying sub-circuit2The turn-on and turn-off of the NMOS transistor M2 can be accelerated.
The grid electrode of the PMOS tube M1 is connected with a charge-discharge branch composed of a first power supply voltage VCC1 and a charge-discharge branch composed of a grid electrode grounding ground GND or a negative power supply of the NMOS tube M2, and the charge-discharge branch can keep proper voltage of the grid electrode of the PMOS tube M1 and the grid electrode of the NMOS tube M2, and keep the grid electrode voltage change of the PMOS tube M1 and the grid electrode voltage change of the NMOS tube M2 in a reasonable range.
As shown in fig. 2, one end of the first capacitor C1 is connected to the amplifier sub-circuit 102, the other end is connected to the gate of the PMOS transistor M1 and one end of a first resistor R1, the other end of the first resistor R1 is connected to the cathode of the first diode D1 and the anode of the second diode D2, the anode of the first diode D1 and the cathode of the second diode D2 are connected to the first power voltage VCC 1; the source of the PMOS transistor M1 is connected to the first power voltage VCC1, the drain of the PMOS transistor M1 is connected to one end of the third resistor R3, and the other end of the third resistor R3 is connected to the gate of the power electronic device Q1; one end of the second capacitor C2 is connected to the amplifier sub-circuit 102, the other end is connected to the gate of the NMOS transistor M2 and one end of the second resistor R2, the other end of the second resistor R2 is connected to the cathode of the third diode D3 and the anode of the fourth diode D4, and the anode of the third diode D3 and the cathode of the fourth diode D4 are grounded to GND; the drain of the NMOS transistor M2 is connected to one end of the fourth resistor R4, the other end of the fourth resistor R4 is connected to the gate of the power electronic device Q1, and the source of the NMOS transistor M2 is grounded to GND.
In the embodiment of the present invention, the connection mode of the PMOS transistor M1 and the NMOS transistor M2 is opposite to the totem pole connection mode in the prior art. The PMOS transistor M1 is at the upper end, is turned on when the grid voltage is lower than the source voltage and is turned off when the grid voltage is higher than the source voltage; the NMOS transistor M2 is at the lower end, and is turned on when the grid voltage is higher than the source voltage and turned off when the grid voltage is lower than the source voltage; therefore, the requirements of the PMOS transistor M1 and the NMOS transistor M2 are separately controlled by different control signals. When the power electronic device Q1 needs to be turned on, the PMOS transistor M1 is turned on, the NMOS transistor M2 is turned off, and the first power supply voltage VCC1 charges the gate-emitter capacitor of the power electronic device Q1 through the on-state resistance of the PMOS transistor M1 and the third resistance R3; in order to increase the charging speed, the resistance of the third resistor R3 is small, and the current is mainly limited to the charging loop, so that the charging current does not exceed the maximum allowable value of the PMOS transistor M1. When the power electronic device Q1 needs to be turned off, the PMOS transistor M1 is turned off, the NMOS transistor M2 is turned on, and the gate-emitter capacitor of the power electronic device Q1 discharges through the on-state resistor of the NMOS transistor M2 and the fourth resistor R4; in order to increase the discharge speed, the resistance of the fourth resistor R4 is small, which mainly limits the current of the discharge loop so that the discharge current does not exceed the maximum allowable value of the NMOS transistor M2. Thus, the gate-emitter capacitance of the power electronic device Q1 is charged and discharged at a high speed, so that the driving speed of the power electronic device Q1 is increased.
As shown in fig. 2, the switch sub-circuit 103 further includes a third capacitor C3 and a fifth diode D5; one end of the third capacitor C3 is connected to a first power voltage VCC1 and the source of the PMOS transistor M1, and the other end is grounded GND; the anode of the fifth diode D5 is grounded GND, and the cathode thereof is connected to the gate of the power electronic device Q1, the other end of the third resistor R3, and the other end of the fourth resistor R4.
Preferably, the PMOS transistor M1 and the NMOS transistor M2 are field effect transistors with low threshold voltage. The field effect transistor with low threshold voltage can be ensured at the second control voltage V2And normally switching on and off.
When the frequency of the control signal is fast enough or the first resistor R1 and the second resistor R2 are large enough, the gate voltage of the NMOS transistor M2 is about + -0.5V2The grid voltage of the PMOS transistor M1 is changed at the first power voltage VCC1 +/-0.5V2And (4) change. The grid threshold voltage points of the PMOS transistor M1 and the NMOS transistor M2 are in the interval with the fastest change on the charging and discharging curve of the grid-source capacitance, so that the interval is avoidedThe slow interval at the end of the charge and discharge of the capacitor is formed, so that the switching speed of the PMOS transistor M1 and the switching speed of the NMOS transistor M2 are increased, and the driving speed of the power electronic device Q1 is increased.
In the gate emitter capacitance to power electronic device Q1 carries out the point in-process of charging and discharging, PMOS pipe M1 and NMOS pipe M2 are all in the state of full-open full-close, make the utility model discloses a drive circuit is faster to the charge-discharge speed of the gate emitter capacitance to power electronic device Q1 to improve the drive speed to power electronic device Q1.
Preferably, the signal isolation sub-circuit 101 includes a high-speed optical coupler device.
As shown in fig. 2, the high-speed optical coupling device is a TLP 117; a first pin 1 of the TLP117 is a control signal input end for connecting a control signal Iin(ii) a The fourth pin 4 is grounded GND; a fifth pin 5 connected to the amplifier sub-circuit 102 for outputting a first control voltage V1To the amplification sub-circuit 102; and its sixth pin 6 is connected to a second supply voltage VCC 2.
In a power electronic circuit or system, the emitter (or source) of the power electronic device Q1 is floating, and due to the potential difference with ground, the driver circuit needs to be isolated from the power electronic device Q1. And the transmission speed of optoisolation is faster than the transmission speed of electromagnetic isolation, so, in the embodiment of the utility model provides an, select the opto-coupler device TLP117 that present speed is very fast as signal isolation.
As shown in fig. 2, the amplifying sub-circuit 102 includes a comparator a, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7 and a fourth capacitor C4; a comparison output end of the comparator a is connected to the first capacitor C1 and the second capacitor C2 of the switch sub-circuit 103 through a fifth resistor R5, a non-inverting input end of the comparator a is connected to the fifth pin 5 of the TLP117, an inverting input end of the comparator a is connected to one end of the sixth resistor R6 and one end of a seventh resistor R7, the other end of the sixth resistor R6 is connected to a second power voltage VCC2, the other end of the seventh resistor R7 is grounded to GND, a voltage end of the comparator a is connected to the second power voltage VCC2, and the ground end of the comparator a is grounded to GND; one end of the fourth capacitor C4 is connected to the second power voltage VCC2, and the other end is grounded GND.
The comparator a amplifies the output signal of the optocoupler TLP117 to meet the requirement of high-speed signal transmission, so that the driving capability of the optocoupler TLP is amplified by the comparator a to meet the driving requirement of subsequent devices. Meanwhile, the comparator A uses positive feedback inside, so that the speed of the comparator A is higher than that of an operational amplifier device.
In some embodiments, the first power voltage VCC1 has a value of 9V to 20V and the second power voltage VCC2 has a value of 4V to 9V.
In a specific embodiment, the first power voltage VCC1 has a value of 15V, and the second power voltage VCC2 has a value of 5V.
The embodiment of the utility model provides a theory of operation does:
in the quiescent state, the second control voltage V2When the voltage of the first capacitor C1 and the gate-source capacitance of the PMOS transistor M1 is lower than the first power supply voltage VCC1 by a first diode D1 junction voltage (about 0.7V), the charging is stopped, and the PMOS transistor M1 maintains a micro-conduction state, the gate voltage of the NMOS transistor M2 is high, the NMOS transistor M2 is turned on, and simultaneously, the first power supply voltage VCC1 charges the first capacitor C1 and the gate-source capacitance of the PMOS transistor M1 through the first diode D1 and the first resistor R1.
In steady state, when the second control voltage V2When the voltage changes from high level (about 5V) to low level (about 0V), the second control voltage V2After the voltage is superposed on the voltage on the second capacitor C2, the gate voltage of the NMOS transistor M2 changes from positive voltage to negative voltage, the NMOS transistor M2 is turned off, and simultaneously the gate-source capacitance of the NMOS transistor M2 is charged through the third diode D3 and the second resistor R2, and when the gate-source capacitance voltage of the NMOS transistor M2 is equal to the junction voltage (about 0.7V) of the third diode D3, the charging is stopped. When the second control voltage V is applied2When the voltage changes from high level (about 5V) to low level (about 0V), the second control voltage V2After the voltage is superposed with the voltage on the first capacitor C1, the gate voltage of the PMOS tube M1 is lower than the first power supply voltage VCC1, the voltage of the gate source of the PMOS tube M1 is negative, so that the PMOS tube M1 is conducted to charge the gate-emitter capacitor of the power electronic device Q1, and meanwhile, the gate source of the PMOS tube M1 is connected with the gate source of the power electronic device Q1The gate capacitance is charged through the first diode D1 and the first resistor R1, and when the gate-source capacitance voltage is equal to the junction voltage (about-0.7V) of the first diode D1, the charging is stopped, so that the PMOS transistor M1 can be kept in a micro-conduction state, the leakage current of the gate emitter capacitance of the power electronic device Q1 is supplemented, the gate emitter capacitance voltage of the power electronic device Q1 is kept unchanged, and the power electronic device Q1 is kept in conduction.
When the second control voltage V2When the voltage changes from low level (about 0V) to high level (about 5V), the second control voltage V2After the voltage is superposed on the voltage on the second capacitor C2, the gate voltage of the NMOS transistor M2 becomes a high voltage, the NMOS transistor M2 is turned on to discharge the gate-emitter capacitor of the power electronic device Q1, and at the same time, the gate-source capacitor of the NMOS transistor M2 is discharged through the fourth diode D4 and the second resistor R2, and when the gate-source capacitor voltage thereof is equal to the junction voltage (about 0.7V) of the fourth diode D4, the discharge is stopped. When the second control voltage V2 changes from a low level (about 0V) to a high level (about 5V), the second control voltage V2The voltage is superposed with the voltage on the first capacitor C1, so that the gate voltage of the PMOS tube M1 is higher than the first power supply voltage VCC1, the voltage of the gate-source electrode of the PMOS tube M1 is positive, the PMOS tube M1 is turned off, the gate-source electrode capacitance of the PMOS tube M1 is charged through the first diode D1 and the first resistor R1, and when the voltage of the gate-source electrode capacitance is equal to the junction voltage (about-0.7V) of the first diode D1D1, the charging is stopped.
It should be understood that the above is only a preferred embodiment of the present invention, and the scope of the present invention is not limited thereto, and all the equivalent structures or equivalent flow changes made by the contents of the specification and the drawings or directly or indirectly applied to other related technical fields are also included in the scope of the present invention.
Claims (9)
1. A high-speed drive circuit of a field control type power electronic device is characterized in that the circuit comprises a signal isolation sub-circuit, an amplification sub-circuit and a switch sub-circuit which are sequentially connected;
the switch sub-circuit comprises a first capacitor and a second capacitor which are connected to the amplification sub-circuit, the first capacitor is connected to a first diode and a second diode through a first resistor, the first capacitor is further connected with a PMOS (P-channel metal oxide semiconductor) tube, the second capacitor is connected to a third diode and a fourth diode through a second resistor, the second capacitor is further connected with an NMOS (N-channel metal oxide semiconductor) tube, and the PMOS tube and the NMOS tube are respectively connected to the power electronic device through a third resistor and a fourth resistor; the PMOS tube is connected to a first power voltage, and the NMOS tube is grounded.
2. The high-speed driving circuit of a field-controlled power electronic device according to claim 1, wherein one end of the first capacitor is connected to the amplifier sub-circuit, the other end of the first capacitor is connected to the gate of the PMOS transistor and one end of a first resistor, the other end of the first resistor is connected to the cathode of the first diode and the anode of the second diode, and the anode of the first diode and the cathode of the second diode are connected to the first power supply voltage;
the source electrode of the PMOS tube is connected to the first power supply voltage, the drain electrode of the PMOS tube is connected to one end of the third resistor, and the other end of the third resistor is connected to the grid electrode of the power electronic device;
one end of the second capacitor is connected to the amplifier sub-circuit, the other end of the second capacitor is connected to the grid electrode of the NMOS tube and one end of the second resistor, the other end of the second resistor is connected to the cathode of the third diode and the anode of the fourth diode, and the anode of the third diode and the cathode of the fourth diode are grounded;
the drain electrode of the NMOS tube is connected to one end of the fourth resistor, the other end of the fourth resistor is connected to the grid electrode of the power electronic device, and the source electrode of the NMOS tube is grounded.
3. The high-speed driving circuit of a field-controlled power electronic device according to claim 2, wherein the switch sub-circuit further comprises a third capacitor and a fifth diode; one end of the third capacitor is connected to the first power voltage and the source electrode of the PMOS tube, and the other end of the third capacitor is grounded;
and the anode of the fifth diode is grounded, and the cathode of the fifth diode is connected to the grid of the power electronic device, the other end of the third resistor and the other end of the fourth resistor.
4. The high-speed driving circuit of a field-controlled power electronic device according to claim 3, wherein the PMOS transistor and the NMOS transistor are field effect transistors with low threshold voltages.
5. The high-speed driving circuit of a field-controlled power electronic device according to claim 1, wherein the signal isolation sub-circuit comprises a high-speed optocoupler.
6. The high-speed driving circuit of a field-controlled power electronic device according to claim 5, wherein the high-speed optocoupler device is a TLP 117; a first pin of the TLP117 is a control signal input terminal for connecting a control signal; the fourth pin is grounded; a fifth pin of the amplifier is connected to the amplifying sub-circuit and used for outputting a first control voltage to the amplifying sub-circuit; the sixth pin is connected to the second supply voltage.
7. The high-speed driving circuit of a field-controlled power electronic device according to claim 6, wherein the amplifying sub-circuit comprises a comparator, a fifth resistor, a sixth resistor, a seventh resistor and a fourth capacitor;
a comparison output end of the comparator is connected to the first capacitor and the second capacitor of the switch sub-circuit through a fifth resistor, a non-inverting input end of the comparator is connected to a fifth pin of the TLP117, an inverting input end of the comparator is connected to one end of the sixth resistor and one end of a seventh resistor, the other end of the sixth resistor is connected to a second power supply voltage, the other end of the seventh resistor is grounded, a voltage end of the comparator is connected to the second power supply voltage, and a ground end of the comparator is grounded;
one end of the fourth capacitor is connected to the second power voltage, and the other end of the fourth capacitor is grounded.
8. The high-speed driving circuit of a field-controlled power electronic device according to claim 7, wherein the first power voltage has a value of 9V to 20V, and the second power voltage has a value of 4V to 9V.
9. The high-speed driving circuit of a field-controlled power electronic device according to claim 8, wherein the first power voltage has a value of 15V and the second power voltage has a value of 5V.
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| CN201921579443.5U CN210273824U (en) | 2019-09-20 | 2019-09-20 | High-speed drive circuit of field control type power electronic device |
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| CN201921579443.5U CN210273824U (en) | 2019-09-20 | 2019-09-20 | High-speed drive circuit of field control type power electronic device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110492725A (en) * | 2019-09-20 | 2019-11-22 | 成都信息工程大学 | A kind of high-speed driving circuit of control type power electronic device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110492725A (en) * | 2019-09-20 | 2019-11-22 | 成都信息工程大学 | A kind of high-speed driving circuit of control type power electronic device |
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