CN210243853U

CN210243853U - Clock generating device suitable for node seismograph

Info

Publication number: CN210243853U
Application number: CN201920076190.3U
Authority: CN
Inventors: Yang Yang; 杨阳; Xin Hu; 胡鑫; Xiaolu Yu; 俞小露; Xuefeng Tang; 唐学峰; Jing Chen; 陈静
Original assignee: HEFEI GUOWEI ELECTRONICS CO Ltd
Current assignee: HEFEI GUOWEI ELECTRONICS CO Ltd
Priority date: 2019-01-16
Filing date: 2019-01-16
Publication date: 2020-04-03
Anticipated expiration: 2029-01-16

Abstract

The utility model discloses a clock produces device suitable for node seismograph belongs to geophysical exploration technical field, include: the system comprises a crystal oscillator, a GPS module and a singlechip; the output interface of the GPS module is connected with the general input/output interface of the singlechip, the voltage output pin of the singlechip is connected with the voltage control pin of the crystal oscillator, and the clock signal output pin of the crystal oscillator is connected with the input interface of the singlechip and synchronously outputs the corrected clock signal to the ADC. The utility model provides a scheme is compared and is adopted the frequency division coefficient who increases its inside counter of FPGA dynamic adjustment to come indirect tuning crystal oscillator frequency's method in traditional node formula seismograph, and it can reduce the consumption of whole instrument to below half. Compared with a node type seismograph without crystal oscillator frequency correction, the aging index can be greatly improved, so that the synchronization error can be remarkably reduced when the node type seismograph is used for collecting for a long time, and the data collecting precision and the precision of subsequent data processing section inversion are improved.

Description

Clock generating device suitable for node seismograph

Technical Field

The utility model relates to a geophysical exploration technical field, in particular to clock produces device suitable for node seismograph.

Background

The seismograph is the most commonly used instrument in the field of geophysical exploration, but the traditional seismograph almost connects each acquisition unit through a long cable, and the copper cables are very heavy and bulky, and are time-consuming and labor-consuming in field construction, and very inconvenient.

Under the condition, a cable-free seismograph is a good substitute, the cable-free seismograph is also called a node seismograph, each acquisition unit is an independent node, and the equipment is lighter and brings difficulty in synchronous acquisition of a plurality of nodes in a large range. Moreover, the seismograph needs to continuously acquire for a long time, so that the clock signal is required to have the characteristic of long-time high precision, otherwise, the data acquired by each station are asynchronous.

The clock signal is generated by a Crystal Oscillator, and the stability of the frequency of the Crystal Oscillator is mainly affected by temperature, so that the oven controlled Crystal Oscillator (OCXO) can maintain high precision for a long time, but the power consumption (500 plus 1000 mw) of the oven controlled Crystal Oscillator is too large compared with the acquisition system of only 100 to 200 mw, which greatly reduces the endurance time of the battery in field use, and the price is expensive, which is not favorable for batch production.

Some documents mention a method for calibrating a short-time high-precision crystal oscillator by using a Global Positioning System (GPS) signal, which is based on the principle that the number of high-precision crystal oscillator pulses is counted by using the GPS signal without accumulated error for a long time, and then the output frequency is dynamically adjusted by changing a frequency division coefficient in real time through a Field-Programmable Gate Array (FPGA), so as to compensate the long-time frequency drift and initial frequency offset of the crystal oscillator. However, this method is not suitable for the node seismograph, because the FPGA chip is not necessary in the node seismograph, and an additional FPGA system is required to implement the clock correction system, which is not favorable for increasing the integration level and controlling the power consumption.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a clock produces device suitable for node seismograph to reduce the consumption of seismograph.

For the purpose above, the utility model discloses a clock produces device suitable for node seismograph, include: the system comprises a crystal oscillator, a GPS module and a singlechip;

the output interface of the GPS module is connected with the general input/output interface of the single chip microcomputer, the voltage output pin of the single chip microcomputer is connected with the voltage control pin of the crystal oscillator, the clock signal output pin of the crystal oscillator is connected with the input interface of the single chip microcomputer, and the clock signal output pin of the crystal oscillator synchronously outputs the corrected clock signal to the acquisition unit.

Preferably, the single chip microcomputer is integrated with a digital-to-analog converter, an output pin of the single chip microcomputer is configured as an output pin of the digital-to-analog converter, and the output pin of the digital-to-analog converter is connected with a voltage control pin of the crystal oscillator.

Preferably, the single chip microcomputer is integrated with a counter for counting the time interval between the adjacent pulse signals.

Preferably, the counter comprises a first counter and a second counter, the first counter and the second counter being cascaded.

Preferably, the general input/output interface of the single chip microcomputer is an interrupt pin.

Preferably, the acquisition unit is an analog-to-digital converter, and an output pin of the analog-to-digital converter is connected with the SPI interface of the single chip microcomputer through a serial peripheral interface.

Preferably, the secure data input/output interface of the single chip is connected with a data storage card.

Preferably, the crystal oscillator is a voltage-controlled temperature-compensated crystal oscillator.

Compared with the prior art, the utility model discloses there are following technological effect: the utility model utilizes the clock signal of the crystal oscillator to achieve high precision in a short time, and has accumulated deviation in a long time; the pulse per second of the GPS module has not high short-time stability but no accumulated error for a long time. Therefore, the actual frequency of the crystal oscillator is measured by using the GPS second pulse, the deviation between the actual frequency and the nominal frequency is calculated, and the output frequency of the clock signal of the crystal oscillator is finely adjusted by using the deviation to adjust the control voltage of the crystal oscillator according to the right proportion.

The utility model provides a scheme is compared and is adopted the method of tuning its frequency of frequency division coefficient that increases FPGA and come dynamic adjustment crystal oscillator in traditional node formula seismograph, and it can reduce the consumption of whole instrument to below half. Compared with a node type seismograph without crystal oscillator frequency correction, the aging index can be greatly improved, so that the synchronization error can be remarkably reduced when the node type seismograph is used for collecting for a long time, and the data collecting precision and the precision of subsequent data processing section inversion are improved.

Drawings

The following detailed description of the embodiments of the present invention is made with reference to the accompanying drawings:

FIG. 1 is a schematic diagram of a clock generation device suitable for a node seismograph;

FIG. 2 is a schematic diagram of a clock generation apparatus suitable for use with a nodal seismograph.

Detailed Description

To further illustrate the features of the present invention, please refer to the following detailed description and accompanying drawings. The drawings are for reference and illustration purposes only and are not intended to limit the scope of the present disclosure.

As shown in fig. 1, the present embodiment discloses a clock generation apparatus suitable for a node seismograph, including: the system comprises a crystal oscillator 10, a GPS module 20 and a singlechip 30; the output interface of the GPS module 20 is connected to the general input/output interface of the single chip microcomputer 30, the voltage output pin of the single chip microcomputer 30 is connected to the voltage control pin of the crystal oscillator 10, the clock signal output pin of the crystal oscillator 10 is connected to the input interface of the single chip microcomputer 30, and the clock signal output pin of the crystal oscillator 10 synchronously outputs the corrected clock signal to the acquisition unit.

Wherein: because a plurality of wireless nodes need to be synchronized and the distance between the nodes is possibly far, the system realizes the synchronization between each node device by adding the GPS module 20, and although the pulse per second of the GPS module 20 has low short-time stability, the pulse per second does not have accumulated errors for a long time; meanwhile, the device also can keep a clock with higher precision in a short time, the system realizes high precision in a short time by adding the crystal oscillator 10, and the crystal oscillator has high precision in a short time but has accumulated errors for a long time.

In this embodiment, the GPS module 20 generates a Pulse Per Second (PPS) within a period of power-on, which is the number of pulses Per Second; in GPS, the GPS second pulse signal PPS is one second. The counter 31 in the single chip microcomputer 30 uses the crystal oscillator 10 to be corrected as a clock source, and measures the actual frequency of the crystal oscillator 10 by using the GPS second pulse within a period of time. And obtaining a current real-time frequency offset value of the crystal oscillator 10 by using the actual frequency and the standard frequency of the crystal oscillator 10, tuning the crystal oscillator 10 by using the real-time frequency offset value, correcting the clock signal output by the crystal oscillator 10, and outputting the corrected clock signal to an acquisition unit of the seismograph.

It should be noted that the GPS pulse-per-second signal is used to indicate the time of the whole second, which is usually indicated by the rising edge of the PPS pulse. The GPS can give out Coordinated Universal Time (UTC), a user has Time delay when receiving the Time, in order to accurately Time, the rising edge of a PPS signal is introduced to mark the whole second Time of the UTC, the precision is very high and can reach nanosecond level, and no accumulated error exists. Therefore, in this embodiment, a general purpose input output interface (GPIO) of the single chip microcomputer 30 is configured as an interrupt pin, each time a rising edge of the PPS arrives, the interrupt process is entered, and in the process, a current value of the counter 31 is recorded and a restart counter 31 (TIMER) is reset, the counter 31 counts intervals between adjacent second pulses by using the crystal oscillator 10 to be corrected as a clock source, and after a period of continuous recording, an average value of the counts in the period of time is used as a clock signal frequency of the period of time.

Preferably, if the counter 31 integrated on the single chip 30 is 16 bits, and the count of the clock within 1 second obviously exceeds 65536, the counter 31 integrated on the single chip 30 in this embodiment includes a first counter and a second counter, and the first counter and the second counter are cascaded. Wherein: the first counter is configured to use the external clock to be corrected as a clock source, and the operation mode is configured to count up, and when the count reaches 65536, an overflow event is generated, and the count value is automatically reset to 0. The internal event is used as the clock of the second counter, so that a 32-bit counter can be realized to meet the counting requirement.

Preferably, the single chip microcomputer 30 is integrated with a digital-to-analog converter 32 (DAC), an output pin of the single chip microcomputer 30 is configured as an output pin of the digital-to-analog converter 32, and the output pin of the digital-to-analog converter 32 is connected with a voltage control pin of the crystal oscillator 10. In this embodiment, the chip 30 converts the corrected voltage value into a 12-bit DAC register value and writes the value to be output to the voltage control pin of the crystal 10.

It should be noted that the clock generation apparatus operates according to the following principle:

the counter counts the interval between adjacent second pulses with the crystal 10 to be corrected as a clock source, and continuously records n seconds later (for example, 60 seconds), and takes the average value of the n second counts as the frequency of the period. This average count value is compared to its standard count value. For example, if the crystal 10 frequency is 19.2MHz, then the standard count value for its 1 second interval is 19200000, and the current real-time frequency offset (in parts per million, ppm) is the count value minus 19200000 divided by 19.2. The crystal 10 is then tuned according to this frequency offset. Assuming that the crystal 10 used in this embodiment is a voltage controlled temperature compensated crystal 10VCTCXO, model LFTVXO076344, the frequency offset adjustment amplitude is +7ppm/V, which indicates that the frequency will rise by 7ppm (seven parts per million) for every 1V voltage increase from 1.5V standard input on its voltage control pin. At this time, the voltage to be applied to the voltage control pin is 1.5V minus the real-time frequency offset divided by 7, for example, if the real-time frequency offset is-0.7 ppm at a certain time, the control voltage should be 1.6V.

Specifically, the model of the single chip microcomputer 30 can be selected as STM32F415RGT6, and a DAC module is integrated in the single chip microcomputer, so that the control voltage is also generated by the MCU, and extra cost and power consumption are not increased. Since the reference voltage of the DAC module is +3.3V and the DAC module is 12 bits, the output voltage of the DAC is the value of the DAC data register divided by 4096 and multiplied by 3.3V, i.e. the output voltage is between 0 and 3.3V, which can meet the 0.5V to 2.5V regulation range required by the VCTCXO.

Preferably, the acquisition unit connected to the clock signal output pin of the crystal oscillator 10 is an analog-to-digital converter 40 (ADC), the output pin of the ADC 40 is connected to the SPI interface of the single chip microcomputer 30 through a serial peripheral interface, and the secure data input/output interface of the single chip microcomputer 30 is connected to the data storage card 50. Wherein: the single chip microcomputer 30 reads data of the ADC through the serial peripheral interface SPI and writes the data into the data memory card SD through the secure data input output interface SDIO after accumulating a certain amount of data; the single chip microcomputer 30 finely adjusts the real-time frequency of the crystal oscillator 10 by adjusting the output voltage of the DAC, and the clock signal output pin of the crystal oscillator 10 outputs the corrected clock signal to the analog-to-digital converter 40 (ADC).

As shown in fig. 2, in the present embodiment: the model of the GPS module 20 is RXM-GPS-FM, on one hand, the PPS output of the GPS module is connected to a PC12 pin of the MCU to be used as an interrupt wire, and one interrupt is generated every second during normal work; on the other hand, the system is connected to UART3 of the MCU through a UART (universal asynchronous receiver transmitter) interface, and the MCU analyzes information such as current UTC time and the like from the UART, so that synchronization of a plurality of seismographs is realized. The MCU is model STM32F415RGT6, which has integrated within it a DAC module, whose PA4 pin is configured such that the DAC output pin is connected to the voltage control pin of the VCTCXO. The ADS1282 is used by the main acquisition chip ADC, the main acquisition chip ADC is connected to an SPI1 interface of the MCU through a 3-line SPI, in addition, a data ready signal DRDY of the main acquisition chip ADC is connected to a PB1 pin of the MCU to be used as an interrupt line, and the ADC generates an interrupt once after data conversion and informs the MCU to fetch data. The MCU also needs to be connected to the micro SD card through an SDIO interface to store the acquisition data of the seismograph.

It should be noted that, in the present embodiment, the long-term acquisition requirement of the node seismograph is realized by using several main chips such as the GPS module 20, the crystal oscillator, the single chip microcomputer 30, and the like, and the conventional method that the frequency division coefficient is changed by using an FPGA chip to compensate the crystal oscillator drift is eliminated, so that the power consumption of the whole seismograph is reduced to one half. Meanwhile, compared with a node type seismograph without crystal oscillator frequency correction, the aging index can be greatly improved, the synchronization error can be obviously reduced in the long-time acquisition process, and the data acquisition precision and the precision of subsequent data processing section inversion are improved. Taking VCTCXO as an example of the crystal oscillator of the system, the aging index can be reduced to 0.2ppb from plus or minus 20ppb (parts per billion) per day by using the method.

The above description is only for the preferred embodiment of the present invention, and is not intended to limit the present invention, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention should be included within the protection scope of the present invention.

Claims

1. A clock generation apparatus for a nodal seismograph, comprising: the system comprises a crystal oscillator, a GPS module and a singlechip;

2. The clock generating device as claimed in claim 1, wherein the single-chip microcomputer is integrated with a digital-to-analog converter, an output pin of the single-chip microcomputer is configured as an output pin of the digital-to-analog converter, and the output pin of the digital-to-analog converter is connected with the voltage control pin of the crystal oscillator.

3. The clock generation device suitable for the node seismograph as claimed in claim 1 or 2, wherein the single chip microcomputer is integrated with a counter for counting the time interval between adjacent pulse-per-second signals generated by the GPS module.

4. The clock generation apparatus for a nodal seismograph of claim 3, wherein the counter comprises a first counter and a second counter, the first counter and the second counter being cascaded.

5. The clock generation apparatus of claim 1, wherein the general purpose input/output interface of the single-chip microcomputer is an interrupt pin.

6. The clock generation device suitable for the node seismograph as claimed in claim 1 or 2, wherein the acquisition unit is an analog-to-digital converter, and an output pin of the analog-to-digital converter is connected with the SPI interface of the single chip microcomputer through a serial peripheral interface.

7. The clock generation device suitable for the node seismograph as claimed in claim 1, wherein the secure data input and output interface of the single chip is connected with a data storage card.

8. The clock generation apparatus for a nodal seismograph of claim 1, wherein the crystal oscillator is a voltage controlled temperature compensated crystal oscillator.