CN210182360U

CN210182360U - Semiconductor packaging structure with linear metal bonding wire

Info

Publication number: CN210182360U
Application number: CN201921040876.3U
Authority: CN
Inventors: Hanlong Cai; 蔡汉龙; Zhengzhong Lin; 林正忠
Original assignee: SJ Semiconductor Jiangyin Corp
Current assignee: SJ Semiconductor Jiangyin Corp
Priority date: 2019-07-04
Filing date: 2019-07-04
Publication date: 2020-03-24
Anticipated expiration: 2029-07-04

Abstract

The utility model provides a semiconductor packaging structure with straight line shape bonding wire, semiconductor packaging structure include the chip, straight line shape bonding wire and encapsulated layer. The chip surface comprises a bonding pad; the linear metal welding line is contacted with the bonding pad to form a welding point, and comprises one or a combination of an upright linear metal welding line and an inclined linear metal welding line; the packaging layer covers the chip surface and the linear metal bonding wires, and the linear metal bonding wires are exposed out of the packaging layer. The utility model discloses form the semiconductor packaging structure who has sharp linear shape metallic bonding wire in the packaging layer, can satisfy the processing procedure demand, and can improve product quality.

Description

Semiconductor packaging structure with linear metal bonding wire

Technical Field

The utility model relates to a semiconductor packaging technology field especially relates to a semiconductor packaging structure with straight line shape bonding wire.

Background

As integrated circuits become more powerful and have higher performance and integration levels, packaging technology plays an increasingly important role in the production of integrated circuits. Lower cost, more reliable, faster, and higher density circuits are sought after goals for integrated circuit packaging. In the future, integrated circuit packages will increase the integration density of various electronic components by continually reducing the minimum feature size.

Wafer Level Package (WLP) technology has become an important packaging method for mobile/wireless network and other electronic devices with high requirements due to its advantages of miniaturization, low cost, high integration level, good performance, and high energy efficiency, and is one of the most promising packaging technologies currently. Among them, the WLP technology is based on the BGA technology and is an improved and enhanced CSP. The wafer is used as a processing object, a plurality of chips are packaged, aged and tested on the wafer at the same time, and finally the chips are cut into single chips which can be directly attached to a substrate or a printed circuit board, so that the packaging size is reduced to the size of the chips, and the production cost is greatly reduced.

In the existing semiconductor packaging process, it is generally required to design a bonding wire located in a package as a straight bonding wire standing upright or a straight bonding wire inclined, considering the requirement of a special function of the package. However, in the current industry, when forming a bonding wire, a second bonding pad (2nd Bond) is needed, i.e. a special bonding machine is used to half-cut the bonding wire by 2nd Bond, and then stretch and cut the bonding wire to form a desired wire shape. However, because the bonding wire is bent, a straight linear bonding wire and an inclined linear bonding wire which meet the requirements cannot be formed through stretching, and the problem of insufficient bonding of the bonding wire is easily caused in the stretching process; during packaging, only one connecting welding spot is arranged, so that the packaging material is easy to cause the deviation of a welding wire; a special wire bonding machine is needed, so that the selection of the wire bonding machine is limited; the process parameters are complex, and the process is difficult to control; the 2nd Bond may damage the chip, requiring special treatment of the surface of the chip, increasing the manufacturing cost.

Therefore, it is necessary to provide a semiconductor package structure with linear metal bonding wires to prepare a semiconductor package structure with linear metal bonding wires.

SUMMERY OF THE UTILITY MODEL

In view of the above-mentioned shortcomings of the prior art, it is an object of the present invention to provide a semiconductor package structure with linear metal bonding wires, which is used to solve the above-mentioned series of quality and cost problems caused by the formation of linear metal bonding wires in the prior art.

To achieve the above and other related objects, the present invention provides a semiconductor package structure having a linear shaped metal bonding wire, the semiconductor package structure including:

a chip, the chip surface comprising a pad;

the linear metal welding wire is contacted with the bonding pad to form a welding point, wherein the linear metal welding wire comprises one or a combination of an upright linear metal welding wire and an inclined linear metal welding wire;

and the packaging layer covers the surface of the chip and the linear metal bonding wires, and the linear metal bonding wires are exposed out of the packaging layer.

Optionally, an included angle between the inclined linear metal bonding wire and the chip surface ranges from 45 ° to 90 °, including 45 °.

Optionally, the linear metal bonding wire comprises one or a combination of a Cu wire, an Au wire, a Cu alloy wire, an Au alloy wire and a Cu/Au alloy wire.

Optionally, the encapsulation layer includes one of a polyimide encapsulation layer, a silicone encapsulation layer, and an epoxy encapsulation layer.

As described above, the present invention forms the semiconductor package structure with linear metal bonding wires in the package layer, thereby satisfying the process requirements and improving the product quality.

Drawings

Fig. 1 is a schematic process flow diagram of the present invention for fabricating a semiconductor package structure with linear metal bonding wires.

Fig. 2 is a schematic top view of a wafer according to the present invention.

Fig. 3 is a schematic structural view of an enlarged region a in fig. 2.

Fig. 4 is a schematic diagram of a structure for forming a metal bonding wire.

Fig. 5 is a schematic structural view of a cross section C-C' of the enlarged region B of fig. 4.

Fig. 6 is a schematic diagram of a structure for forming an encapsulation layer.

Fig. 7 is a schematic structural diagram after thinning the encapsulation layer.

Fig. 8 is a schematic structural diagram of a wafer after dicing.

Fig. 9 is a schematic structural diagram of another semiconductor package structure with linear metal bonding wires according to the present invention.

Description of the element reference numerals

100 wafer

101. 1011 chip

102 cutting line

111. 1111 first bonding pad

112 second bonding pad

200 metal welding wire

201 straight-line metal welding line

2011 vertical metal welding wire

2012 inclined linear metal welding wire

202 curved metal welding wire

301. 3011 first solder joint

302 second welding point

400 encapsulation layer

401. 4011 first package region

402 second package region

A. B enlarged region

Angle theta

Detailed Description

The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The present invention can also be implemented or applied through other different specific embodiments, and various details in the present specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

Please refer to fig. 1 to 9. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the invention in a schematic manner, and only the components related to the invention are shown in the drawings rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, quantity and proportion of the components in actual implementation may be changed at will, and the layout of the components may be more complicated.

As shown in fig. 1, the utility model provides a preparation method of semiconductor packaging structure with straight line shape metal bonding wire, form first pad on the chip surface, form the second pad on the cutting road surface, and will sharply appear the first encapsulation district that the metal bonding wire formed in the packaging layer, curvilinear figure metal bonding wire is formed in the second encapsulation district of packaging layer, and through the attenuate packaging layer, show straight line shape metal bonding wire, through to wafer cutting, get rid of curvilinear figure metal bonding wire when obtaining independent chip, thereby can be under the condition that does not increase technology steps, form the semiconductor packaging structure who has straight line shape metal bonding wire. The utility model discloses there is not special restriction to the bonding wire machine to can enlarge the selection of bonding wire machine, reduce the process control degree of difficulty, reduce manufacturing cost, and can reduce the damage to the chip, improve product quality.

Referring to fig. 2 to 8, schematic structural diagrams of steps of manufacturing a semiconductor package structure with linear metal bonding wires are shown.

Referring to fig. 2 and fig. 3, fig. 3 is a schematic structural diagram of an enlarged area a in fig. 2.

First, a wafer 100 is provided, where the wafer 100 includes a chip 101, a scribe line 102, a first bonding pad 111 on a surface of the chip 101, and a second bonding pad 112 on a surface of the scribe line 102.

Specifically, the wafer 100 may further include a support substrate (not shown) and a separation layer (not shown) located between the wafer 100 and the support substrate, so as to support the wafer 100 through the support substrate, and the wafer 100 is connected to the support substrate through the separation layer. The support substrate may include one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate, the separation layer may include a polymer layer having a reduced viscosity under heating or light irradiation, and the polymer layer may include a LTHC light-to-heat conversion layer. The glass substrate is low in cost, the separation layer is easy to form on the surface of the glass substrate, and the difficulty of a subsequent stripping process can be reduced, so that the support substrate is preferably the glass substrate, the separation layer is preferably coated on the surface of the support substrate by adopting a spin coating process, and then is cured and formed through an ultraviolet curing or thermocuring process, so that the LTHC light-heat conversion layer can be heated based on laser in the subsequent stripping process, and the support substrate is separated from the LTHC light-heat conversion layer. Of course, the wafer 100 may not include the supporting substrate and the separation layer, for example, when the wafer 100 is thicker, the wafer 100 may be directly subjected to a subsequent process on the surface of the wafer 100 without damaging the wafer 100, and then the wafer 100 may be thinned by a thinning process to reduce the package size, which may be specifically selected according to the needs, and is not limited herein. The specific sizes of the wafer 100, the chips 101 and the scribe lines 102 are not limited herein, and the sizes, the numbers and the distributions of the first pads 111 and the second pads 112 are not limited herein.

Referring to fig. 4 and 5, fig. 4 is a schematic view illustrating a structure of forming a metal bonding wire, and fig. 5 is a schematic view illustrating a cross-section C-C' of an enlarged region B in fig. 4.

The first bonding pad 111 and the second bonding pad 112 are connected by a metal bonding wire 200 by using a bonding wire process, wherein the metal bonding wire 200 comprises a linear metal bonding wire 201 and a curved metal bonding wire 202, the linear metal bonding wire 201 is in contact with the first bonding pad 111 to form a first bonding point 301, and the curved metal bonding wire 202 is in contact with the second bonding pad 112 to form a second bonding point 302.

Specifically, the bonding process may be a thermosonic bonding process, and the number and distribution of the first pads 111, the second pads 112 and the metal bonding wires 200 may be selected according to the requirement, which is not limited herein. The linear metal bonding wire 201 is connected with the first bonding pad 111 through the first welding point 301, and the curved metal bonding wire 202 is connected with the second bonding pad 112 through the second welding point 302, so that during the wire bonding process, a bonding machine which is relatively universal in the industry can be adopted by the bonding machine, a special bonding machine which is required to perform half-cutting and straightening on the metal bonding wire 201 is not required, the selection range of the bonding machine can be expanded, the process control difficulty is reduced, and the manufacturing cost is reduced. In addition, since the second solder joints 302 are located at the second solder pads 302 on the surface of the scribe line 102, the wire bonding process does not need to perform special processing on the surface of the chip 101, so that the cost can be further reduced, and when the second solder joints 302 are soldered, the damage to the chip 101 can be reduced, so that the product quality can be improved.

As a further example of this embodiment, the metal bonding wire 200 may include one or a combination of a Cu wire, an Au wire, a Cu alloy wire, an Au alloy wire, and a Cu/Au alloy wire, and it is preferable that the metal bonding wire 200 uses the Cu wire which is cheap to reduce the cost.

As shown in fig. 6, a package layer 400 is formed, wherein the package layer 400 covers the surface of the wafer 100 and the metal bonding wires 200, wherein the package layer 400 includes a first package region 401 and a second package region 402, the first package region 401 covers the surface of the chip 101 and the linear metal bonding wires 201, and the second package region 402 covers the first package region 401, the scribe lines 102 and the curved metal bonding wires 202.

As a further example of this embodiment, the encapsulation layer 400 may include one of a polyimide encapsulation layer, a silicone encapsulation layer, and an epoxy encapsulation layer; the method of forming the encapsulation layer 400 may include one of compression molding, transfer molding, liquid encapsulation molding, vacuum lamination, and spin coating.

Specifically, in the process of packaging with the packaging layer 400, since the linear metal bonding wire 201 of the metal bonding wire 200 is fixed to the first bonding pad 111 of the chip 101 by the first bonding pad 301, and the curved metal bonding wire 202 is fixed to the second bonding pad 112 of the scribe line 102 by the second bonding pad 302. Therefore, the bonding performance between the metal bonding wires 200 and the wafer 100 is good, so that the metal bonding wires 200 are less likely to cause wire deviation during the packaging process, and the linear metal bonding wires 201 can further maintain their linear morphology.

As shown in fig. 7, the package layer 400 is thinned to expose the linear metal bonding wires 201 in the first package region 401.

As a further example of this embodiment, the method of thinning the encapsulation layer 400 may include a chemical mechanical polishing method.

Specifically, while the package layer 400 is thinned, a portion of the curved metal bonding wire 202 in the second package region 402 may be removed, such that the top surface of the linear metal bonding wire 201 is exposed to the top surface of the first package region 401, so as to facilitate subsequent electrical connection. In this embodiment, the method for thinning the encapsulation layer 400 is preferably a chemical mechanical polishing method that provides a relatively flat surface, but is not limited thereto, and other thinning methods such as a mechanical polishing method may also be used.

As shown in fig. 8, the wafer 100 is diced along the dicing streets 102 to obtain individual chips 101.

Specifically, while the wafer 100 is diced to obtain the individual chips 101, a portion of the curved metal bonding wires 202 in the second package region 402 may be removed, so as to form the semiconductor package structure having the linear metal bonding wires 201 without adding process steps through the steps of thinning the package layer 400 and dicing the wafer 100.

As a further embodiment of this embodiment, the method for dicing the wafer 100 may include one or a combination of a laser dicing method and a blade dicing method.

Specifically, when the blade cutting method is adopted, the blade can be selected from a soft blade or a hard blade, and can be specifically selected according to the requirement. The cutting method may adopt a method of performing laser pre-cutting and then performing blade cutting, so as to further reduce damage to the chip 101, and may be specifically selected as required.

As a further embodiment of this embodiment, an included angle between the linear metal bonding wire 201 and the surface of the chip 101 may be in a range from 45 ° to 90 °.

Specifically, as shown in fig. 9, a schematic structural diagram of another semiconductor package structure with a linear metal bonding wire is illustrated, where the linear metal bonding wire includes an upright linear metal bonding wire 2011 and an inclined linear metal bonding wire 2012, an included angle θ between the upright linear metal bonding wire 2011 and the surface of the chip 1011 is 90 °, an included angle θ between the inclined linear metal bonding wire 2012 and the surface of the chip 1011 is preferably in a range of 45 ° to 90 °, including 45 °, and the included angle θ may also be selected to be equal to 60 ° or 75 °, so as to facilitate setting electrical leading-out of the linear metal bonding wire according to needs.

The present invention also provides a semiconductor package structure with linear metal bonding wires, and the manufacturing method of the semiconductor package structure with linear metal bonding wires can refer to the above manufacturing process, but is not limited thereto.

As shown in fig. 9, the semiconductor package structure includes a chip 1011, linear metal bonding wires, and a package layer 4011. Wherein the chip 1011 surface includes pads 1111; the linear metal bonding wire is in contact with the bonding pad 1111 to form a bonding point 3011, wherein the linear metal bonding wire includes one or a combination of an upright linear metal bonding wire 2011 and an inclined linear metal bonding wire 2012; the packaging layer 4011 covers the surface of the chip 1011 and the linear metal bonding wires, and the linear metal bonding wires are exposed from the packaging layer 4011. The utility model discloses form in the packaging layer and have the semiconductor packaging structure of straight line shape metal bonding wire can satisfy the processing procedure demand, and can improve product quality.

As a further embodiment of the embodiment, an included angle θ between the tilted linear metal bonding wire 2012 and the surface of the chip 1011 is between 45 ° and 90 °, including 45 °.

Specifically, the linear metal bonding wire may only include the upright metal bonding wire 2011 or the inclined metal bonding wire 2012 or include a combination of the upright metal bonding wire 2011 and the inclined metal bonding wire 2012. The included angle θ between the vertical linear metal bonding wire 2011 and the surface of the chip 1011 is 90 °, the included angle θ between the inclined linear metal bonding wire 2012 and the surface of the chip 1011 is preferably in a range of 45 ° to 90 °, including 45 °, and the included angle θ can also be selected to be equal to 60 ° or 75 °, so that the electrical leading-out of the linear metal bonding wire can be conveniently set according to requirements.

As a further example of this embodiment, the linear metal bonding wire may include one or a combination of a Cu wire, an Au wire, a Cu alloy wire, an Au alloy wire, and a Cu/Au alloy wire.

As a further embodiment of this embodiment, the encapsulation layer 4011 may include one of a polyimide encapsulation layer, a silicone encapsulation layer, and an epoxy encapsulation layer.

To sum up, the utility model discloses a semiconductor package structure with straight line shape bonding wire forms first pad on the chip surface, form the second pad on the cutting street surface, and will sharply appear the bonding wire and form in the first encapsulation district of packaging layer, curvilinear figure bonding wire is formed in the second encapsulation district of packaging layer, and through the attenuate packaging layer, show and sharply appear the bonding wire, through wafer cutting, get rid of curvilinear figure bonding wire in the time of obtaining independent chip, thereby can be under the condition that does not increase the process step, form and have the semiconductor package structure who sharply appears the bonding wire (including upright and slope). The utility model discloses there is not special restriction to the bonding wire machine to can enlarge the selection of bonding wire machine, reduce the process control degree of difficulty, reduce manufacturing cost, and can reduce the damage to the chip, improve product quality. Therefore, the utility model effectively overcomes various defects in the prior art and has high industrial utilization value.

The above embodiments are merely illustrative of the principles and effects of the present invention, and are not to be construed as limiting the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. A semiconductor package structure with linear metal bonding wires is characterized by comprising:

a chip, the chip surface comprising a pad;

2. The semiconductor package structure with linear metal bonding wires according to claim 1, wherein: the included angle range of the inclined linear metal welding line and the surface of the chip is between 45 degrees and 90 degrees, including 45 degrees.

3. The semiconductor package structure with linear metal bonding wires according to claim 1, wherein: the linear metal bonding wire comprises one or a combination of a Cu wire, an Au wire, a Cu alloy wire, an Au alloy wire and a Cu/Au alloy wire.

4. The semiconductor package structure with linear metal bonding wires according to claim 1, wherein: the packaging layer comprises one of a polyimide packaging layer, a silica gel packaging layer and an epoxy resin packaging layer.