CN202917475U - Chip packaging structure - Google Patents
Chip packaging structure Download PDFInfo
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- CN202917475U CN202917475U CN2012205866562U CN201220586656U CN202917475U CN 202917475 U CN202917475 U CN 202917475U CN 2012205866562 U CN2012205866562 U CN 2012205866562U CN 201220586656 U CN201220586656 U CN 201220586656U CN 202917475 U CN202917475 U CN 202917475U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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Abstract
Provided is a chip packaging structure, comprising a semiconductor substrate; a metal pad located in the semiconductor substrate; an insulating layer located on the semiconductor substrate and possessing an opening for exposing the metal pad; an under ball metal electrode located on the metal pad and a solder ball located on the surface of the under ball metal electrode. The solder ball possesses a first apron structure which covers the metal pad around the bottom of the under ball metal electrode. According to the utility model, the adhesive force between the metal pad and the solder ball is increased and reliability of chip packaging is raised.
Description
Technical field
The utility model relates to technical field of semiconductors, relates in particular to a kind of chip-packaging structure.
Background technology
On the conventional art, IC chip and being connected of external circuit are that the mode by metal lead wire bonding (Wire Bonding) realizes.Along with the expansion with the integrated circuit scale dwindled of IC chip features size, Wire Bonding Technology is no longer applicable.Crystal wafer chip dimension encapsulation (Wafer Level Chip Scale Packaging, WLCSP) technology is that the full wafer wafer is carried out cutting the technology that obtains the single finished product chip after the packaging and testing again, and chip size and nude film after the encapsulation are in full accord.The crystal wafer chip dimension encapsulation technology has thoroughly been overturned the pattern of conventional package such as ceramic leadless chip carrier (Ceramic Leadless Chip Carrier), organic leadless chip carrier (Organic Leadless Chip Carrier), has complied with that market is day by day light, little, short to microelectronic product, thinning and low priceization requirement.It is highly microminiaturized that chip size after crystal wafer chip dimension encapsulation technology encapsulation has reached, chip cost along with chip size reduce significantly reduce with the increase of wafer size.The crystal wafer chip dimension encapsulation technology be IC can be designed, wafer manufacturing, packaging and testing, the technology that integrates, be the focus of current encapsulation field and the trend of future development.
Prior art discloses a kind of crystal wafer chip dimension encapsulation technology, please refer to Fig. 1, and Fig. 1 is the generalized section of prior art wafer level chip scale package structure, comprising: Semiconductor substrate 101; Be positioned at the metal pad 103 of described Semiconductor substrate 101 inside; Be positioned at the insulating barrier 102 on described Semiconductor substrate 101 surfaces, described insulating barrier 102 has the opening that exposes described metal pad 103; Be positioned at metal electrode 104 under the ball of the described metal pad 103 in described opening and cover part; Be positioned at the soldered ball on the metal electrode 104 105 under the described ball, the upper surface of metal electrode 104 under described soldered ball 105 ball covering on soils.
In the prior art under soldered ball 105 and the ball contact area of metal electrode 104 little, the poor adhesive force under soldered ball 105 and the ball between the metal electrode 104.In addition, soldered ball 105 is located immediately under the ball on the metal electrode 104 in the prior art, the material of metal electrode 104 is generally copper under the ball, the material of soldered ball 105 is generally tin, tin atom can diffuse in the copper electrode and go, and copper atom also can diffuse in the tin ball simultaneously, forms interface alloy altogether compound (IMC:Intermetallic Compound) and cavity, interface alloy altogether compound enbrittles, and will affect mechanical strength and the life-span of solder joint.
The chip-packaging structure poor reliability of prior art.
The method for filling of other relevant chips can also be the Chinese invention patent application of CN101211791 with reference to publication number, and it discloses a kind of wafer-grade chip packaging process and chip-packaging structure.
The utility model content
The problem that the utility model solves be under prior art soldered ball and the ball between the metal electrode contact area little, poor adhesive force; Have interface alloy altogether compound and cavity under soldered ball and the ball between the metal electrode, poor reliability
For addressing the above problem, the utility model provides a kind of chip-packaging structure, comprising: Semiconductor substrate; Be positioned at the metal pad of described Semiconductor substrate; Be positioned at the insulating barrier on the described Semiconductor substrate, described insulating barrier has the opening that exposes described metal pad; Be positioned at metal electrode under the ball on the described metal pad; Be positioned at the soldered ball of surface of metal electrode under the described ball, described soldered ball has the first skirt structure, and described the first skirt structure covers the metal pad of metal electrode bottom periphery under the described ball.
Optionally, described metal pad is distributed pad again.
Optionally, metal electrode has electrode body and electrode afterbody under the described ball, and described electrode body section is positioned under the described ball metal electrode bottom and joins with described metal pad, and described electrode afterbody is positioned at metal electrode top under the described ball.
Optionally, described electrode tail height is 0.005 ~ 1.5 times of described electrode body height.
Optionally, surface of metal electrode has cover layer under the described ball, described cover layer has the second skirt structure, and described the second skirt structure covers the metal pad of metal electrode bottom periphery under the described ball, and described the second skirt structure surface is covered by described the first skirt structure.
Optionally, described cover layer is the stacked structure of barrier layer and soakage layer, and described barrier layer is positioned at surface of metal electrode under the described ball, and described soakage layer is positioned at described barrier layer surface, described barrier layer has the 3rd apron structure, and described soakage layer has the skirt structure all around.
Optionally, the thickness of described barrier layer is 0.05 μ m to 5 μ m.
Optionally, the thickness of described soakage layer is 0.05 μ m to 10 μ m.
Compared with prior art, the utlity model has following advantage:
Described soldered ball has the first skirt structure, and described the first skirt structure covers the metal pad of metal electrode bottom periphery under the described ball.Described the first skirt structure has increased the contact area of soldered ball and metal pad, has strengthened the adhesive force of soldered ball and metal pad, comes off from the metal pad surface so that soldered ball is more difficult when being subjected to External Force Acting.
Further, described cover layer is the stacked structure of barrier layer and soakage layer, and described barrier layer is positioned at surface of metal electrode under the described ball, and described soakage layer is positioned at described barrier layer surface.In the prior art, soldered ball is located immediately under the ball on the metal electrode, under the ball between metal electrode and the soldered ball diffusion by atom can form interface alloy altogether compound and cavity, interface alloy altogether compound enbrittles, and will affect mechanical strength and the life-span of solder joint.In the utility model, surface of metal electrode forms first barrier layer under ball, the material of described barrier layer is nickel, compare barrier layer and soldered ball formation interface alloy compound is slow a lot of altogether with metal electrode under the ball, can be used as the barrier layer between the metal electrode and soldered ball under the ball, prevent from forming interface alloy altogether compound and cavity.And because the easy oxidation of barrier layer, further form the oxidation that soakage layer prevents barrier layer on the barrier layer surface, in addition, the material of the soldered ball of soakage layer and follow-up formation infiltrates, adhesive force is better, the material of described soakage layer is a kind of in tin, the gold, silver, and perhaps the material of described soakage layer is the alloy of stanniferous, gold or silver.Compared with prior art, surface of metal electrode forms cover layer and has improved altogether compound problem of interface alloy under ball, has promoted the reliability of chip package.
Further, metal electrode has electrode body and electrode afterbody under the described ball, and described electrode body section is positioned under the described ball metal electrode bottom and joins with described metal pad, and described electrode afterbody is positioned at metal electrode top under the described ball.Described electrode afterbody embeds in the described soldered ball, increased the contact area of metal electrode and soldered ball under the ball, so the Adhesion enhancement of metal electrode and soldered ball under the ball so that soldered ball is when being subjected to External Force Acting, more difficult under the ball surface of metal electrode come off.Described cover layer has the second skirt structure, and tectal the second skirt structure has increased the contact area of cover layer and metal pad, has strengthened the adhesive force of metal electrode and metal pad under soldered ball, cover layer, the ball.
Description of drawings
Fig. 1 is prior art chip-packaging structure schematic diagram;
Fig. 2 is the utility model the first embodiment chip-packaging structure schematic diagram;
Fig. 3 is the utility model the second embodiment chip-packaging structure schematic diagram;
Fig. 4 is the utility model the 3rd embodiment chip-packaging structure schematic diagram;
Fig. 5 is the utility model the 4th embodiment chip-packaging structure schematic diagram.
Embodiment
By background technology as can be known, please continue with reference to figure 1, in the prior art, soldered ball 105 is positioned under the ball on the metal electrode 104, and the upper surface of metal electrode 104 contacts under soldered ball 105 and the ball, and contact area is little, the poor adhesive force under soldered ball 105 and the ball between the metal electrode 104.In addition, the material of metal electrode 104 is generally copper under the ball, the material of soldered ball 105 is generally tin, when surface of metal electrode forms the tin ball under copper ball, tin atom can diffuse under the copper ball and go in the metal electrode, and copper atom also can diffuse in the tin ball simultaneously, forms interface alloy altogether compound (IMC:Intermetallic Compound) and cavity, interface alloy altogether compound enbrittles, and will affect mechanical strength and the life-span of solder joint.
Inventor of the present utility model proposes a kind of new chip-packaging structure through creative work, comprising: Semiconductor substrate; Be positioned at the metal pad of described Semiconductor substrate; Be positioned at the insulating barrier on the described Semiconductor substrate, described insulating barrier has the opening that exposes described metal pad; Be positioned at metal electrode under the ball on the described metal pad, the following table area of metal electrode is less than the metal pad area under the described ball; Be positioned at the soldered ball of surface of metal electrode under the described ball, described soldered ball has the first skirt structure, and described the first skirt structure covers the metal pad of metal electrode bottom periphery under the described ball.
Describe four specific embodiments that the utility model provides below in conjunction with Figure of description, above-mentioned purpose and advantage of the present utility model will be clearer.Need to prove, the purpose that these accompanying drawings are provided is to help to understand embodiment of the present utility model, and should not be construed as improperly restriction of the present utility model.For the purpose of clearer, size shown in the figure and not drawn on scale may be made amplification, be dwindled or other changes.A lot of details have been set forth in order to fully understand the utility model in the following description.But the utility model can be implemented much to be different from other modes described here, those skilled in the art can be in the situation that do similar popularization without prejudice to the utility model intension, so the utility model is not subjected to the restriction of following public specific embodiment.
The first embodiment
Please refer to Fig. 2, Fig. 2 is the chip-packaging structure schematic diagram of the utility model the first embodiment, comprising: Semiconductor substrate 201; Be positioned at the metal pad 203 of described Semiconductor substrate 201; Be positioned at the insulating barrier 202 on the described Semiconductor substrate 201, described insulating barrier 202 has the opening that exposes described metal pad 203; Be positioned at metal electrode 204 under the ball on the described metal pad 203; Be positioned at the soldered ball 207 on metal electrode 204 surfaces under the described ball, described soldered ball 207 has the first skirt structure 207a, and described the first skirt structure 207a covers the metal pad 203 of metal electrode 204 bottom peripheries under the described ball.
Particularly, described Semiconductor substrate 201 can be monocrystalline silicon, SOI(silicon-on-insulator), SiGe or III-V compounds of group wafer, described Semiconductor substrate 201 comprises one deck or the some layers of dielectric layer that are positioned at its inside and surface, and described Semiconductor substrate 201 can also comprise making semiconductor device, metal interconnected and other semiconductor structures thereon.
Described metal pad 203 is positioned at described Semiconductor substrate 201, the top layer interconnecting metal electrode that described metal pad 203 is described Semiconductor substrate 201, the material of described metal pad is gold, copper, aluminium or silver, and described metal pad 203 is used for connecting chip internal circuit and outer enclosure parts in encapsulating structure.
Described insulating barrier 202 is positioned on the described Semiconductor substrate 201, and described insulating barrier 202 has the opening that exposes described metal pad 203.Described insulating barrier 202 comprises passivation layer and polymeric layer (not shown), described passivation layer exposes the opening of described metal pad 203 for the protection of metal pad 203, electric isolation and formation, the material of described passivation layer can be silica, silicon nitride or low-K material; Described polymeric layer is positioned on the described passivation layer, described polymeric layer has the opening that exposes described metal pad 203, and the material of described polymer can be polyimides (Polyimide), epoxy resin (Epoxy) or benzocyclobutane olefine resin (Benzocyclobutene).
In one embodiment, described Semiconductor substrate 201 is monocrystalline silicon, and described Semiconductor substrate 201 has also comprised semiconductor device, metal interconnection and other semiconductor structures of making thereon.Described insulating barrier 202 comprises that material is that passivation layer and the material of silica is the polymeric layer of polyimides, described insulating barrier 202 has the opening of exposing metal pad 203, the interconnected metal electrode of top layer that described metal pad 203 is described Semiconductor substrate 201, the material of described metal pad 203 is copper.
Particularly, be positioned at metal electrode 204 under the ball on the described metal pad 203, metal electrode 204 is used for connection metal pad 203 and soldered ball under the described ball.The material of metal electrode 204 is a kind of in gold, copper, the silver under the described ball, and perhaps the material of metal electrode 204 is the alloy that contains gold, copper or silver under the described ball.
In one embodiment, the technique that forms metal electrode 204 under the described ball is specially: form photoresist layer on described Semiconductor substrate 201 surfaces, described photoresist layer has the opening of the described metal pad 203 of expose portion, use the technique of plating, physical vapour deposition (PVD) or evaporation vapour deposition to fill metal material to described opening, remove photoresist layer, described metal material forms metal electrode 204 under the ball.
In another embodiment, the technique that forms metal electrode 204 under the described ball is Bonding, concrete steps are: metal lead wire arrives metal pad 203 tops by bonding head, utilizing oxyhydrogen flame or electrical discharge system to produce electric spark goes between with the deposite metal, under capillary effect, motlten metal solidifies and forms spherical (bulb diameter generally is 1.5 times to 4 times of metal lead wire diameter), fall bonding head, at suitable pressure, temperature, in kinetic energy and time Metal Ball is pressed on the metal pad 203, in this process, exert pressure to Metal Ball by bonding head, promote simultaneously lead-in wire metal and metal pad 203 that phase counterdiffusion between plastic deformation and the atom occurs, form metal electrode 204 under the ball, utilize the bonding wire clamp to cut off metal lead wire.
Particularly, be positioned at the soldered ball 207 on metal electrode 204 surfaces under the described ball, described soldered ball 207 has the first skirt structure 207a, and described the first skirt structure 207a covers the metal pad 203 of metal electrode 204 bottom peripheries under the described ball.Described the first skirt structure 207a has increased the contact area of soldered ball 207 and metal pad 203, has strengthened the adhesive force of soldered ball 207 and metal pad 203, comes off from the metal pad surface so that soldered ball 207 is more difficult when being subjected to External Force Acting.
Described soldered ball 207 can form by typography, and the material of described soldered ball 207 is tin or ashbury metal.The concrete technology that forms soldered ball 207 is: with scolder by screen printing on metal electrode under the ball 204, then carry out high temperature reflux, under surface tension effects, form soldered ball 207 so that described scolder changes.Because solder material infiltrates metal electrode material and metal pad material under the ball, metal electrode 204 and metal pad 203 under soldered ball 207 ball covering on soils that form, be that soldered ball 207 has the first skirt structure 207a, described the first skirt structure 207a covers the metal pad 203 of metal electrode 204 bottom peripheries under the described ball.
The second embodiment
Please refer to Fig. 3, Fig. 3 is the chip-packaging structure schematic diagram of the utility model the second embodiment, comprising:
The present embodiment is compared with the first embodiment, difference is: metal electrode 304 has electrode body 304a and electrode afterbody 304b under the described ball, described electrode body 304a is positioned under the described ball metal electrode 304 bottoms and joins with described metal pad 303, and described electrode afterbody 304b is positioned at metal electrode 304 tops under the described ball.Wherein, described electrode body 304a connection metal pad 303 and soldered ball also support described electrode afterbody 304b, described electrode afterbody 304b embeds in the soldered ball 307, increased the contact area of metal electrode 304 and soldered ball under the ball, therefore the Adhesion enhancement of metal electrode 304 and soldered ball under the ball, so that soldered ball 307 is when being subjected to External Force Acting, more difficult under the ball metal electrode 304 surfaces come off.
Need to prove, metal electrode 304 can form by the technique of Bonding (Wire Bonding) under the described ball, further specifies its feature below in conjunction with the formation method of metal electrode 304 under the ball described in the specific embodiment.The technique of using wire bonding method to form metal electrode 304 under the described ball is specially: metal lead wire arrives metal pad 303 tops by bonding head, utilizing oxyhydrogen flame or electrical discharge system to produce electric spark goes between with the deposite metal, under capillary effect, motlten metal solidifies and forms spherical (bulb diameter generally is 1.5 times to 4 times of metal lead wire diameter), fall bonding head, at suitable pressure, temperature, in kinetic energy and time Metal Ball is pressed on the metal pad 303, in this process, exert pressure to Metal Ball by bonding head, promote simultaneously lead-in wire metal and metal pad 303 that phase counterdiffusion between plastic deformation and the atom occurs, form electrode body 304a, then, bonding head lifts, the metal lead wire starting the arc is to certain height (electrode afterbody 304b height to be formed), utilize the bonding wire clamp to cut off metal lead wire, the upper metal lead wire of electrode body 304a is electrode afterbody 304b, forms metal electrode 304 under the ball.Need to prove, Bonding is usually used in the technique that connects between semiconductor packaged inner chip and external terminal and the chip, and inventor of the present utility model is by improving lead key closing process, be applied in the formation technique of metal electrode 304 under the ball, the metal lead wire starting the arc forms electrode afterbody 304b after can adopting bonding head to lift when forming electrode body 304a, technique is simple, forms efficient high.
The material of metal electrode 304 is a kind of in gold, copper, the silver under the described ball, and perhaps the material of metal electrode 304 is the alloy that contains gold, copper or silver under the described ball.The height of described electrode afterbody 304b is 0.005 ~ 1.5 times of described electrode body 304a height, when the height of electrode afterbody 304b is lower than 0.005 times of electrode body 304a height, electrode afterbody 304b embeds the limited length of the soldered ball of follow-up formation, and is limited to the Adhesion enhancement of metal electrode under the ball 304 and soldered ball; And when the height of electrode afterbody 304b is higher than 1.5 times of height of electrode body 304a, because electrode afterbody 304b forms by the starting the arc behind the Bonding, electrode afterbody 304b is thinner with electrode body 304a phase diameter group, and the metal quality is softer, easy bending and affect the shape of soldered ball in the manufacture process, rate of finished products reduces, and is unfavorable for down chip package.
In one embodiment, the material of metal electrode 304 is copper under the described ball, and the height of described electrode afterbody 304b is identical with the height of described electrode body 304a.
The material of Semiconductor substrate described in the present embodiment 301, described insulating barrier 302, described metal pad 303, described soldered ball 307 and structure and the first embodiment are similar, introduce in detail and please refer to the first embodiment, do not repeat them here.
The 3rd embodiment
Please refer to Fig. 4, Fig. 4 is the chip-packaging structure schematic diagram of the utility model the 3rd embodiment, comprising: Semiconductor substrate 401; Be positioned at the metal pad 403 of described Semiconductor substrate 401; Be positioned at the insulating barrier 402 on the described Semiconductor substrate 401, described insulating barrier 402 has the opening that exposes described metal pad 403; Be positioned at metal electrode 404 under the ball on the described metal pad 403, metal electrode 404 has electrode body and electrode afterbody under the described ball, described electrode body section is positioned under the described ball metal electrode 404 bottoms and joins with described metal pad 403, and described electrode afterbody is positioned at metal electrode 404 tops under the described ball; Be positioned at the cover layer on metal electrode 404 surfaces under the described ball, described cover layer has the second skirt structure, and described the second skirt structure covers the metal pad 403 of metal electrode 404 bottom peripheries under the described ball; Be positioned at the soldered ball 407 of described cover surface, described soldered ball 407 has the first skirt structure 407a, and described the first skirt structure 407a covers described the second skirt structure.
The present embodiment is compared with the second embodiment, difference is: metal electrode 404 surfaces form cover layer under described ball, described cover layer has the second skirt structure, and described the second skirt structure covers the metal pad 403 of metal electrode 404 bottom peripheries under the described ball.Described cover layer is the stacked structure of barrier layer 405 and soakage layer 406, and described barrier layer 405 is positioned at metal electrode 404 surfaces under the described ball, and described soakage layer 406 is positioned at described barrier layer 405 surfaces.Described barrier layer 405 has the 3rd apron structure 405a, and described soakage layer 406 has the skirt structure 406a all around.Described the second skirt structure is all around stacked structure of skirt structure 406a of the 3rd apron structure 405a and.
Described barrier layer 405 has the 3rd apron structure 405a, described the 3rd apron structure 405a covering metal pad 403 surfaces, increased the contact area of barrier layer 405 and metal pad 403, strengthened the adhesive force of barrier layer 405 and metal pad 403, in addition, because the coating function of metal electrode 404 under 405 pairs of balls of barrier layer, the adhesive force of metal electrode 404 and metal pad 403 has also obtained enhancing under the ball, so that metal electrode 404 more difficultly comes off from metal pad 403 surfaces when being subjected to External Force Acting under the ball.
The material of described barrier layer 405 is nickel, compare barrier layer 405 compound is slow a lot of altogether with soldered ball formation interface alloy with metal electrode under the ball 404, can be used as the barrier layer between the metal electrode 404 and soldered ball under the ball, prevent from forming interface alloy altogether compound and cavity.The interface alloy is compound and empty mechanical strength and the life-span that can affect solder joint altogether, can effectively improve altogether compound problem of interface alloy so form barrier layer 405, has promoted the reliability of chip package.The thickness of described barrier layer 405 is 0.05 μ m to 5 μ m, and the thickness of described barrier layer 405 is relevant with the technique of chip package process, and when the technological temperature of chip package process was lower, the thickness of described barrier layer 405 can reduce.In one embodiment, described barrier layer 405 is nickel dam, and the thickness of described nickel dam is 0.5 μ m to 3 μ m.
Described barrier layer 405 is nickel dam, and the easy oxidation of nickel dam causes interfacial resistivity to increase, so further have soakage layer 406 to prevent the oxidation of nickel dam on the nickel dam surface, in addition, soakage layer 406 infiltrates with the material of the soldered ball of follow-up formation, and adhesive force is better.The material of described soakage layer 406 is a kind of in tin, the gold, silver, and perhaps the material of described soakage layer 406 is the alloy of stanniferous, gold or silver.Described soakage layer 406 has the skirt structure 406a all around, described all around skirt structure 406a play the effect that increases soakage layer 406 and barrier layer 405 contacts area, and jointly play the effect that strengthens with metal pad 403 adhesive force with the 3rd apron structure 405a.Described all around skirt structure 406a and the 3rd apron structure 405a are common consists of the second skirt structure.The thickness of described soakage layer 406 is 0.05 μ m to 10 μ m, and the thickness of described soakage layer 406 is also relevant with the technique of chip package.In one embodiment, described soakage layer 406 is the tin layer, and the tin layer is not easy oxidized in air, and infiltrates with the soldered ball material of follow-up formation, and adhesive force is better, and the thickness of described tin layer is 0.1 μ m to 5 μ m.
The 4th embodiment
Please refer to Fig. 5, Fig. 5 is the chip-packaging structure schematic diagram of the utility model the 4th embodiment, comprising: Semiconductor substrate 501; Be positioned at the metal electrode 508 of described Semiconductor substrate 501; Be positioned at the first insulating barrier 509 on the described Semiconductor substrate 501, the described metal electrode 508 in described the first insulating barrier 509 cover parts, described the first insulating barrier 509 have the first opening that exposes described metal electrode 508; Be positioned at the transition metal layer 510 on described the first insulating barrier 509, described transition metal layer 510 covers sidewall and the basal surface of described the first opening, and described transition metal layer 510 forms the second opening along described the first open surfaces; Be positioned at the metal pad 503 on the transition metal layer 510, described metal pad 503 is filled full described the second opening; Be positioned at the second insulating barrier 502 on the described metal pad 503, described the second insulating barrier has the 3rd opening that exposes described metal pad 503; Be positioned at metal electrode 504 under the ball on the described metal pad 503, metal electrode 504 has electrode body and electrode afterbody under the described ball, described electrode body section is positioned under the described ball metal electrode 504 bottoms and joins with described metal pad 503, and described electrode afterbody is positioned at metal electrode 504 tops under the described ball; Be positioned at the cover layer on metal electrode 504 surfaces under the described ball, described cover layer has the second skirt structure, and described the second skirt structure covers the metal pad 503 of metal electrode 504 bottom peripheries under the described ball; Be positioned at the soldered ball 507 of described cover surface, described soldered ball 507 has the first skirt structure 507a, and described the first skirt structure 507a covers described the second skirt structure.
The present embodiment is compared with the 3rd embodiment, and difference is: the described metal pad 503 of the present embodiment is distributed pad (RDL) again.Described more distributed pad is by increasing the first insulating barrier 509, transition metal layer 510 and the second insulating barrier 502 forms at chip surface, it can again be arranged the position of the metal electrode 508 in the Semiconductor substrate 501 according to the design rule of packaging technology and be the position of distributed pad again.Distributed pad can dwindle the chip package size greatly again, reaches the demand of high-density packages, and has promoted speed and the stability of transfer of data.The formation method of described more distributed pad is well known to those skilled in the art, and does not repeat them here.
The material of metal electrode 504, described barrier layer 505, described soakage layer 506, described soldered ball 507 and structure and the 3rd embodiment are similar under Semiconductor substrate described in the present embodiment 501, the described ball, introduce in detail and please refer to the 3rd embodiment, do not repeat them here.
In sum, compared with prior art, the utlity model has following advantage: described soldered ball has the first skirt structure, and described the first skirt structure covers the metal pad of metal electrode bottom periphery under the described ball.Described the first skirt structure has increased the contact area of soldered ball and metal pad, has strengthened the adhesive force of soldered ball and metal pad, comes off from the metal pad surface so that soldered ball is more difficult when being subjected to External Force Acting.
Metal electrode has electrode body and electrode afterbody under ball described in second, third and the 4th embodiment, described electrode body section is positioned under the described ball metal electrode bottom and joins with described metal pad, and described electrode afterbody is positioned at metal electrode top under the described ball.Described electrode afterbody embeds in the described soldered ball, increased the contact area of metal electrode and soldered ball under the ball, so the Adhesion enhancement of metal electrode and soldered ball under the ball so that soldered ball is when being subjected to External Force Acting, more difficult under the ball surface of metal electrode come off.
Be the stacked structure of barrier layer and soakage layer at cover layer described in the 3rd, the 4th embodiment, described barrier layer is positioned at surface of metal electrode under the described ball, and described soakage layer is positioned at described barrier layer surface.In the prior art, soldered ball is located immediately under the ball on the metal electrode, under the ball between metal electrode and the soldered ball diffusion by atom can form interface alloy altogether compound and cavity, interface alloy altogether compound enbrittles, and will affect mechanical strength and the life-span of solder joint.In the utility model, surface of metal electrode forms first barrier layer under ball, the material of described barrier layer is nickel, compare barrier layer and soldered ball formation interface alloy compound is slow a lot of altogether with metal electrode under the ball, can be used as the barrier layer between the metal electrode and soldered ball under the ball, prevent from forming interface alloy altogether compound and cavity.And because the easy oxidation of barrier layer, further form the oxidation that soakage layer prevents barrier layer on the barrier layer surface, in addition, the material of the soldered ball of soakage layer and follow-up formation infiltrates, adhesive force is better, the material of described soakage layer is a kind of in tin, the gold, silver, and perhaps the material of described soakage layer is the alloy of stanniferous, gold or silver.Compared with prior art, surface of metal electrode forms cover layer and has improved altogether compound problem of interface alloy under ball, has promoted the reliability of chip package.In addition, described cover layer has the second skirt structure, and tectal the second skirt structure has increased the contact area of cover layer and metal pad, has strengthened the adhesive force of metal electrode and metal pad under soldered ball, cover layer, the ball.
Although the utility model with preferred embodiment openly as above; but it is not to limit the utility model; any those skilled in the art are not within breaking away from spirit and scope of the present utility model; can utilize method and the technology of above-mentioned announcement that technical solutions of the utility model are made possible change and modification; therefore; every content that does not break away from technical solutions of the utility model; to any simple modification, equivalent variations and modification that above embodiment does, all belong to the protection range of technical solutions of the utility model according to technical spirit of the present utility model.
Claims (8)
1. a chip-packaging structure is characterized in that, comprising:
Semiconductor substrate;
Be positioned at the metal pad of described Semiconductor substrate;
Be positioned at the insulating barrier on the described Semiconductor substrate, described insulating barrier has the opening that exposes described metal pad;
Be positioned at metal electrode under the ball on the described metal pad;
Be positioned at the soldered ball of surface of metal electrode under the described ball, described soldered ball has the first skirt structure, and described the first skirt structure covers the metal pad of metal electrode bottom periphery under the described ball.
2. chip-packaging structure as claimed in claim 1 is characterized in that, described metal pad is distributed pad again.
3. chip-packaging structure as claimed in claim 1, it is characterized in that, metal electrode has electrode body and electrode afterbody under the described ball, and described electrode body section is positioned under the described ball metal electrode bottom and joins with described metal pad, and described electrode afterbody is positioned at metal electrode top under the described ball.
4. chip-packaging structure as claimed in claim 3 is characterized in that, described electrode tail height is 0.005 ~ 1.5 times of described electrode body height.
5. chip-packaging structure as claimed in claim 1, it is characterized in that, surface of metal electrode has cover layer under the described ball, described cover layer has the second skirt structure, described the second skirt structure covers the metal pad of metal electrode bottom periphery under the described ball, and described the second skirt structure surface is covered by described the first skirt structure.
6. chip-packaging structure as claimed in claim 5, it is characterized in that, described cover layer is the stacked structure of barrier layer and soakage layer, described barrier layer is positioned at surface of metal electrode under the described ball, described soakage layer is positioned at described barrier layer surface, described barrier layer has the 3rd apron structure, and described soakage layer has the skirt structure all around.
7. chip-packaging structure as claimed in claim 6 is characterized in that, the thickness of described barrier layer is 0.05 μ m to 5 μ m.
8. chip-packaging structure as claimed in claim 6 is characterized in that, the thickness of described soakage layer is 0.05 μ m to 10 μ m.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012205866562U CN202917475U (en) | 2012-11-08 | 2012-11-08 | Chip packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012205866562U CN202917475U (en) | 2012-11-08 | 2012-11-08 | Chip packaging structure |
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| CN202917475U true CN202917475U (en) | 2013-05-01 |
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| CN2012205866562U Expired - Lifetime CN202917475U (en) | 2012-11-08 | 2012-11-08 | Chip packaging structure |
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| CN (1) | CN202917475U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014071814A1 (en) * | 2012-11-08 | 2014-05-15 | 南通富士通微电子股份有限公司 | Chip packaging structure and packaging method |
| US9293432B2 (en) | 2012-11-08 | 2016-03-22 | Nantong Fujitsu Microelectronics Co., Ltd. | Metal contact for chip packaging structure |
| US9379077B2 (en) | 2012-11-08 | 2016-06-28 | Nantong Fujitsu Microelectronics Co., Ltd. | Metal contact for semiconductor device |
| US9548282B2 (en) | 2012-11-08 | 2017-01-17 | Nantong Fujitsu Microelectronics Co., Ltd. | Metal contact for semiconductor device |
-
2012
- 2012-11-08 CN CN2012205866562U patent/CN202917475U/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014071814A1 (en) * | 2012-11-08 | 2014-05-15 | 南通富士通微电子股份有限公司 | Chip packaging structure and packaging method |
| US9293432B2 (en) | 2012-11-08 | 2016-03-22 | Nantong Fujitsu Microelectronics Co., Ltd. | Metal contact for chip packaging structure |
| US9379077B2 (en) | 2012-11-08 | 2016-06-28 | Nantong Fujitsu Microelectronics Co., Ltd. | Metal contact for semiconductor device |
| US9548282B2 (en) | 2012-11-08 | 2017-01-17 | Nantong Fujitsu Microelectronics Co., Ltd. | Metal contact for semiconductor device |
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Address after: Jiangsu province Nantong City Chongchuan road 226006 No. 288 Patentee after: TONGFU MICROELECTRONICS Co.,Ltd. Address before: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Patentee before: NANTONG FUJITSU MICROELECTRONICS Co.,Ltd. |
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Granted publication date: 20130501 |