CN209823394U - High-efficiency multi-path low-cost direct current overload detection protection circuit - Google Patents
High-efficiency multi-path low-cost direct current overload detection protection circuit Download PDFInfo
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- CN209823394U CN209823394U CN201920819697.3U CN201920819697U CN209823394U CN 209823394 U CN209823394 U CN 209823394U CN 201920819697 U CN201920819697 U CN 201920819697U CN 209823394 U CN209823394 U CN 209823394U
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Abstract
The utility model discloses a protection circuit technical field's a high-efficient multichannel low-cost direct current overload detection protection circuit, including detection circuitry, a power supply, drive circuit, comparator and delay circuit, detection circuitry feed end electric connection is at the power, detection circuitry establishes ties with drive circuit, detection circuitry's output and comparator's input electric connection, comparator's power end electric connection is at the power, comparator's output and delay circuit's input electric connection, delay circuit's power end electric connection is at the power, delay circuit's output and drive circuit's input electric connection, the utility model discloses possess better environmental suitability, it is great to have avoided delay time error, the uniformity is than relatively poor problem, realizes automatic cutout's guard action, has solved MOS pipe overheat, fragile problem.
Description
Technical Field
The utility model relates to a protection circuit technical field specifically is a high-efficient multichannel low-cost direct current overload detection protection circuit.
Background
The existing low-voltage direct-current overload protection generally comprises overcurrent protection and short-circuit protection. Generally, a triode and a sampling resistor are adopted to carry out high-end current detection on an MOS (metal oxide semiconductor) tube, the detected voltage controls the conduction and the disconnection of the MOS through the triode, and then the MOS preceding stage triode is started in a delayed manner according to the charge-discharge characteristics of a capacitor, so that the purpose of delayed driving is achieved, and the overload protection is realized.
Because the low-voltage direct-current overload protection circuit in the prior art directly adopts the resistance-capacitance control delay circuit, the delay time error is larger, the consistency is poorer, and meanwhile, the triode management and control overcurrent protection circuit is adopted, so that the MOS transistor works in an incomplete conduction state easily, and the MOS transistor is overheated and is easy to damage.
Based on this, the utility model designs a high-efficient multichannel low-cost direct current overload detection protection circuit to solve above-mentioned problem.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a high-efficient multichannel low-cost direct current overload detection protection circuit to because directly adopt resistance-capacitance control delay circuit among the low pressure direct current overload protection circuit of the prior art who proposes in solving above-mentioned background art, delay time error is great, and the uniformity is relatively poor, adopts triode management and control overcurrent protection circuit simultaneously, makes MOS pipe work not complete on-state easily, thereby leads to MOS pipe overheated, fragile problem.
In order to achieve the above object, the utility model provides a following technical scheme:
a high-efficiency multi-path low-cost DC overload detection protection circuit comprises a detection circuit, a power supply, a drive circuit, a comparator and a delay circuit;
the power supply end of the detection circuit is electrically connected to the power supply, the detection circuit is connected with the driving circuit in series, and the output end of the detection circuit is electrically connected with the input end of the comparator;
the power end of the comparator is electrically connected with the power supply, and the output end of the comparator is electrically connected with the input end of the delay circuit;
the power end of the delay circuit is electrically connected to the power supply, and the output end of the delay circuit is electrically connected to the input end of the driving circuit.
Preferably, the detection circuit includes a PNP tube Q9, a detection resistor Rs3, a detection resistor Rs5, a resistor R21, a resistor R29, a resistor R33, and a capacitor C8, the power supply is electrically connected to the first end of the resistor Rs3, the second end of the resistor Rs3 is electrically connected to the first end of the detection resistor Rs5, the second end of the detection resistor Rs5 is electrically connected to the driving circuit, the power supply is electrically connected to the emitter of the PNP tube Q9, the base of the PNP tube Q9 is connected to the second end of the detection resistor Rs5 through a resistor R21, the collector of the PNP tube Q9 is electrically connected to the first end of the resistor R29, the second end of the resistor R29 is electrically connected to the first end of the resistor R33, the first end of the capacitor C8, and the second ends of the resistor R33 and the capacitor C8 are both grounded.
Preferably, a thermistor PTC2 is connected in series between the power supply and the PNP tube Q9.
Preferably, the driving circuit includes a resistor R22, a MOS transistor Q8, a resistor R25, an NPN transistor Q10, a resistor R31, a resistor R28, an NPN transistor Q31, and a resistor R35, the detection circuit is electrically connected to a first end of the resistor R22 and a source of the MOS transistor Q8, a gate of the MOS transistor Q8 and a second end of the resistor R22 are both electrically connected to a first segment of the resistor R25, a second end of the resistor R25 is electrically connected to a collector of the NPN transistor Q10, a base of the NPN transistor Q10 is electrically connected to the first end of the resistor R28, the first end of the resistor R31, and the collector of the NPN transistor Q13, a second end of the resistor R31 is electrically connected to an emitter of the NPN transistor Q10, a base of the NPN transistor Q13 is electrically connected to the first end of the resistor R35, and a second end of the resistor R35 is electrically connected to an emitter of the NPN transistor Q13.
Preferably, the comparator comprises a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a capacitor C1 and an LM358 chip packaged by SOP8, the OUT1 port of the LM358 chip is electrically connected with the V1+ interface through a resistor R1, the V2+ port and the OUT2 port of the LM358 chip are electrically connected through a resistor R3, the power supply is electrically connected with the first end of the capacitor C1, the first end of the resistor R2, the first end of the resistor R4 and the VCC end of the LM358 chip, the second end of the resistor R2 is electrically connected with the V1-end of the LM358 chip and the first end of the resistor R5, the second end of the resistor R4 is electrically connected with the first end of the resistor R6 and the V2-end of the LM358 chip, the second end of the capacitor C1, the second end of the resistor R5, the second end of the resistor R6 and the GND interface end of the LM358 chip are all grounded.
Preferably, the delay circuit comprises a resistor R24, a resistor R30, a resistor R27, a resistor R32, a resistor R34, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C9, a capacitor C10, an NPN tube Q11, an NPN tube Q12 and an NE556 chip.
Preferably, the plurality of driving circuits are provided, and the plurality of driving circuits are connected in parallel.
Compared with the prior art, the beneficial effects of the utility model are that:
the utility model discloses a be provided with thermistor PTC2, according to thermistor PTC 2's resistance characteristic, when operational environment high temperature, can carry out temperature compensation to detection circuitry, make output voltage stable to realize the voltage compensation function, avoided the temperature drift to influence and flow over the current point setting, consequently possess better environmental suitability, thermistor PTC2 should install be close to heat-sensitive element as far as possible.
The utility model discloses a be provided with time base chip NE556 and hinder the container spare, delay time is confirmed by hindering the appearance setting value, does not have delay output high level during the protection, and output low level when overcurrent condition cancellation delay realizes the delay automatic recovery function, has avoided delay time error great, and the uniformity is than relatively poor problem.
The utility model discloses a be provided with drive circuit, turn-off MOS pipe Q8's preceding stage triode through NPN pipe among the drive circuit to realize automatic cutout's guard action.
The utility model discloses a be provided with PNP pipe Q9 and comparator. Because PNP manages the electronic characteristic, when MOS pipe Q8 high-end has certain electric current, can form certain voltage, compare through comparator and the voltage that sets up in advance, output relatively stable level volume, realize overflowing the detection function, avoided MOS pipe work in the complete on-state of not having, solved MOS pipe overheated, the fragile problem.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic diagram of the detection circuit and the driving circuit of the present invention;
fig. 2 is a schematic diagram of the comparator circuit of the present invention;
FIG. 3 is a schematic diagram of the delay circuit of the present invention;
fig. 4 is a schematic diagram of the parallel driving circuit of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without creative efforts belong to the protection scope of the present invention.
Referring to fig. 1-4, the present invention provides a technical solution:
a high-efficiency multi-path low-cost DC overload detection protection circuit comprises a detection circuit, a power supply, a drive circuit, a comparator and a delay circuit;
the power supply end of the detection circuit is electrically connected to the power supply, the detection circuit is connected with the driving circuit in series, and the output end of the detection circuit is electrically connected with the input end of the comparator;
the power supply end of the comparator is electrically connected with the power supply, and the output end of the comparator is electrically connected with the input end of the delay circuit;
the power end of the delay circuit is electrically connected to the power supply, and the output end of the delay circuit is electrically connected to the input end of the driving circuit.
The detection circuit comprises a PNP tube Q9, a detection resistor Rs3, a detection resistor Rs5, a resistor R21, a resistor R29, a resistor R33 and a capacitor C8, a power supply is electrically connected with a first end of the resistor Rs3, a second end of the resistor Rs3 is electrically connected with a first end of the detection resistor Rs5, a second end of the detection resistor Rs5 is electrically connected with a driving circuit, the power supply is electrically connected with an emission collector of the PNP tube Q5, a base of the PNP tube Q5 is connected with a second end of the detection resistor Rs5 through the resistor R5, a collector of the NPN tube Q5 is electrically connected with a first end of the resistor R5, a first end of the capacitor C5 and a comparator, a second end of the resistor R5 and a second end of the capacitor C5 are both grounded, a thermistor 5 is further connected between the power supply and the PNP tube Q5 in series, and the driving circuit comprises a resistor R5, a MOS tube Q5, a resistor R5, a resistor R36, An NPN transistor Q31 and a resistor R31, the detection circuit is electrically connected to a first end of the resistor R31 and a source of the MOS transistor Q31, a gate of the MOS transistor Q31 and a second end of the resistor R31 are electrically connected to a first segment of the resistor R31, a second end of the resistor R31 is electrically connected to a collector of the NPN transistor Q31, a base of the NPN transistor Q31 is electrically connected to the first end of the resistor R31, the first end of the resistor R31 and the collector of the NPN transistor Q31, the second end of the resistor R31 is electrically connected to the emitter of the NPN transistor Q31, the base of the NPN transistor Q31 is electrically connected to the first end of the resistor R31, the second end of the resistor R31 is electrically connected to the emitter of the NPN transistor Q31, the comparator includes the resistor R31, the capacitor C31, the resistor R31, the resistor LM chip 358 and the resistor R31 are electrically connected to the LM chip 31 through the resistor LM 31 + 31, and the resistor LM chip 31, the power supply is electrically connected with a first end of a capacitor C1, a first end of a resistor R2, a first end of a resistor R4 and a VCC end of an LM358 chip, a second end of the resistor R2 is electrically connected with a V1-end of the LM358 chip and a first end of a resistor R5, a second end of a resistor R4 is electrically connected with a first end of a resistor R6 and a V2-end of the LM358 chip, a second end of a capacitor C1, a second end of the resistor R5, a second end of a resistor R6 and a GND interface end of the LM358 chip are grounded, the delay circuit comprises a resistor R24, a resistor R30, a resistor R27, a resistor R32, a resistor R34, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C9, a capacitor C10, an NPN tube Q11, an NPN tube Q12 and an NE chip 556, and a plurality of driving circuits are connected in parallel.
One specific application of this embodiment is:
the utility model discloses a be provided with PNP pipe Q9 and comparator. Because PNP manages the electronic characteristic, when MOS pipe Q8 high-end has certain electric current, can form certain voltage, compare through comparator and the voltage that sets up in advance, output relatively stable level volume, realize overflowing the detection function, avoided MOS pipe work in the complete on-state of not having, solved MOS pipe overheated, the fragile problem.
The utility model discloses a be provided with thermistor PTC2, according to thermistor PTC 2's resistance characteristic, when operational environment high temperature, can carry out temperature compensation to detection circuitry, make output voltage stable to realize the voltage compensation function, avoided the temperature drift to influence and flow over the current point setting, consequently possess better environmental suitability, thermistor PTC2 should install be close to heat-sensitive element as far as possible.
The utility model discloses a be provided with time base chip NE556 and hinder the container spare, delay time is confirmed by hindering the appearance setting value, does not have delay output high level during the protection, and output low level when overcurrent condition cancellation delay realizes the delay automatic recovery function, has avoided delay time error great, and the uniformity is than relatively poor problem.
The utility model discloses a be provided with drive circuit, turn-off MOS pipe Q8's preceding stage triode through NPN pipe among the drive circuit to realize automatic cutout's guard action.
This company's high-efficient multichannel low-cost direct current overload detection protection circuit of research and development, the purpose is:
the utility model discloses a be provided with multiunit drive circuit all with detection circuitry electric connection, realized the one-way detection, multichannel overload protection and output.
In the description herein, references to the description of "one embodiment," "an example," "a specific example," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The preferred embodiments of the present invention disclosed above are intended only to help illustrate the present invention. The preferred embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, to thereby enable others skilled in the art to best understand the invention for and utilize the invention. The present invention is limited only by the claims and their full scope and equivalents.
Claims (6)
1. The utility model provides a high-efficient multichannel low-cost direct current overload detection protection circuit which characterized in that:
the circuit comprises a detection circuit, a power supply, a driving circuit, a comparator and a time delay circuit;
the power supply end of the detection circuit is electrically connected with the power supply, the detection circuit is electrically connected with the driving circuit, and the output end of the detection circuit is electrically connected with the input end of the comparator;
the power end of the comparator is electrically connected with the power supply, and the output end of the comparator is electrically connected with the input end of the delay circuit;
the power end of the delay circuit is electrically connected to the power supply, and the output end of the delay circuit is electrically connected to the input end of the driving circuit.
2. The efficient multi-path low-cost direct current overload detection protection circuit according to claim 1, wherein: the detection circuit comprises a PNP tube Q9, a detection resistor Rs3, a detection resistor Rs5, a resistor R21, a resistor R29, a resistor R33 and a capacitor C8, wherein the power supply is electrically connected with a first end of a resistor Rs3, a second end of the resistor Rs3 is electrically connected with a first end of the detection resistor Rs5, a second end of the detection resistor Rs5 is electrically connected with the driving circuit, the power supply is electrically connected with an emitter and a collector of the PNP tube Q9, a base of the PNP tube Q9 is connected with a second end of the detection resistor Rs5 through a resistor R21, a collector of the PNP tube Q9 is electrically connected with a first end of the resistor R29, a second end of the resistor R29 is electrically connected with a first end of a resistor R33, a first end of the capacitor C8 and a comparator, and a second end of the resistor R33 and a second end of the capacitor C8 are both grounded.
3. The efficient multi-path low-cost direct current overload detection protection circuit according to claim 2, wherein: and a thermistor PTC2 is also connected between the power supply and the PNP tube Q9.
4. The efficient multi-path low-cost direct current overload detection protection circuit according to claim 2, wherein: the driving circuit comprises a resistor R22, a MOS transistor Q8, a resistor R25, an NPN transistor Q10, a resistor R31, a resistor R28, an NPN transistor Q31 and a resistor R35, the detection circuit is electrically connected with a first end of the resistor R22 and a source of the MOS transistor Q8, a gate of the MOS transistor Q8 and a second end of the resistor R22 are electrically connected with a first section of the resistor R25, a second end of the resistor R25 is electrically connected with a collector of the NPN transistor Q10, a base of the NPN transistor Q10 is electrically connected with a first end of the resistor R28, a first end of the resistor R31 and a collector of the NPN transistor Q13, a second end of the resistor R31 and an emitter of the NPN transistor Q10 are all grounded, a base of the NPN transistor Q13 is electrically connected with a first end of the resistor R35, and a second end of the resistor R35 and an emitter of the NPN transistor Q13 are all grounded.
5. The efficient multi-path low-cost direct current overload detection protection circuit according to claim 1, wherein: the comparator comprises a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a capacitor C1 and an LM358 chip packaged by SOP8, the OUT1 port of the LM358 chip is electrically connected with the V1+ interface through a resistor R1, the V2+ port and the OUT2 port of the LM358 chip are electrically connected through a resistor R3, the power supply is electrically connected with the first end of the capacitor C1, the first end of the resistor R2, the first end of the resistor R4 and the VCC end of the LM358 chip, the second end of the resistor R2 is electrically connected with the V1-end of the LM358 chip and the first end of the resistor R5, the second end of the resistor R4 is electrically connected with the first end of the resistor R6 and the V2-end of the LM358 chip, the second end of the capacitor C1, the second end of the resistor R5, the second end of the resistor R6 and the GND interface end of the LM358 chip are all grounded.
6. The efficient multi-path low-cost direct current overload detection protection circuit according to claim 1, wherein: the delay circuit comprises a resistor R24, a resistor R30, a resistor R27, a resistor R32, a resistor R34, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C9, a capacitor C10, an NPN tube Q11, an NPN tube Q12 and an NE556 chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920819697.3U CN209823394U (en) | 2019-06-03 | 2019-06-03 | High-efficiency multi-path low-cost direct current overload detection protection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920819697.3U CN209823394U (en) | 2019-06-03 | 2019-06-03 | High-efficiency multi-path low-cost direct current overload detection protection circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209823394U true CN209823394U (en) | 2019-12-20 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201920819697.3U Active CN209823394U (en) | 2019-06-03 | 2019-06-03 | High-efficiency multi-path low-cost direct current overload detection protection circuit |
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| Country | Link |
|---|---|
| CN (1) | CN209823394U (en) |
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- 2019-06-03 CN CN201920819697.3U patent/CN209823394U/en active Active
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