CN209692711U - A kind of wide input range high cmrr operation transconductance amplifier - Google Patents
A kind of wide input range high cmrr operation transconductance amplifier Download PDFInfo
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Abstract
The utility model discloses a kind of wide input range high cmrr operation transconductance amplifiers, including biasing circuit and operation transconductance amplifier main body circuit, the biasing circuit to provide bias current for operation transconductance amplifier main body circuit；The utility model has the advantage of, it can be while common mode input varies widely and realizes preferable CMRR performance in range, maintain input difference to the stabilization of transconductance value, and input stage tail current source still is able to provide more constant bias current when compared with low pressure drop.
Description
Technical field
The utility model belongs to analogue layout field, more particularly, to a kind of high common mode inhibition of wide input range
Compare operation transconductance amplifier.
Background technique
Operation transconductance amplifier is the amplifying unit for being capable of providing high transconductance gain, is operation amplifier in CMOS integrated circuit
The principal mode of device (in CMOS integrated circuit, operational amplifier mainly drives capacitive load).Two-level configuration is that operation transconductance is put
The main selection of big device, the first order are Differential Input pair, provide differential transconductance and inhibit common mode mutual conductance, and output electric current utilizes it certainly
Height output impedance characteristic is converted to voltage signal, drives second level transconductance cell to provide further transadmittance gain.It is this
Structure has very high power consumption efficiency in terms of providing loop gain.
There are two input terminals for CMOS operation transconductance amplifier, are metal-oxide-semiconductor grid, output end is metal-oxide-semiconductor drain electrode, therefore is had
There is the characteristics of high input impedance-high output impedance.Input stage is a source electrode coupled differential to structure, due to the height of tail current source
Output impedance characteristic, operation transconductance amplifier are insensitive to input common mode variations, that is, have the characteristics that high cmrr (CMRR).
That is: the output impedance of operation transconductance amplifier input stage tail current source is bigger, and the common mode rejection performance of operation transconductance amplifier is got over
It is good.
Traditional tail current source is a job in the metal-oxide-semiconductor of saturation region, is drained as current output terminal, high output impedance master
If being guaranteed by biggish drain-source voltage (i.e. current source pressure drop) and the longer channel length of metal-oxide-semiconductor.With CMOS technology
The sub-micro stage is come into, even if choosing long channel length, the output impedance of metal-oxide-semiconductor is also seriously degenerated.Meanwhile supply voltage
It is even lower to be reduced to 1.2V, voltage margin is very nervous for analog circuit, can distribute to the pressure drop of tail current source
It is smaller, the problem of output impedance deficiency when being further degrading metal-oxide-semiconductor as basic tail current source.
The shortcomings that prior art, is as follows:
(1) when operation transconductance amplifier is applied in reverse phase ratio enlargement topology, input terminal is virtual earth, therefore, fortune
The position that the input terminal for putting trsanscondutance amplifier is biased in close to power track can alleviate that tail current source voltage margin is insufficient to ask
Topic.Disadvantage is: output end is typically biased at half supply voltage to obtain the maximum output voltage amplitude of oscillation, i.e. input terminal and output
The bias voltage at end is different, then just having bias current to flow through on feedback network.If adjusting the resistance in feedback network
To change gain, what the transition for flowing through the bias current of feedback network can bring amplifier establishes problem.
(2) for the topology such as mutual conductance-C integrator, in-phase proportion amplifier architecture, the input of operation transconductance amplifier
End is connection input signal.The input range of so operation transconductance amplifier is exactly an important performance indicator.For passing
It unites for operation transconductance amplifier, minimum voltage needed for input terminal to power track (minimum voltage or ceiling voltage) is equal to 1
The sum of a VGS and 1 VDSAT, actual value generally will also larger, and otherwise CMRR can severe exacerbation.
A kind of common solution is simply to remove tail current source, and input stage is made of a pair of of common source amplifying stage, that is, is adopted
Use pseudo differential architectures.But the advantages of high CMRR of traditional source electrode coupled differential pair, disappears, and in order to alleviate this problem, input
Grade also need to introduce a feedforward loop circuit with offset common mode input influence (referring to paper: Mohieldin, Ahmed Nader,
Edgar Sánchez-Sinencio,and JoséSilva-Martínez."A fully balanced pseudo-
differential OTA with common-mode feedforward and inherent common-mode
feedback detector."IEEE Journal of Solid-State Circuits,38.4(2003):663-668.)。
This method not only significantly increases current drain, and there are also input bias current non-constant the problem of leading to input mutual conductance variation.
Summary of the invention
The utility model aim is to provide a kind of wide input range high cmrr operation transconductance amplifier, can be defeated
While entering the preferable CMRR performance of realization in common-mode voltage large change range, maintain input difference to the stabilization of transconductance value, and
Input stage tail current source still is able to provide more constant bias current when compared with low pressure drop.
The technical solution of the utility model is: a kind of wide input range high cmrr operation transconductance amplifier, including
Biasing circuit and operation transconductance amplifier main body circuit, the biasing circuit provide biasing for operation transconductance amplifier main body circuit
Electric current.
The biasing circuit includes the first NMOS tube N1, the second NMOS tube N2, the 3rd NMOS as a preferred technical solution,
Pipe N3, the 7th NMOS tube N7, the 8th NMOS tube N8, the 9th NMOS tube N9, the first PMOS tube P1, the second PMOS tube P2, the 5th
PMOS tube P5, the 6th PMOS tube P6, reference current source IREF, resistance R1 and voltage source VDD；
The drain electrode of the first NMOS tube N1 is connected to the source electrode of the 7th NMOS tube N7, the drain electrode of the second NMOS tube N2
It is connected to the source electrode of the 8th NMOS tube N8, the drain electrode of the third NMOS tube N3 is connected to the source electrode of the 9th NMOS tube N9；It is described
The grid of first NMOS tube N1 is connected respectively to the grid of the second NMOS tube N2, the grid of third NMOS tube N3 and the 7th NMOS tube
The drain electrode of N7；The drain electrode of the 7th NMOS tube N7 is connected to one end of resistance R1, and the other end of the resistance R1 is separately connected
To the grid of the 7th NMOS tube N7, the grid of the 8th NMOS tube N8, the 9th NMOS tube N9 grid, reference current source IREF
One end, and the reference current source IREFThe other end be connected respectively to the source electrode of the first PMOS tube P1, the second PMOS tube P2
Source electrode and voltage source VDD；The drain electrode of the 8th NMOS tube N8 is connected respectively to the grid of the first PMOS tube P1, the second PMOS tube
The drain electrode of the drain electrode of the grid of P2 and the 5th PMOS tube P5, the 9th NMOS tube N9 is connected respectively to the grid of the 5th PMOS tube P5
Pole, the grid of the 6th PMOS tube P6 and drain electrode；The drain electrode of the first PMOS tube P1 is connected to the source electrode of the 5th PMOS tube P5, the
The drain electrode of two PMOS tube P2 is connected to the source electrode of the 6th PMOS tube P6, while the first NMOS tube N1, second NMOS tube
The source grounding of N2, the third NMOS tube N3.
The operation transconductance amplifier main body circuit includes the 4th NMOS tube N4, the 5th as a preferred technical solution,
NMOS tube N5, the 6th NMOS tube N6, the tenth NMOS tube N10, the 11st NMOS tube N11, third PMOS tube P3, the 4th PMOS tube
P4, the 7th PMOS tube P7, the 8th PMOS tube P8, the 9th PMOS tube P9, the tenth PMOS tube P10, the 11st PMOS tube P11 and resistance
R2；
The voltage source VDD is connected respectively to the source electrode of third PMOS tube P3, the source electrode of the 4th PMOS tube P4, the 11st
The source electrode of PMOS tube P11；The drain electrode of the second PMOS tube P2 is connected respectively to the source electrode and the tenth PMOS of the 9th PMOS tube P9
The source electrode of pipe P10；The reference current source IREFConnection resistance R1 one end be connected respectively to the tenth NMOS tube N10 grid and
The grid of 11st NMOS tube N11；The grid of the first NMOS tube N1 is connected respectively to the grid of the 4th NMOS tube N4, the 5th
The grid of the grid of NMOS tube N5 and the 6th NMOS tube N6；The grid of the third PMOS tube P3 is connected respectively to the 4th PMOS tube
The grid of P4, the drain electrode of the 7th PMOS tube P7 and resistance R2 one end；The other end of the resistance R2 is connected respectively to the tenth
The drain electrode of NMOS tube N10, the grid of the 7th PMOS tube P7 and the 8th PMOS tube P8 grid；The drain electrode of the third PMOS tube P3
It is connected to the source electrode of the 7th PMOS tube P7, the drain electrode of the 4th PMOS tube P4 is connected to the source electrode of the 8th PMOS tube P8；It is described
The drain electrode of 8th PMOS tube P8 is connected respectively to the drain electrode of the 11st NMOS tube N11, the grid of the 11st PMOS tube P11；It is described
The drain electrode of 9th PMOS tube P9 is connected respectively to drain electrode and the source electrode of the tenth NMOS tube N10 of the 4th NMOS tube N4；Described tenth
The drain electrode of PMOS tube P10 is connected respectively to drain electrode and the source electrode of the 11st NMOS tube N11 of the 5th NMOS tube N5；Described 11st
The drain electrode of PMOS tube P11 is connected to the drain electrode of the 6th NMOS tube N6 and as voltage output end Vout, the 9th PMOS tube P9
Grid as voltage input end Vin, the grid of the tenth PMOS tube P10 is as voltage input end Vip；4th NMOS simultaneously
The source electrode of pipe N4, the source electrode of the 5th NMOS tube N5, the 6th NMOS tube N6 source grounding.
The size of the first PMOS tube P1 and the second PMOS tube P2 are mutually matched as a preferred technical solution,
And size ratio is 1:M+1.
The size of the 5th PMOS tube P5 and the 6th PMOS tube P6 is mutually matched as a preferred technical solution,
And size ratio is 1:1.
The utility model has the advantages that:
1. the wide input range high cmrr operation transconductance amplifier of the utility model, can be in common mode input
While varying widely the preferable CMRR performance of realization in range, maintain input difference to the stabilization of transconductance value, and input stage tail is electric
Stream source still is able to provide more constant bias current when compared with low pressure drop；
2. the utility model is due to the limitation of bandwidth, suitable with traditional structure in the CMRR performance of high frequency treatment, but low
There is apparent gain effect at frequency；
3. the utility model reverse phase ratio enlargement is equal to (or close) output in application, input offset voltage can be set
Bias voltage, transient response when can switch in this way to avoid (or alleviation) gain；
4. the utility model can effectively maintain high cmrr in the biggish variation range of common mode input.
Detailed description of the invention
The utility model is further described with reference to the accompanying drawings and embodiments:
Fig. 1 is the electrical block diagram of the utility model.
Fig. 2 is the CMRR frequency response simulation curve comparison diagram of the utility model and traditional structure；
Fig. 3 is the low frequency CMRR of the utility model and traditional structure and the simulation curve of common mode input relationship compares
Figure.
Specific embodiment
Embodiment: shown in referring to Fig.1, a kind of wide input range high cmrr operation transconductance amplifier, including biasing
Circuit and operation transconductance amplifier main body circuit, biasing circuit provide bias current for operation transconductance amplifier main body circuit.
Biasing circuit includes the first NMOS tube N1, the second NMOS tube N2, third NMOS tube N3, the 7th NMOS in the present embodiment
Pipe N7, the 8th NMOS tube N8, the 9th NMOS tube N9, the first PMOS tube P1, the second PMOS tube P2, the 5th PMOS tube P5, the 6th
PMOS tube P6, reference current source IREF, resistance R1 and voltage source VDD；The drain electrode of first NMOS tube N1 is connected to the 7th NMOS tube N7
Source electrode, the drain electrode of the second NMOS tube N2 is connected to the source electrode of the 8th NMOS tube N8, and the drain electrode of third NMOS tube N3 is connected to
The source electrode of nine NMOS tube N9；The grid of first NMOS tube N1 is connected respectively to the grid of the second NMOS tube N2, third NMOS tube N3
Grid and the 7th NMOS tube N7 drain electrode；The drain electrode of 7th NMOS tube N7 is connected to one end of resistance R1, and resistance R1's is another
End is connected respectively to grid, the reference current of the grid of the 7th NMOS tube N7, the grid of the 8th NMOS tube N8, the 9th NMOS tube N9
Source IREFOne end, and reference current source IREFThe other end be connected respectively to the source electrode of the first PMOS tube P1, the second PMOS tube P2
Source electrode and voltage source VDD；The drain electrode of 8th NMOS tube N8 is connected respectively to the grid of the first PMOS tube P1, the second PMOS tube P2
Grid and the 5th PMOS tube P5 drain electrode, the drain electrode of the 9th NMOS tube N9 is connected respectively to the grid of the 5th PMOS tube P5,
The grid of six PMOS tube P6 and drain electrode；The drain electrode of first PMOS tube P1 is connected to the source electrode of the 5th PMOS tube P5, the second PMOS tube
The drain electrode of P2 is connected to the source electrode of the 6th PMOS tube P6, while the first NMOS tube N1, the second NMOS tube N2, third NMOS tube N3
Source grounding.
Operation transconductance amplifier main body circuit includes the 4th NMOS tube N4, the 5th NMOS tube N5, the 6th in the present embodiment
NMOS tube N6, the tenth NMOS tube N10, the 11st NMOS tube N11, third PMOS tube P3, the 4th PMOS tube P4, the 7th PMOS tube
P7, the 8th PMOS tube P8, the 9th PMOS tube P9, the tenth PMOS tube P10, the 11st PMOS tube P11 and resistance R2；Voltage source VDD
It is connected respectively to the source electrode of the source electrode of third PMOS tube P3, the source electrode of the 4th PMOS tube P4, the 11st PMOS tube P11；Second
The drain electrode of PMOS tube P2 is connected respectively to the source electrode of the 9th PMOS tube P9 and the source electrode of the tenth PMOS tube P10；Reference current source IREF
One end of connection resistance R1 is connected respectively to the grid of the tenth NMOS tube N10 and the grid of the 11st NMOS tube N11；First NMOS
The grid of pipe N1 is connected respectively to the grid, the grid of the 5th NMOS tube N5 and the grid of the 6th NMOS tube N6 of the 4th NMOS tube N4
Pole；The grid of third PMOS tube P3 is connected respectively to the grid of the 4th PMOS tube P4, the drain electrode of the 7th PMOS tube P7 and resistance R2
One end；The other end of resistance R2 is connected respectively to the grid and the 8th of the drain electrode of the tenth NMOS tube N10, the 7th PMOS tube P7
The grid of PMOS tube P8；The drain electrode of third PMOS tube P3 is connected to the source electrode of the 7th PMOS tube P7, the drain electrode of the 4th PMOS tube P4
It is connected to the source electrode of the 8th PMOS tube P8；The drain electrode of 8th PMOS tube P8 is connected respectively to the drain electrode of the 11st NMOS tube N11,
The grid of 11 PMOS tube P11；The drain electrode of 9th PMOS tube P9 is connected respectively to drain electrode and the tenth NMOS of the 4th NMOS tube N4
The source electrode of pipe N10；The drain electrode of tenth PMOS tube P10 is connected respectively to drain electrode and the 11st NMOS tube N11 of the 5th NMOS tube N5
Source electrode；The drain electrode of 11st PMOS tube P11 is connected to the drain electrode of the 6th NMOS tube N6 and as voltage output end Vout, and the 9th
The grid of PMOS tube P9 is as voltage input end Vin, and the grid of the tenth PMOS tube P10 is as voltage input end Vip；While the 4th
The source electrode of NMOS tube N4, the source electrode of the 5th NMOS tube N5, the 6th NMOS tube N6 source grounding.
The first NMOS tube N1, the second NMOS tube N2 and third NMOS tube N3, the 7th NMOS tube N7, the 8th in the present embodiment
NMOS tube N8 and the 9th NMOS tube N9 constitutes traditional common-source common-gate current mirror, and the 5th PMOS tube P5 and the 6th PMOS is flowed through in guarantee
The electric current of pipe P6 is equal, while the size of the 5th PMOS tube P5 and the 6th PMOS tube P6 is mutually matched, and size ratio is 1:1, with
Realize the equal of P1 and P2 drain voltage, while the size of the first PMOS tube P1 and the second PMOS tube P2 are mutually matched, and size
Than for 1:M+1 (M is settable amount), then the electric current for being supplied to operational amplification input stage is equal to the first PMOS tube P1 bias current
M times.When common mode input is higher, the first PMOS tube P1 and the second PMOS tube P2 can be close even into linear zone, but
It is that the condition that their VGS and VDS are equal makes current mirror still be able to be normally carried out, to maintain output more constant
Bias current.
The utility model is built under 180nm CMOS standard technology (nominal voltage 1.8V, threshold voltage are about 0.7V)
Circuit is emulated, and is compared with traditional structure.The common mode input of Fig. 2 is set as half supply voltage, i.e.,
0.9V, low frequency CMRR improve 56dB；The frequency of Fig. 3 is set as 100Hz, in traditional structure, when common mode input is higher than
After 0.6V, CMRR starts to be remarkably decreased；And the high CMRR of the utility model can maintain to common mode input to increase up to
0.93V, it means that the common-mode input range of the utility model has obtained larger expansion.
The above embodiments are only for explaining the technical ideas and features of the present invention, and its object is to allow be familiar with technique
Personage can understand the content of the utility model and implement accordingly, do not limit the protection scope of the present invention.
All equivalent change or modifications according to made by the spirit of the present invention essence, should all cover the protection scope of the utility model it
It is interior.
Claims (3)
1. a kind of wide input range high cmrr operation transconductance amplifier, which is characterized in that including biasing circuit and operation
Trsanscondutance amplifier main body circuit, the biasing circuit provide bias current for operation transconductance amplifier main body circuit；
The biasing circuit includes the first NMOS tube N1, the second NMOS tube N2, third NMOS tube N3, the 7th NMOS tube N7, the 8th
NMOS tube N8, the 9th NMOS tube N9, the first PMOS tube P1, the second PMOS tube P2, the 5th PMOS tube P5, the 6th PMOS tube P6, ginseng
Examine current source IREF, resistance R1 and voltage source VDD；
The drain electrode of the first NMOS tube N1 is connected to the source electrode of the 7th NMOS tube N7, the drain electrode connection of the second NMOS tube N2
Drain electrode to the source electrode of the 8th NMOS tube N8, the third NMOS tube N3 is connected to the source electrode of the 9th NMOS tube N9；Described first
The grid of NMOS tube N1 is connected respectively to the grid of the second NMOS tube N2, the grid of third NMOS tube N3 and the 7th NMOS tube N7's
Drain electrode；The drain electrode of the 7th NMOS tube N7 is connected to one end of resistance R1, and the other end of the resistance R1 is connected respectively to institute
State grid, the reference current source I of the grid of the 7th NMOS tube N7, the grid of the 8th NMOS tube N8, the 9th NMOS tube N9REFOne
End, and the reference current source IREFThe other end be connected respectively to the source electrode of the source electrode of the first PMOS tube P1, the second PMOS tube P2
With voltage source VDD；The drain electrode of the 8th NMOS tube N8 is connected respectively to the grid of the first PMOS tube P1, the second PMOS tube P2
The drain electrode of grid and the 5th PMOS tube P5, the drain electrode of the 9th NMOS tube N9 be connected respectively to the grid of the 5th PMOS tube P5,
The grid of 6th PMOS tube P6 and drain electrode；The drain electrode of the first PMOS tube P1 is connected to the source electrode of the 5th PMOS tube P5, and second
The drain electrode of PMOS tube P2 is connected to the source electrode of the 6th PMOS tube P6, at the same the first NMOS tube N1, the second NMOS tube N2,
The source grounding of the third NMOS tube N3；
The operation transconductance amplifier main body circuit includes the 4th NMOS tube N4, the 5th NMOS tube N5, the 6th NMOS tube N6, the tenth
NMOS tube N10, the 11st NMOS tube N11, third PMOS tube P3, the 4th PMOS tube P4, the 7th PMOS tube P7, the 8th PMOS tube
P8, the 9th PMOS tube P9, the tenth PMOS tube P10, the 11st PMOS tube P11 and resistance R2；
The voltage source VDD is connected respectively to the source electrode of third PMOS tube P3, the source electrode of the 4th PMOS tube P4, the 11st PMOS tube
The source electrode of P11；The drain electrode of the second PMOS tube P2 is connected respectively to the source electrode and the tenth PMOS tube P10 of the 9th PMOS tube P9
Source electrode；The reference current source IREFOne end of connection resistance R1 is connected respectively to the grid and the 11st of the tenth NMOS tube N10
The grid of NMOS tube N11；The grid of the first NMOS tube N1 is connected respectively to the grid of the 4th NMOS tube N4, the 5th NMOS tube
The grid of the grid of N5 and the 6th NMOS tube N6；The grid of the third PMOS tube P3 is connected respectively to the grid of the 4th PMOS tube P4
Pole, the drain electrode of the 7th PMOS tube P7 and resistance R2 one end；The other end of the resistance R2 is connected respectively to the tenth NMOS tube N10
Drain electrode, the grid of the 7th PMOS tube P7 and the grid of the 8th PMOS tube P8；The drain electrode of the third PMOS tube P3 is connected to
The drain electrode of the source electrode of seven PMOS tube P7, the 4th PMOS tube P4 is connected to the source electrode of the 8th PMOS tube P8；8th PMOS
The drain electrode of pipe P8 is connected respectively to the drain electrode of the 11st NMOS tube N11, the grid of the 11st PMOS tube P11；9th PMOS
The drain electrode of pipe P9 is connected respectively to drain electrode and the source electrode of the tenth NMOS tube N10 of the 4th NMOS tube N4；The tenth PMOS tube P10
Drain electrode be connected respectively to the 5th NMOS tube N5 drain electrode and the 11st NMOS tube N11 source electrode；The 11st PMOS tube P11
Drain electrode be connected to the drain electrode of the 6th NMOS tube N6 and as voltage output end Vout, the grid conduct of the 9th PMOS tube P9
Voltage input end Vin, the grid of the tenth PMOS tube P10 is as voltage input end Vip；The source of 4th NMOS tube N4 simultaneously
Pole, the source electrode of the 5th NMOS tube N5, the 6th NMOS tube N6 source grounding.
2. wide input range high cmrr operation transconductance amplifier according to claim 1, which is characterized in that described
The size of first PMOS tube P1 and the second PMOS tube P2 are mutually matched, and size ratio is 1:M+1.
3. wide input range high cmrr operation transconductance amplifier according to claim 1, which is characterized in that described
The size of 5th PMOS tube P5 and the 6th PMOS tube P6 are mutually matched, and size ratio is 1:1.
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| CN201920586088.8U CN209692711U (en) | 2019-04-26 | 2019-04-26 | A kind of wide input range high cmrr operation transconductance amplifier |
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| CN201920586088.8U CN209692711U (en) | 2019-04-26 | 2019-04-26 | A kind of wide input range high cmrr operation transconductance amplifier |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110011627A (en) * | 2019-04-26 | 2019-07-12 | 苏州大学 | A kind of wide input range high cmrr operation transconductance amplifier |
| CN111721986A (en) * | 2020-05-21 | 2020-09-29 | 广东省大湾区集成电路与***应用研究院 | Wide input common mode voltage range current detection amplifier circuit |
| CN113341212A (en) * | 2021-06-05 | 2021-09-03 | 晶通微电子(南京)有限公司 | Differential voltage detection circuit with wide voltage input range |
-
2019
- 2019-04-26 CN CN201920586088.8U patent/CN209692711U/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110011627A (en) * | 2019-04-26 | 2019-07-12 | 苏州大学 | A kind of wide input range high cmrr operation transconductance amplifier |
| CN111721986A (en) * | 2020-05-21 | 2020-09-29 | 广东省大湾区集成电路与***应用研究院 | Wide input common mode voltage range current detection amplifier circuit |
| CN111721986B (en) * | 2020-05-21 | 2022-05-20 | 广东省大湾区集成电路与***应用研究院 | Wide input common mode voltage range current detection amplifier circuit |
| CN113341212A (en) * | 2021-06-05 | 2021-09-03 | 晶通微电子(南京)有限公司 | Differential voltage detection circuit with wide voltage input range |
| CN113341212B (en) * | 2021-06-05 | 2022-08-02 | 晶通微电子(南京)有限公司 | Differential voltage detection circuit with wide voltage input range |
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