CN209591533U - A kind of NOR Flash test macro based on FPGA - Google Patents
A kind of NOR Flash test macro based on FPGA Download PDFInfo
- Publication number
- CN209591533U CN209591533U CN201920199316.6U CN201920199316U CN209591533U CN 209591533 U CN209591533 U CN 209591533U CN 201920199316 U CN201920199316 U CN 201920199316U CN 209591533 U CN209591533 U CN 209591533U
- Authority
- CN
- China
- Prior art keywords
- flash
- fpga
- flash storage
- fpga chip
- module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 54
- 238000003860 storage Methods 0.000 claims abstract description 166
- 230000032683 aging Effects 0.000 claims abstract description 13
- 238000000465 moulding Methods 0.000 claims 1
- 238000005516 engineering process Methods 0.000 abstract description 3
- 230000014759 maintenance of location Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000006399 behavior Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 238000004804 winding Methods 0.000 description 1
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The utility model relates to flash memory technology fields, disclose a kind of NOR Flash test macro based on FPGA, the base plate including FPGA master control borad and in ageing oven, and base plate is equipped with NOR flash storage, and FPGA master control borad is equipped with fpga chip；Fpga chip is equipped with the control terminal for gating NOR flash storage, connect with the chip selection signal end of NOR flash storage；Fpga chip is additionally provided with the data signal end for reading the data in NOR flash storage, it connect with the data signal end of NOR flash storage, make it possible to read data current in NOR flash storage by fpga chip, and it is compared with the primary data in memory, to identify data holding ability of NOR flash storage under conditions of high/low temperature, the test to Nor flash storage is realized.
Description
Technical field
The utility model relates to flash memory technology fields, more particularly to a kind of NOR Flash test macro based on FPGA.
Background technique
With the development of science and technology and the building of information-intensive society, the storage and processing of data become in daily life
It is more and more important；Flash memory (Flash Memory) is used as a kind of nonvolatile memory, and data will not lose when power is off,
Thus gradually have received widespread attention.
Flash storage mainly includes Nor flash storage and NAND flash storage two major classes.Nor Flash
Memory can not only be wiped as a kind of electrically erasable programmable read-only memory in the case where not removing storage chip
It removes and programming operation, also has many advantages, such as non-volatile, solid-state, small in size, light-weight, anti-vibration, high-performance and low energy consumption,
Thus Nor flash storage is in every field such as computer hardware, Industry Control, hardware instrument, household electrical appliance, smart phones
Extensive utilization is obtained.But the present inventor is in implementing the present invention, it may, at least there is following skill in the discovery prior art
Art problem:
Currently, the test object being generally directed to is NAND flash storage in flash storage test, still, and
It is not directed to the test to Nor flash storage, leads to the reliability for being difficult to ensure Nor flash storage.
Utility model content
The utility model embodiment provides a kind of NOR Flash test macro based on FPGA, to solve in existing Flash
In memory test, the technical issues of being not directed to the test to Nor flash storage, to ensure Nor flash storage
Stability and reliability.
In order to solve the above-mentioned technical problem, the utility model provides a kind of NOR Flash test macro based on FPGA, packet
FPGA master control borad and the base plate in ageing oven are included, the base plate is equipped with NOR flash storage, the FPGA master
Control the fpga chip that plate is equipped with the data holding ability of the NOR flash storage for identification；The fpga chip is set
There is the control terminal for gating the NOR flash storage, the control terminal of the fpga chip and the NOR Flash are stored
The chip selection signal end of device connects；The fpga chip is additionally provided with the number for reading the data in the NOR flash storage
According to signal end, the data signal end of the fpga chip is connect with the data signal end of the NOR flash storage.
Preferably, the NOR flash storage is multiple；The control terminal of the fpga chip respectively with it is each
The chip selection signal end of the NOR flash storage connects；The data signal end of the fpga chip respectively with each NOR
The data signal end of flash storage connects.
Preferably, decoder is additionally provided on the FPGA master control borad, the fpga chip includes NOR Flash
Control module,
Control terminal of the control terminal of the sub- control module of NOR Flash as the fpga chip；The NOR Flash
The control terminal of sub- control module is connect with the input terminal of the decoder, the output end of the decoder respectively with it is each described
The chip selection signal end of NOR flash storage connects；
Digital signal end of the data signal end of the sub- control module of NOR Flash as the fpga chip；It is described
The data signal end of the sub- control module of NOR Flash is connect with the data signal end of each NOR flash storage respectively；
The clock signal terminal of the sub- control module of NOR Flash respectively with each NOR flash storage when
The connection of clock signal end.
Preferably, the sub- control module of NOR Flash is multiple；Correspondingly, the decoder is multiple, and
The sub- control module of NOR Flash is one-to-one relationship with the decoder.
Preferably, the decoder is 4-16 decoder.
Preferably, it is additionally provided on the FPGA master control borad for generating gating NOR Flash work order and reading
The input module for taking NOR Flash data to instruct, the first input end of the output end of the input module and the fpga chip
Connection.
Preferably, the display mould for showing NOR Flash test result is additionally provided on the FPGA master control borad
Block, the input terminal of the display module are connect with the first output end of the fpga chip.
Preferably, be additionally provided on the FPGA master control borad for by test program burning in the fpga chip
Configuration module, the output end of the configuration module connect with the second input terminal of the fpga chip.
Preferably, power module, the output end of the power module and institute are additionally provided on the FPGA master control borad
State the power end connection of fpga chip.
Preferably, be additionally provided on the FPGA master control borad for for the fpga chip provide clock signal when
Clock module, the output end of the clock module are connect with the third input terminal of the fpga chip.
The utility model provides a kind of NOR Flash test macro based on FPGA, including FPGA master control borad and is set to old
Change the base plate in case, the base plate is equipped with NOR flash storage, and the FPGA master control borad is equipped with institute for identification
State the fpga chip of the data holding ability of NOR flash storage；The fpga chip is equipped with for gating the NOR
The chip selection signal end of the control terminal of flash storage, the control terminal of the fpga chip and the NOR flash storage connects
It connects；The fpga chip is additionally provided with the data signal end for reading the data in the NOR flash storage, the FPGA
The data signal end of chip is connect with the data signal end of the NOR flash storage.By the way that the NOR Flash will be equipped with
The base plate of memory is placed in the ageing oven, and deposits the control terminal of the fpga chip with the NOR Flash
The chip selection signal end of reservoir connects, and enables the fpga chip to gate the NOR flash storage, and described in control
NOR flash storage works；And data signal end and the NOR flash storage by making the fpga chip
Data signal end connection, enable the fpga chip to read data current in the NOR flash storage, and will
Current data are compared with the primary data in the NOR flash storage in the NOR flash storage read
Compared with so that data holding ability of NOR flash storage under conditions of high/low temperature is identified, to verify Nor
Flash storage stability and reliability, and then the test to Nor flash storage is realized, therefore ensure that Nor
The stability and reliability of flash storage.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of the NOR Flash test macro provided by the embodiment of the utility model based on FPGA；
Fig. 2 is the sub- control module of NOR Flash provided by the embodiment of the utility model, decoder and NOR Flash storage
The connection schematic diagram of device；
Fig. 3 is the structural schematic diagram of FPGA master control borad provided by the embodiment of the utility model.
Wherein, 1, FPGA master control borad；11, fpga chip；111, the sub- control module of NOR Flash；12, decoder；13, defeated
Enter module；14, display module；15, configuration module；16, power module；17, clock module；2, base plate；21,NOR Flash
Memory；3, ageing oven.
Specific embodiment
The following will be combined with the drawings in the embodiments of the present invention, carries out the technical scheme in the embodiment of the utility model
Clearly and completely describe, it is clear that the described embodiments are only a part of the embodiments of the utility model, rather than whole
Embodiment.Based on the embodiments of the present invention, those of ordinary skill in the art are without creative efforts
Every other embodiment obtained, fall within the protection scope of the utility model.
As shown in Figure 1, the utility model embodiment provides a kind of NOR Flash test macro based on FPGA, including
FPGA master control borad 1 and the base plate 2 in ageing oven 3, the base plate 2 is equipped with NOR flash storage 21, described
FPGA master control borad 1 is equipped with the fpga chip 11 of the data holding ability of the NOR flash storage for identification；It is described
Fpga chip 11 is equipped with control terminal for gating the NOR flash storage 21, the control terminal of the fpga chip 11 with
The chip selection signal end of the NOR flash storage 21 connects；The fpga chip 11 is additionally provided with for reading the NOR
The data signal end of data in flash storage 21, the data signal end of the fpga chip 11 are deposited with the NOR Flash
The data signal end of reservoir 21 connects.
In the utility model embodiment, by the way that the base plate 2 for being equipped with the NOR flash storage 21 is placed in
In the ageing oven 3, and connect the control terminal of the fpga chip 11 and the chip selection signal end of the NOR flash storage 21
It connects, the fpga chip 11 is enabled to gate the NOR flash storage 21, to control the NOR flash storage
21 work, and the NOR flash storage 21 as described in control carries out reading circulation and writes circulation；And by making the fpga chip
11 data signal end is connect with the data signal end of the NOR flash storage 21, enables the fpga chip 11
Read data current in the NOR flash storage 21；The fpga chip 11 is reading the NOR flash storage
It, will be at the beginning of the current position bit of the NOR flash storage 21 and the NOR flash storage 21 in 21 after current data
The position bit when the beginning is compared one by one, if every a bit all the same, the fpga chip 11 identifies the NOR Flash
The data holding ability of memory 21 is good；If any bit different, the fpga chip 11 identifies the NOR Flash
The data holding ability of memory 21 is poor, identifies the NOR flash storage 21 under high/low temperature condition to realize
Data holding ability to verify 21 stability of Nor flash storage and reliability, and then is realized and is stored to Nor Flash
The test of device 21, therefore ensure that the stability and reliability of Nor flash storage 21.Wherein, it should be noted that described
Communication between fpga chip 11 and the Nor flash storage 21 follows SPI (Serial Peripheral
Interface, Serial Peripheral Interface (SPI)) agreement.
In addition, it should be noted that, it is set to the device on the FPGA master control borad 1, such as fpga chip 11, in height
When working under the conditions of temperature, it is easily damaged；Therefore, in order to guarantee the reliability of the NOR Flash test macro based on FPGA,
To guarantee being normally carried out for test, base plate 2 described in the present embodiment is set in the ageing oven 3, and the FPGA master control borad 1
It is then set to outside the ageing oven 3, and the FPGA master control borad 1 is connect by FPC winding displacement with the base plate 2.
In the utility model embodiment, in order to improve the efficiency of test, and testing cost is reduced, described in the present embodiment
NOR flash storage 21 is multiple；The control terminal of the fpga chip 11 respectively with each NOR flash storage 21
Chip selection signal end connection；The data signal end of the fpga chip 11 respectively with each NOR flash storage 21
Data signal end connection.By the way that multiple NOR flash storages 21 are arranged on the base plate 2, and make the FPGA
The control terminal of chip 11 is connect with the chip selection signal end of each NOR flash storage 21 respectively, the fpga chip 11
Data signal end connect respectively with the data signal end of each NOR flash storage 21, thus pass through the FPGA
Multiple NOR flash storages 21 are tested in the realization of chip 11, and then improve the efficiency of test, and reduce survey
Try cost.
As shown in Fig. 2, in a preferred embodiment, being carried out to realize to multiple NOR flash storages 21
It tests, decoder 12 is additionally provided on the FPGA master control borad 1, the fpga chip 11 includes the sub- control module of NOR Flash
111,
The control terminal of the fpga chip is connect with the chip selection signal end of the NOR flash storage, the FPGA core
The data signal end of piece is connect with the data signal end of the NOR flash storage, specifically:
Control terminal of the control terminal of the sub- control module 111 of NOR Flash as the fpga chip 11；The NOR
The control terminal of the sub- control module 111 of Flash is connect with the input terminal of the decoder 12, the output end difference of the decoder 12
It is connect with the chip selection signal end of each NOR flash storage 21；
Digital signal end of the data signal end of the sub- control module 111 of NOR Flash as the fpga chip 11；
The data signal end of the sub- control module 111 of NOR Flash is believed with the data of each NOR flash storage 21 respectively
Number end connection；
The clock signal terminal of the sub- control module 111 of NOR Flash respectively with each NOR flash storage 21
Clock signal terminal connection.
In the utility model embodiment, by translating the control terminal of the sub- control module 111 of the NOR Flash with described
The input terminal connection of code device 12, and make the output end of the decoder 12 respectively with each NOR flash storage 21
The connection of chip selection signal end, enables the sub- control module 111 of the NOR Flash successively to gate each NOR Flash and deposits
Reservoir 21, and then realize and successively control each NOR flash storage 21；By making NOR Flash control mould
The data signal end of block 111 is connect with the data signal end of each NOR flash storage 21 respectively, so that the NOR
The sub- control module 111 of Flash is after gating a NOR flash storage 21, the sub- control module 111 of NOR Flash
Specific DI data can be sent to the NOR flash storage 21 that is gated so that the NOR flash storage 21 into
Data in row read-write circulate operation or the reading NOR flash storage 21.Wherein, it should be noted that synchronization
Only one described NOR flash storage 21 is in running order；Therefore, when the sub- control module 111 of the NOR Flash is selected
Lead to the NOR flash storage 21, and controls the NOR flash storage 21 and be written and read circulation behaviour
After making or reading the data in a NOR flash storage 21, the sub- control module 111 of NOR Flash is just selected
Lead to next NOR flash storage 21, and controls next NOR flash storage 21 and be written and read circulate operation or reading
Next sub- control module 111 of the NOR Flash.It should be understood that NOR Flash controls mould in synchronization
One NOR flash storage 21 of block 111 gatings, and only the NOR flash storage 21 gated into
Row operation, the NOR flash storage 21 as described in control are written and read NOR flash storage as described in the operation or reading of circulation
The operation of data in 21.In addition, by make the clock signal terminal of the sub- control module 111 of the NOR Flash respectively with it is each
The clock signal terminal of the NOR flash storage 21 connects, enable the sub- control module 111 of the NOR Flash by when
Clock signal is sent to the NOR flash storage 21, to guarantee the normal work of the NOR flash storage 21.
In addition, by the way that the decoder 12 is arranged in the present embodiment, enable the sub- control module 111 of the NOR Flash
Enough multiple institutes are controlled using less (General Purpose Input Output, the universal input/output) port GPIO
NOR flash storage 21 is stated, the GPIO port of the sub- control module 111 of the NOR Flash is dramatically saved, is realized pair
The efficient utilization of the GPIO port resource of the sub- control module 111 of NOR Flash, and ensuring can be by the FPGA core
Piece 11 realizes the test to multiple NOR flash storages 21.
In the utility model embodiment, the type of the decoder 12 can be arranged according to actual operation requirements；It is preferred that
Ground, decoder 12 described in the present embodiment are 4-16 decoder.
As shown in Fig. 2, when the decoder 12 is the 4-16 decoder, the sub- control module of NOR Flash
Control terminal is connect with the input terminal of the decoder, and the output end of the decoder is stored with each NOR Flash respectively
The chip selection signal end of device connects, the data signal end of the sub- control module of NOR Flash respectively with each NOR Flash
The data signal end of memory connects, the clock signal terminal of the sub- control module of NOR Flash respectively with each NOR
The clock signal terminal of flash storage connects, specific manifestation are as follows: the control terminal of the sub- control module 111 of NOR Flash
GPIO4-GPIO7 is connect with the input terminal of the 4-16 decoder respectively, and output end CE1-CE16 points of the 4-16 decoder
It is not connect with the chip selection signal end CE ' of each NOR flash storage 21, the sub- control module 111 of NOR Flash
Clock signal terminal GPIO1 is connect with the clock signal terminal SCLK of each NOR flash storage 21 respectively, the NOR
The data signal output GPIO2 of the sub- control module 111 of Flash data with each NOR flash storage 21 respectively
Signal input part DI connection, the data signal input GPIO3 of the sub- control module 111 of NOR Flash respectively with each institute
State the data signal output DO connection of NOR flash storage 21.It is translated by setting the 4-16 for the decoder 13
Code device, enabling the sub- control module 111 of the NOR Flash that 4 GPIO ports are used only can be achieved with controlling 16 simultaneously
The NOR flash storage 21, to guarantee to measure multiple NOR flash storages 21.
In the utility model embodiment, the quantity of the sub- control module 111 of NOR Flash can be according to actual use
It is required that setting.In the present embodiment, large batch of NOR flash storage is tested in order to realize, NOR Flash
Control module 111 is multiple；Correspondingly, the decoder 13 is multiple, and the sub- control module 111 of the NOR Flash and institute
Decoder 13 is stated to be one-to-one relationship.By the way that multiple sub- control modules 111 of NOR Flash are arranged, and make each institute
It states the sub- control module 111 of NOR Flash to match with a decoder 13, so that each NOR Flash control
Module 111 can test multiple NOR flash storages 21 simultaneously, so that can be real by the FPGA master control borad
Now large batch of NOR flash storage is tested, thereby, it is ensured that can be improved the efficiency of test, and reduce test at
This.In addition, it should be noted that, multiple sub- control modules 111 of the NOR Flash concurrently control corresponding thereto multiple
NOR flash storage 21.
As shown in figure 3, in order to improve the convenience that the NOR Flash test macro based on FPGA uses, this implementation
It is additionally provided on FPGA master control borad 1 described in example and refers to for generating gating NOR Flash work order and reading NOR Flash data
The input module 13 of order, the output end of the input module 13 are connect with the first input end of the fpga chip 11.By setting
The input module 13 is set, tester is sent by the input module 13 to the fpga chip 11 and is gated
NOR Flash work order, so that the fpga chip can gate the NOR flash storage, to control the NOR
Flash storage works；And it can be sent by the input module 13 to the fpga chip 11 and read NOR Flash
Data command, so that the fpga chip can read data current in the NOR flash storage, and working as reading
Preceding data are compared with the primary data in the NOR flash storage, to identify the NOR Flash storage
Data holding ability of device under conditions of high/low temperature, and then improve the NOR Flash test macro based on FPGA and make
Convenience.
In the utility model embodiment, the type of the input module 13 can be according to actual use situation setting, only
It need to meet and guarantee to generate gating NOR Flash work order by the input module 13 and read NOR Flash data
Instruction, and it is sent to the fpga chip 11.Preferably, input module 13 described in the present embodiment is key module, institute
Stating key module includes multiple keys；Wherein, each key is for generating different instructions.In a specific embodiment, may be used
To be arranged one for generating the first key of gating NOR Flash work order, one is read NOR Flash number for generating
According to the second key of instruction；When user presses first key, triggering generates gating NOR Flash work order, described
The gating NOR Flash work order is sent to the fpga chip 11 by the first key, so that 11 energy of the fpga chip
The NOR flash storage 21 is enough gated, and controls the NOR flash storage 21 and works, the NOR as described in control
The work of flash storage 21 is under read-write circulation；When user presses second key, triggering, which generates, reads NOR Flash
Data command, reading NOR Flash data instruction is sent to the fpga chip 11 by second key, so that described
Fpga chip 11 reads data current in the NOR Flash memory 21, and with it is initial in NOR flash storage 21
Data are compared, to identify data holding ability of the NOR flash storage 21 under high/low temperature condition.
In the utility model embodiment, test result is known for the ease of tester, FPGA described in the present embodiment
Be additionally provided with the display module 14 for showing NOR Flash test result on master control borad 1, the input terminal of the display module 14 with
First output end of the fpga chip 11 connects.By the way that the display module 14 is arranged, and make the defeated of the display module 14
Enter end to connect with the first output end of the fpga chip 11, the NOR that the fpga chip 11 will be recognized
The result of data holding ability of the flash storage 21 under high/low temperature condition is sent to the display module 14, by described aobvious
Show that module 14 is shown.In addition, the display module 14 can be also used for showing the NOR Flash test macro based on FPGA
Working condition, such as open state and off-mode；It can certainly show the working condition of NOR flash storage 21, In
This, which does not do, more repeats.
In the utility model embodiment, the type of the display module 14 can be according to actual use situation setting, only
It need to meet and guarantee to show test result by the display module 14.Preferably, mould is shown described in the present embodiment
Block 14 is LED light.Specifically, the LED light exists according to the NOR flash storage 21 that the fpga chip 11 recognizes
The result of data holding ability under high/low temperature condition shows different light, to realize the display to test result.
As shown in figure 3, be additionally provided on FPGA master control borad described in the present embodiment 1 for by test program burning in described
Second input terminal of the configuration module 15 in fpga chip 11, the output end of the configuration module 15 and the fpga chip 11 connects
It connects.By the way that the configuration module 15 is arranged, make it possible to firmware can be burnt to by the configuration module 15 described
In fpga chip 11, so that it is guaranteed that the test to the NOR flash storage 21 can be realized by the fpga chip 11.
Wherein, firmware is the program for testing the NOR flash storage 21.
In the utility model embodiment, in order to ensure the normal work of the NOR Flash test macro based on FPGA
Make, be additionally provided with power module 16 on FPGA master control borad described in the present embodiment 1, the output end of the power module 14 with it is described
The power end of fpga chip 11 connects.By the way that the power module 16 is arranged, and make output end and the institute of the power module 16
The power end connection for stating fpga chip 11 makes it possible to be that the fpga chip 11 provides power supply by the power module 16,
So that it is guaranteed that the normal work of the fpga chip 11.
In addition, being additionally provided on the FPGA master control borad 1 in the utility model embodiment for being the fpga chip 11
The clock module 17 of clock signal, the third input terminal company of the output end of the clock module 17 and the fpga chip 11 are provided
It connects.By the way that the clock module 17 is arranged, to generate clock signal, and make the output end and the FPGA of the clock module 17
The third input terminal of chip 11 connects, so that the clock signal can be sent to the FPGA by the clock module 17
Chip 11, to ensure the normal work of the fpga chip 11.
In the utility model embodiment, the course of work of the NOR Flash test system based on FPGA, specifically:
S1, it is powered on to the FPGA master control borad 1；
S2, by the configuration module 15, by the FPGAfirmware programming write in advance to the FPGA master control borad 1
On fpga chip 11 in；
The temperature of S3, the setting ageing oven 3, so as to be set to described on the base plate 2 in the ageing oven 3
NOR flash storage 21 works in desired high and low temperature environment；
S4, pass through the input module 13, gating NOR Flash work order is sent to the fpga chip 11, with
So that the fpga chip 11 is gated the NOR flash storage 21, and controls the NOR flash storage 21 and carry out work
Make, the NOR flash storage 21 as described in control carries out reading circulation, writes circulation；
S5, after the NOR flash storage 21 continues working the preset time, make the NOR flash storage
21 stop working；And the instruction of NOR Flash data will be read by the input module 13 and be sent to the fpga chip 11, with
So that the fpga chip 11 is read data current in the NOR flash storage 21, and in NOR flash storage 21
Primary data be compared, to identify data holding ability of the NOR flash storage 21 under high/low temperature；Most
Test result is shown by the display module 14 afterwards, completes the test to the Nor flash storage 21.
In addition, it should be noted that, after implementation steps S4, and before implementation steps S5, institute can also be passed through
State the working condition that display module 14 observes the NOR flash storage 21.
To sum up, the utility model embodiment provides a kind of NOR Flash test macro based on FPGA, including FPGA master control
Plate 1 and the base plate 2 in ageing oven 3, the base plate 2 are equipped with NOR flash storage 21, the FPGA master control borad
1 is equipped with the fpga chip 11 of the data holding ability of the NOR flash storage for identification；The fpga chip 11 is set
There are the control terminal for gating the NOR flash storage 21, the control terminal of the fpga chip 11 and the NOR Flash
The chip selection signal end of memory 21 connects；The fpga chip 11 is additionally provided with for reading in the NOR flash storage 21
Data data signal end, the data of the data signal end of the fpga chip 11 and the NOR flash storage 21 believe
Number end connection.By the way that the base plate 2 for being equipped with NOR flash storage 21 to be placed in ageing oven 3, and make the fpga chip 11
Control terminal connect with the chip selection signal end of the NOR flash storage 21, enable the fpga chip 11 to gate institute
NOR flash storage 21 is stated, is worked to control the NOR flash storage 21, circulation is such as read and writes circulation；And
By connecting the data signal end of the fpga chip 11 and the data signal end of the NOR flash storage 21, so that
The fpga chip 11 can read data current in the NOR flash storage 21, and the NOR Flash is stored
Current data are compared with the primary data in the NOR flash storage 21 in device, thus realize identify it is described
Data holding ability of the NOR flash storage 21 under high/low temperature condition, with verify 21 stability of Nor flash storage and
Reliability, and then the test to Nor flash storage 21 is realized, therefore ensure that the stabilization of Nor flash storage 21
Property and reliability.
The above is only the preferred embodiment of the utility model, it is noted that for the common skill of the art
For art personnel, without deviating from the technical principle of the utility model, several improvement and replacement can also be made, these change
It also should be regarded as the protection scope of the utility model into replacement.
Claims (10)
1. a kind of NOR Flash test macro based on FPGA, which is characterized in that including FPGA master control borad and be set in ageing oven
Base plate, the base plate is equipped with NOR flash storage, and the FPGA master control borad is equipped with the NOR for identification
The fpga chip of the data holding ability of flash storage；The fpga chip is equipped with for gating the NOR Flash storage
The control terminal of device, the control terminal of the fpga chip are connect with the chip selection signal end of the NOR flash storage；The FPGA
Chip is additionally provided with the data signal end for reading the data in the NOR flash storage, the data of the fpga chip
Signal end is connect with the data signal end of the NOR flash storage.
2. the NOR Flash test macro based on FPGA as described in claim 1, which is characterized in that the NOR Flash is deposited
Reservoir is multiple；The control terminal of the fpga chip is connect with the chip selection signal end of each NOR flash storage respectively；
The data signal end of the fpga chip is connect with the data signal end of each NOR flash storage respectively.
3. the NOR Flash test macro based on FPGA as claimed in claim 2, which is characterized in that the FPGA master control borad
On be additionally provided with decoder, the fpga chip includes the sub- control module of NOR Flash,
Control terminal of the control terminal of the sub- control module of NOR Flash as the fpga chip；The NOR Flash control
The control terminal of molding block is connect with the input terminal of the decoder, the output end of the decoder respectively with each NOR
The chip selection signal end of flash storage connects；
Data signal end of the data signal end of the sub- control module of NOR Flash as the fpga chip；The NOR
The data signal end of the sub- control module of Flash is connect with the data signal end of each NOR flash storage respectively；
The clock signal terminal of the sub- control module of NOR Flash is believed with the clock of each NOR flash storage respectively
Number end connection.
4. the NOR Flash test macro based on FPGA as claimed in claim 3, which is characterized in that NOR Flash
Control module is multiple；Correspondingly, the decoder is multiple, and the sub- control module of NOR Flash and the decoder
It is one-to-one relationship.
5. the NOR Flash test macro based on FPGA as described in claim 3 or 4, which is characterized in that the decoder is
4-16 decoder.
6. the NOR Flash test macro according to any one of claims 1-4 based on FPGA, which is characterized in that described
It is additionally provided on FPGA master control borad for generating gating NOR Flash work order and reading the input of NOR Flash data instruction
Module, the output end of the input module are connect with the first input end of the fpga chip.
7. the NOR Flash test macro according to any one of claims 1-4 based on FPGA, which is characterized in that described
Be additionally provided with the display module for showing NOR Flash test result on FPGA master control borad, the input terminal of the display module with
First output end of the fpga chip connects.
8. the NOR Flash test macro according to any one of claims 1-4 based on FPGA, which is characterized in that described
It is additionally provided on FPGA master control borad for the configuration module by test program burning in the fpga chip, the configuration module
Output end is connect with the second input terminal of the fpga chip.
9. the NOR Flash test macro according to any one of claims 1-4 based on FPGA, which is characterized in that described
Power module is additionally provided on FPGA master control borad, the output end of the power module is connect with the power end of the fpga chip.
10. the NOR Flash test macro according to any one of claims 1-4 based on FPGA, which is characterized in that described
It is additionally provided on FPGA master control borad for providing the clock module of clock signal, the output of the clock module for the fpga chip
End is connect with the third input terminal of the fpga chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920199316.6U CN209591533U (en) | 2019-02-14 | 2019-02-14 | A kind of NOR Flash test macro based on FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920199316.6U CN209591533U (en) | 2019-02-14 | 2019-02-14 | A kind of NOR Flash test macro based on FPGA |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209591533U true CN209591533U (en) | 2019-11-05 |
Family
ID=68355496
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201920199316.6U Expired - Fee Related CN209591533U (en) | 2019-02-14 | 2019-02-14 | A kind of NOR Flash test macro based on FPGA |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN209591533U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112582015A (en) * | 2020-12-30 | 2021-03-30 | 普冉半导体(上海)股份有限公司 | Method and system for NOR Flash reliability test |
-
2019
- 2019-02-14 CN CN201920199316.6U patent/CN209591533U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112582015A (en) * | 2020-12-30 | 2021-03-30 | 普冉半导体(上海)股份有限公司 | Method and system for NOR Flash reliability test |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102446141B (en) | Device and method for realizing write protection control | |
| CN103365689A (en) | Singlechip parallel burning method | |
| CN101996121A (en) | Universal serial bus (USB) port testing device and testing method | |
| CN107645310B (en) | The data transmission device and data transmission method of breaker controller | |
| CN102902626B (en) | Block management method, Memory Controller and memorizer memory devices | |
| CN209591533U (en) | A kind of NOR Flash test macro based on FPGA | |
| CN110619914A (en) | Mass production method for solid state disk with PCIe interface mass production device | |
| CN111833797A (en) | Time sequence control plate, driving device and display device | |
| CN102169442B (en) | Method, equipment, device and system for performing system boot by using USB (universal serial bus) device | |
| CN104158709A (en) | Optical module identification method and port extender | |
| CN109739783A (en) | Read and/or write simultaneously the device of more optical module EEPROM | |
| CN110459260A (en) | Automatic test switching device, method and system | |
| CN105955919A (en) | Implementation method of reading-writing NANDFlash by multiple MCUs based on FPGA (Field Programmable Gate Array) | |
| CN106205726B (en) | Quick test technology for EEPROM memory | |
| CN105334920B (en) | A kind of PCIE universal signal power board | |
| CN103383663A (en) | System operating method, memory controller and memory | |
| CN108170623A (en) | A kind of USB switching circuits and switching system | |
| CN109817273B (en) | NAND performance test method and system | |
| CN116346117B (en) | IIC port expansion circuit, transmission method, transmission system, computer equipment and medium | |
| CN208954104U (en) | Multichannel SIM card read-write equipment | |
| CN106547716B (en) | A kind of expansion bus configuration system and method towards low pin number | |
| CN107577574B (en) | Debugging switching circuit and debugging circuit board | |
| CN205051829U (en) | Intelligence PON terminal with EPONGPON switches ability | |
| CN106681653B (en) | Memory erasing method, memorizer control circuit unit and memory storage apparatus | |
| CN111710357B (en) | MTP unit read-write control circuit of MCU |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20191105 |