CN102446141B - Device and method for realizing write protection control - Google Patents
Device and method for realizing write protection control Download PDFInfo
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- CN102446141B CN102446141B CN201110272109.7A CN201110272109A CN102446141B CN 102446141 B CN102446141 B CN 102446141B CN 201110272109 A CN201110272109 A CN 201110272109A CN 102446141 B CN102446141 B CN 102446141B
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Abstract
The invention provides a device and a method for realizing write protection control. In the device and the method provided in the invention, the CPU (Central Processing Unit) of a local host, apart from being capable of generating a write instruction which can be transferred to a nonvolatile memory via an I2C (Inter-Integrated Circuit) bus to realize a write-in operation according to a write command from a remote host, is also capable of generating an on instruction which can be transferred to a processor prior to the write instruction via the I2C bus and an off instruction which can be transferred to the processor after the write instruction via the I2C bus according to the write command from the remote host; and the processor of a pluggable device is capable of obtaining the off instruction and the on instruction from the I2C bus and thereby controlling the nonvolatile memory to be powered off and on; therefore, the device and the method provided in the invention are capable of realizing the write protection control on the nonvolatile memory by means of the existing I2C bus without adding any signal wire to an interface between the local host and the pluggable device.
Description
Technical field
The present invention relates to storer write-protect technology, particularly a kind of for realizing the device, a kind of for realizing the method for write-protect control of write-protect control.
Background technology
In existing electronic equipment, conventionally can be provided with can be for some slots that can plug device grafting.Can plug power supply can utilize and can plug power supply and realize power supply by pegging graft at any slot.
For the ease of the plugged power supply of pegging graft in distinct electronic apparatuses is managed, can be by long-range sequence number and other information that can plug power supply of reading of the distance host of data center.For the plugged power supply that there is no sequence number, can also be by the distance host of data center to plugging the long-range sequence number of its distribution and other information that user needs of being written as of power supply.Correspondingly, just need in power supply can be plugged, set up E
2pROM (Electrically Erasable Programmable Read-Only Memory, EEPROM (Electrically Erasable Programmable Read Only Memo)) realizes the read-write of sequence number.
Fig. 1 is for realizing sequence number to plugging power supply and a kind of structural representation of other Card read/writes in prior art.As shown in Figure 1, electronic equipment is as local host (" this locality " as herein described is for " long-range ") and have CPU, can plug power supply and comprise E
2pROM.
CPU can carry out telecommunication with distance host, in order to receive for E from distance host
2the write order of PROM and sequence number and receive for E from distance host
2the read command of PROM is also returned from E to distance host
2the sequence number that PROM reads.
CPU also can be used as I
2c main device with as I
2c is from the E of device
2pROM passes through I
2c bus is carried out alternately, in order to E
2pROM sends and meets I
2the write command of C specification and sequence number and to E
2pROM sends and meets I
2c specification read instruction and from E
2pROM receives the sequence number reading.
In addition, can plug and in power supply, also comprise that for can plug the MCU that carries out corresponding control operation in power supply (Micro Control Unit, micro-control unit, be called single-chip microcomputer again), CPU can be used as I
2c main device with as I
2c passes through I from the MCU of device
2c bus is carried out alternately, in order to realize control and/or the monitoring to MCU.
Based on structure as shown in Figure 1, in order to ensure distance host to plugging the read-write of sequence number of power supply, can be by E
2pROM suspends or ground connection for write-protected WP pin, to close E
2the writing protection function of PROM.But like this, just make not have the E of writing protection function
2the sequence number of depositing in PROM is easily mistakenly rewritten, even loses.
Fig. 2 is for realizing sequence number to plugging power supply and the another kind of structural representation of other Card read/writes and write-protect control in prior art.Than structure as shown in Figure 1, in structure as shown in Figure 2 by E
2pROM is introduced into local host one side and is controlled by the CPU that is arranged at local host for write-protected WP pin.Only at needs according to the write request of distance host to E
2in PROM, when writing sequence number, CPU just can draw high WP pin for high level, to close E
2the writing protection function of PROM, and in during not needing writing sequence number, CPU all can drag down WP pin remain low level, to open E
2the writing protection function of PROM.
Based on structure as shown in Figure 2, although can either guarantee that distance host, to plugging the read-write of sequence number of power supply, can utilize again writing protection function to avoid E
2the sequence number of depositing in PROM is easily mistakenly rewritten, even loses, but, this scheme must increase for controlling a signal wire of WP pin can plug between power supply and local host in the interface at slot place, this will cause this scheme realization must taking amendment interface terminal assignment as prerequisite, can cause the interface circuit layout of local host need corresponding modify and need to carry out corresponding modify to plugging the interface of power supply and the terminal assignment of amendment interface is inevitable, thereby just increase the difficulty that realizes of this scheme.
Summary of the invention
In view of this, the invention provides a kind ofly for realizing the device, a kind of for realizing the method for write-protect control of write-protect control, can in the case of avoiding revising the terminal assignment of interface, realize write-protect control.
Provided by the invention a kind of for realizing the device of write-protect control, comprising:
Be arranged at the CPU of local host, receive and carry the write order of writing data from a distance host by telecommunication, and the described write order of foundation is at I
2in C bus as I
2c main device with the time delay interval order of being scheduled to send out code, the write command, open command that carry write data be to the plugged device that is plugged in described local host;
Be arranged at the described nonvolatile memory that can plug device, as I
2c is from device from I
2c bus receives described write command, and realizes the write operation to write data according to described write command;
Be arranged at the described processor that can plug device, as I
2c is from device from I
2c bus receives described out code and described open command, and the write-protect pin of described nonvolatile memory is set to the level state of closing the level state of writing protection function, according to described open command, the write-protect pin of described nonvolatile memory being set to unlatching writing protection function according to described out code.
Described processor comprises:
Down trigger logic, from I
2c bus identifies to trigger after described out code interrupts and state that a register cuts out described in being set to represent and from I
2c bus identifies to trigger after described open command interrupts and described register is set to represent the state of described unlatching;
Interrupt handling logic; after interruption is triggered, inquire about described register, and in the time of the state of closing described in described register is expression, carry out the operation that the write-protect pin of described nonvolatile memory is set to the operation of the level state of closing writing protection function, execution is set to the write-protect pin of described nonvolatile memory the level state of unlatching writing protection function in the time that described register is the state of the described unlatching of expression.
The original state that described register records after power-up initializing is the state that represents described unlatching.
Described processor further detect described can plug device whether in place, also further ignore described out code time not in place at the described device that plugs;
Or whether described processor further detects the described device that can plug and is enabled, also further ignores described out code when device is not enabled described plug;
Or, described processor further detect described can plug device whether in place and whether be enabled, also further not in place and/or ignore described out code while not being enabled at the described device that plugs.
Write data comprise the described identification code that can plug device, and the described device that plugs is for can plug power supply, and described nonvolatile memory is E
2pROM, described processor is MCU.
Provided by the invention a kind of for realizing the method for write-protect control, comprising:
The CPU that is arranged at local host is received and carries the write order of writing data from a distance host by telecommunication, and the described write order of foundation is at I
2in C bus as I
2c main device with the time delay interval order of being scheduled to send out code, the write command, open command that carry write data be to the plugged device that is plugged in described local host;
The method also comprises the corresponding following steps of described out code, described write command, described open command that send with order:
Be arranged at the described processor that can plug device as I
2c is from device from I
2c bus receives described out code, and according to described out code, the write-protect pin of described nonvolatile memory is set to the level state of closing writing protection function;
Be arranged at the described nonvolatile memory that can plug device as I
2c is from device from I
2c bus receives described write command, and realizes the write operation to write data according to described write command;
Described processor is as I
2c is from device from I
2c bus receives described open command, and the write-protect pin of described nonvolatile memory is set to the level state of opening writing protection function according to described open command.
According to described out code, the write-protect pin of described nonvolatile memory being set to the level state of closing writing protection function comprises: described processor is from I
2c bus identify trigger after described out code interrupt and described processor in the register state of closing described in being set to represent, and described processor after interrupting being triggered, to inquire described register be the state of closing described in representing, and carry out the operation that the write-protect pin of described nonvolatile memory is set to the level state of closing writing protection function;
According to described open command, the write-protect pin of described nonvolatile memory is set to and opens the level state of writing protection function and comprise: described processor is from I
2c bus identifies to trigger after described open command interrupts and described register is set to represent the state of described unlatching, and described processor after interrupting being triggered, to inquire described register be the state that represents described unlatching, and carry out the operation that the write-protect pin of described nonvolatile memory is set to the level state of opening writing protection function.
It is the state that represents described unlatching that the method arranges the original state that described register records after power-up initializing.
The method further comprises:
Described in detecting, described processor can plug device whether in place and ignore described out code time not in place at the described device that plugs;
Or, described in described processor detects, can plug whether device is enabled and further ignore described out code when plugging device and not being enabled described;
Or, described in described processor detects, can plug device whether in place and whether be enabled and not in place and/or ignore described out code while not being enabled at the described device that plugs.
Write data are the described identification code that can plug device, and the described device that plugs is for can plug power supply, and described nonvolatile memory is E
2pROM, described processor is MCU.
As above visible, in the present invention, the CPU of local host can be at I except producing according to the write order from distance host
2in C bus, be passed to nonvolatile memory and realize outside the write command of write operation, can also produce according to the write order from distance host can be at I
2in C bus prior to write command be passed to processor out code and after be passed to the open command of processor in write command, the processor that can plug device can be from I
2c bus is obtained out code and open command and is controlled closing and opening of nonvolatile memory with this, thereby the present invention utilizes existing I
2c bus can realize write-protect control to nonvolatile memory and without setting up any signal wire at local host and in can plugging the interface between device.
Brief description of the drawings
Fig. 1 is for realizing sequence number to plugging power supply and a kind of structural representation of other Card read/writes in prior art;
Fig. 2 is for realizing sequence number to plugging power supply and the another kind of structural representation of other Card read/writes and write-protect control in prior art;
Fig. 3 is for realizing sequence number to plugging power supply and the structural representation of other Card read/writes and write-protect control in the embodiment of the present invention;
Fig. 4 is for realizing the method flow schematic diagram of write-protect control in the embodiment of the present invention.
Embodiment
For making object of the present invention, technical scheme and advantage clearer, referring to the accompanying drawing embodiment that develops simultaneously, the present invention is described in more detail.
In embodiments of the present invention, the CPU that is arranged at local host controls the E that can plug in power supply by the level state of direct control WP pin as prior art
2the writing protection function of PROM, but first utilize existing I in interface
2c bus is to plugging power supply transmission for controlling E
2the instruction of PROM writing protection function.Meanwhile, although can plug the E in power supply
2pROM is as I
2c is articulated in I from device
2in C bus, but E
2pROM is except identifying I
2reading outside instruction and write command in C bus, does not have the ability of identifying other instructions, and therefore, CPU utilizes I
2the I that C bus is transmitted
2the address of C bus command is not E
2pROM but can plug the MCU in power supply, so, MCU is at I
2in C bus, after identifying these instructions, can control the E that can plug in power supply by the level state of controlling WP pin
2the writing protection function of PROM.
That is to say, the write-protect control realizing in the embodiment of the present invention is divided into two parts, wherein, and at local host and can plug a part between power supply based on I
2c bus realizes, the another part that can plug power supply inside still the level state control based on to WP pin realize.Just can obviously find out thus, due to local host and can plug a part between power supply based on interface in existing I
2c bus realizes, thereby sets up any signal in also just need to and can not plugging the interface between device at local host.
Fig. 3 is for realizing sequence number to plugging power supply and the structural representation of other Card read/writes and write-protect control in the embodiment of the present invention.As shown in Figure 3, be provided with CPU in local host, the plugged power supply that is plugged in local host comprises MCU and E
2pROM.
The CPU that is arranged at local host can carry out telecommunication with a distance host, in order to receive from a distance host write order that carries sequence number and other information (comprising that to write data sequence number and other information are as example the embodiment of the present invention) by telecommunication;
And SCL pin and SDA pin that CPU has are connected to I
2c bus, therefore the CPU write order that also foundation receives is at I
2in C bus as I
2c main device with the time delay interval order of being scheduled to send out code, the write command, open command that carry sequence number and other information be to the plugged power supply that is plugged in local host.Wherein, carry the I of the write command of sequence number and other information
2c bus address is still E
2the address of PROM, and the I of out code and open command
2c bus address is the address of MCU.
That is to say, wish plugging the E in power supply for distance host
2pROM carries out the situation of write operation, by relating to I in CPU
2the improvement of C bus protocol function, makes CPU not only produce and pass through I according to the write order that is received from distance host
2c bus is to E
2the write command that carries sequence number and other information that PROM transmits, also can be created in write command and pass through I before
2c bus to MCU transmit out code and after write command, pass through I
2the open command that C bus is transmitted to MCU.
E
2sCL pin and SDA pin that PROM has are connected to I
2c bus, and SCL pin and SDA pin that MCU has are connected to I
2i/O pin and E that C bus and MCU have
2the WP pin of PROM is direct-connected, thus:
First, by being arranged at the MCU that can plug power supply as I
2c is from device from I
2c bus receives described out code, and according to out code by E
2the WP pin of PROM be set to close writing protection function level state (being low level state), make E
2pROM now becomes can write state.
Then,, through a predetermined time delay interval, be arranged at the E that can plug power supply
2pROM is as I
2c is from device from I
2c bus receives and carries the write command of sequence number and other information, and realizes the write operation to sequence number and other information according to write command.
Finally, then through a predetermined time delay interval, be arranged at the MCU that can plug power supply as I
2c is from device from I
2c bus receive open command, and according to open command by E
2the WP pin of PROM be set to open writing protection function level state (being high level state), make E
2pROM now becomes can not write state under write-protect.
In practical application, MCU can and carry out E by interrupt mode based on its built-in register
2the control of the WP pin level state of PROM.Specifically, MCU inside can comprise:
Down trigger logic, from I
2c bus identifies to trigger after out code interrupts and above-mentioned register is set to represent the state of cutting out and from I
2c bus identifies to trigger after open command interrupts and above-mentioned register is set to represent the state of opening;
Interrupt handling logic, is interrupting after being triggered inquiring about above-mentioned register, and carries out E in the time that above-mentioned register is the state that represents to cut out
2the WP pin of PROM is set to the operation of the low level state of closing writing protection function, in the time that above-mentioned register is the state of expression unlatching, carries out E
2the WP pin of PROM is set to the operation of the high level state of opening writing protection function.
Wherein, the original state that above-mentioned register records after power-up initializing is the state that represents unlatching.
More reliably, MCU can also detect can plug power supply (whether being normally plugged in local host) whether in place and/or can plug power supply whether enabled (control MCU by CPU by level state and start or stop the EN pin that can plug power work and judge according to existing in interface) by CPU.Thereby:
For only detecting and can plug power supply situation whether in place, MCU can be detecting that can plug power supply ignores out code time not in place, that is, as long as it is in place to plug power supply, even if receive that out code also still keeps E
2the write-protect state of PROM;
For only detecting and can plug the situation whether power supply is enabled, MCU can ignore out code detecting when can plug power supply is not enabled, that is, be not enabled as long as can plug power supply, even if receive that out code also still keeps E
2the write-protect state of PROM;
For detect and can plug the situation that whether power supply is in place and whether be enabled simultaneously, MCU can detect that can to plug power supply in place and/or ignore out code while not being enabled again,, as long as fail to meet simultaneously, can to plug power supply in place and be enabled, even if receive that out code also still keeps E
2the write-protect state of PROM.
Adopt with upper type be because: not in place and/or while not being enabled, likely due to I when plugging power supply
2c bus is interfered and is thought by mistake be out code by MCU, thereby mistake is by E
2the writing protection function of PROM is closed and is caused E
2the sequence number of having deposited in PROM and other information are due to I
2interference in C bus and be mistakenly rewritten is even deleted.Although such situation probability of happening is less, but still should be avoided.
In the embodiment of the present invention, above structure and corresponding function are comprised for realizing the device of write-protect control.As above visible, in the embodiment of the present invention, utilize existing I for realizing the device of write-protect control
2c bus and MCU can realize E
2the write-protect control of PROM, thereby without setting up any signal wire at local host and in can plugging the interface between power supply.More preferably, can also be by whether in place and/or can plug the judgement whether power supply enabled by CPU and improve the reliability of write-protect control to plugging power supply.
And, in the embodiment of the present invention, do not affect reading of sequence number to plugging power supply and other information for realizing the device of write-protect control yet.Specifically, read and can plug the sequence number of power supply and the situation of other information for needs:
CPU receives read command by carrying out telecommunication with distance host from distance host; And the CPU read command that also foundation receives is at I
2in C bus as I
2c main device sends and reads instruction to the plugged power supply that is plugged in local host.Wherein, read the I of instruction
2c bus address is still E
2the address of PROM.
E
2pROM is as I
2c is from device from I
2c bus receives reads instruction, and realizes the read operation to sequence number and other information according to reading instruction, then at I
2in C bus, return to CPU the sequence number and other information that read.
After this, CPU is from I
2c bus receive sequence number and other information also return to distance host by carrying out telecommunication with distance host.
Visible, wish plugging the E in power supply for distance host
2pROM carries out the situation of read operation, still can carry out according to existing mode.
Fig. 4 is for realizing the method flow schematic diagram of write-protect control in the embodiment of the present invention.
Referring to Fig. 4, in the embodiment of the present invention, be included in for realizing the method for write-protect control the following steps that local host side is carried out:
Step 410, the CPU that is arranged at local host receives the write order that carries sequence number and other information from a distance host by telecommunication, then CPU according to write order at I
2in C bus as I
2c main device is carried out following step 411～step 413 with the time delay interval order of being scheduled to.
Step 411, CPU is at I
2in C bus as I
2c main device sends out code to plugging power supply.
Step 412, CPU is at I
2in C bus as I
2c main device sends the write command that carries sequence number and other information to plugging power supply.
Step 413, CPU is at I
2in C bus as I
2c main device sends open command to plugging power supply.
Again referring to Fig. 4, in the embodiment of the present invention, be also included in the following steps of the out code that can plug mains side and send with order, write command, the corresponding execution of open command for realizing the method for write-protect control:
Step 421, is arranged at the MCU that can plug power supply as I
2c is from device from I
2c bus receives described out code, and according to out code by E
2the WP pin of PROM be set to close writing protection function level state (being low level state), make E
2pROM now becomes can write state.
Concrete processing mode in this step can be: MCU is from I
2c bus identify trigger after out code interrupt and MCU in a register be set to represent the state of closing, and it is the state that represents to close that MCU inquires above-mentioned register after interrupting being triggered, and carry out E
2the WP pin of PROM is set to the operation of the low level state of closing writing protection function.Wherein, the original state that above-mentioned register records after power-up initializing is the state that represents unlatching.
Step 422, through a predetermined time delay interval, is arranged at the E that can plug power supply
2pROM is as I
2c is from device from I
2c bus receives and carries the write command of sequence number and other information, and realizes the write operation to sequence number and other information according to write command.
Step 423, then through a predetermined time delay interval, be arranged at the MCU that can plug power supply as I
2c is from device from I
2c bus receive open command, and according to open command by E
2the WP pin of PROM be set to open writing protection function level state (being high level state), make E
2pROM now becomes can not write state under write-protect.
Concrete processing mode in this step can be: MCU is from I
2c bus identifies to trigger after open command interrupts and aforementioned register is set to represent the state of opening, and it is the state that represents to open that MCU inquires above-mentioned register after interrupting being triggered, and carry out E
2the WP pin of PROM is set to the operation of the high level state of opening writing protection function.
So far, in the embodiment of the present invention, a flow process for the method that realizes write-protect control finishes.
In addition, more reliably, carrying out in above-mentioned flow process, the method can further include: MCU detects can plug power supply (whether being normally plugged in local host) whether in place and/or can plug power supply whether enabled (control MCU by CPU by level state and start or stop the enable pin that can plug power work and judge according to existing in interface) by CPU.Thereby:
For only detecting and can plug power supply situation whether in place, MCU can be detecting that can plug power supply ignores out code time not in place, that is, as long as it is in place to plug power supply, even if receive that out code also still keeps E
2the write-protect state of PROM;
For only detecting and can plug the situation whether power supply is enabled, MCU can ignore out code detecting when can plug power supply is not enabled, that is, be not enabled as long as can plug power supply, even if receive that out code also still keeps E
2the write-protect state of PROM;
For detect and can plug the situation that whether power supply is in place and whether be enabled simultaneously, MCU can detect that can to plug power supply in place and/or ignore out code while not being enabled again,, as long as fail to meet simultaneously, can to plug power supply in place and be enabled, even if receive that out code also still keeps E
2the write-protect state of PROM.
As above visible, in the embodiment of the present invention, can utilize existing I for the method that realizes write-protect control
2c bus and MCU can realize E
2the write-protect control of PROM, thereby without setting up any signal wire at local host and in can plugging the interface between power supply.More preferably, can also be by whether in place and/or can plug the judgement whether power supply enabled by CPU and improve the reliability of write-protect control to plugging power supply.
Be more than in the present embodiment for realizing the detailed description of apparatus and method of write-protect control.
All with E in the above description
2pROM, MCU and can plug power supply and sequence number is example, but in actual applications:
E
2pROM is also substitutable for the nonvolatile memory of the other types such as such as Flash, and correspondingly, the level state that the level state of closing writing protection function likely can be become to high level state, unlatching writing protection function also just may become low level state;
MCU is substitutable for such as CPLD etc., and other can realize the processor of identity function;
Write the data of writing that the sequence number that data comprise is also substitutable for the identification code of other types, even can be replaced by other purposes, and other information can be any information that user needs;
And the such scheme in the embodiment of the present invention is also applicable to the plugged device of the other types that need telemanagement.
The above is only preferred embodiment of the present invention, in order to limit the present invention, within the spirit and principles in the present invention not all, any amendment of making, is equal to replacement, improvement etc., within all should being included in the scope of protection of the invention.
Claims (8)
1. for realizing a device for write-protect control, it is characterized in that, comprising:
Be arranged at the CPU of local host, receive and carry the write order of writing data from a distance host by telecommunication, and the described write order of foundation is at I
2in C bus as I
2c main device with the time delay interval order of being scheduled to send out code, the write command, open command that carry write data be to the plugged device that is plugged in described local host;
Be arranged at the described nonvolatile memory that can plug device, as I
2c is from device from I
2c bus receives described write command, and realizes the write operation to write data according to described write command;
Be arranged at the described processor that can plug device, as I
2c is from device from I
2c bus receives described out code and described open command, and the write-protect pin of described nonvolatile memory is set to the level state of closing the level state of writing protection function, according to described open command, the write-protect pin of described nonvolatile memory being set to unlatching writing protection function according to described out code;
And, described processor further detect described can plug device whether in place, also further ignore described out code time not in place at the described device that plugs, or, whether described processor further detects the described device that can plug and is enabled, also further when device is not enabled, ignores described out code described plug, or, described processor further detect described can plug device whether in place and whether be enabled, also further not in place and/or ignore described out code while not being enabled at the described device that plugs.
2. device according to claim 1, is characterized in that, described processor comprises:
Down trigger logic, from I
2c bus identifies to trigger after described out code interrupts and state that a register cuts out described in being set to represent and from I
2c bus identifies to trigger after described open command interrupts and described register is set to represent the state of described unlatching;
Interrupt handling logic; after interruption is triggered, inquire about described register, and in the time of the state of closing described in described register is expression, carry out the operation that the write-protect pin of described nonvolatile memory is set to the operation of the level state of closing writing protection function, execution is set to the write-protect pin of described nonvolatile memory the level state of unlatching writing protection function in the time that described register is the state of the described unlatching of expression.
3. device according to claim 2, is characterized in that, the original state that described register records after power-up initializing is the state that represents described unlatching.
4. device according to claim 1, is characterized in that, write data comprise the described identification code that can plug device, and the described device that plugs is for can plug power supply, and described nonvolatile memory is E
2pROM, described processor is MCU.
5. for realizing a method for write-protect control, it is characterized in that, the method comprises:
The CPU that is arranged at local host is received and carries the write order of writing data from a distance host by telecommunication, and the described write order of foundation is at I
2in C bus as I
2c main device with the time delay interval order of being scheduled to send out code, the write command, open command that carry write data be to the plugged device that is plugged in described local host;
The method also comprises the corresponding following steps of described out code, described write command, described open command that send with order:
Be arranged at the described processor that can plug device as I
2c is from device from I
2c bus receives described out code, and according to described out code, the write-protect pin of the described nonvolatile memory that plugs device is set to the level state of closing writing protection function;
Be arranged at the described described nonvolatile memory that can plug device as I
2c is from device from I
2c bus receives described write command, and realizes the write operation to write data according to described write command;
Described processor is as I
2c is from device from I
2c bus receives described open command, and the write-protect pin of described nonvolatile memory is set to the level state of opening writing protection function according to described open command;
And, the method further comprises: described in described processor detects, can plug device whether in place and ignore described out code time not in place at the described device that plugs, or, described in described processor detects, can plug whether device is enabled and further ignore described out code when plugging device and not being enabled described, or, described in described processor detects, can plug device whether in place and whether be enabled and not in place and/or ignore described out code while not being enabled at the described device that plugs.
6. method according to claim 5, is characterized in that,
According to described out code, the write-protect pin of described nonvolatile memory being set to the level state of closing writing protection function comprises: described processor is from I
2c bus identify trigger after described out code interrupt and described processor in the register state of closing described in being set to represent, and described processor after interrupting being triggered, to inquire described register be the state of closing described in representing, and carry out the operation that the write-protect pin of described nonvolatile memory is set to the level state of closing writing protection function;
According to described open command, the write-protect pin of described nonvolatile memory is set to and opens the level state of writing protection function and comprise: described processor is from I
2c bus identifies to trigger after described open command interrupts and described register is set to represent the state of described unlatching, and described processor after interrupting being triggered, to inquire described register be the state that represents described unlatching, and carry out the operation that the write-protect pin of described nonvolatile memory is set to the level state of opening writing protection function.
7. method according to claim 6, is characterized in that, it is the state that represents described unlatching that the method arranges the original state that described register records after power-up initializing.
8. method according to claim 5, is characterized in that, write data are the described identification code that can plug device, and the described device that plugs is for can plug power supply, and described nonvolatile memory is E
2pROM, described processor is MCU.
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| CN105025328B (en) * | 2015-07-20 | 2018-03-27 | 合一网络技术(北京)有限公司 | Composite machine top box |
| CN106293524B (en) * | 2016-08-02 | 2019-05-24 | 浙江昱能科技有限公司 | A kind of method of data storage |
| CN106971108A (en) * | 2017-03-20 | 2017-07-21 | 郑州云海信息技术有限公司 | A kind of system and method for online updating BIOS ROM write-protects |
| CN108009448A (en) * | 2018-01-02 | 2018-05-08 | 湖南国科微电子股份有限公司 | A kind of solid state hard disc data destruction method, apparatus and system |
| CN109192237B (en) * | 2018-09-14 | 2021-06-04 | 惠科股份有限公司 | Memory write protection circuit and display device |
| CN110047190A (en) * | 2019-05-30 | 2019-07-23 | 广东科徕尼智能科技有限公司 | The data protection unit and means of defence of a kind of use on smart lock |
| CN112416824B (en) * | 2020-12-03 | 2024-02-09 | 上海集成电路研发中心有限公司 | efuse read-write controller, chip, electronic equipment and control method |
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