CN209297188U - A kind of novel LDO Zigzag type current-limiting protection circuit - Google Patents

Abstract

A kind of novel LDO Zigzag type current-limiting protection circuit, including LDO main part and returning type current limiting circuit main body；The LDO main part is by error amplifier, transmission gate TG1, TG2, adjustment pipe, resistance pressure-dividing network, feed-forward capacitance C_FBIt is formed with applications circuit part；The returning type current limiting circuit main body is made of comparator, transmission gate TG3, TG4, phase inverter INV1, INV2, PMOS tube MP1, NMOS tube MN1, MN2, MN3 and resistance R3.Under limited current state, current-limiting circuit detects output voltage, when output electric current reaches preset maximum current value I_MAXWhen, output voltage and output electric current are all gradually reduced, and output electric current is made to be reduced to another current threshold I set_TH, and output voltage is reduced to I_TH*R_load.Due to I_THThan maximum current value I_MAXMuch smaller, then chip does not have apparent heating, and the power consumption of whole system there will not be apparent increase, meets the development trend of low power dissipation electron product.

Description

A kind of novel LDO Zigzag type current-limiting protection circuit

Technical field

The utility model relates to a kind of integrated circuits, especially provide a kind of novel LDO Zigzag type current-limiting protection circuit.

Background technique

LDO (LOW DROPOUT LINER REGULATOR) is known as low pressure difference linear voltage regulator, in order to prevent chip overheating And the performance for influencing chip even burns chip, LDO is usually constructed with current-limiting protection circuit part, but the current-limiting mode of existing LDO Constant current current-limiting mode is generallyd use, i.e. LDO reaches preset maximum current value (I_MAXWhen, current limiting action occurs for LDO, makes defeated Electric current maintains maximum current I out_MAXPoint work, and output voltage is reduced to I_MAX*R_load, however if external loading limits Stream or short circuit duration are too long, then chip heating is just very serious, and will increase the power consumption of whole system, in low-power dissipation system application In be unacceptable.

The constant flow restriction of traditional LDO usually monitors load current, the handle under limited current state with a sampling pipe The load current of LDO is limited in maximum output current I_MAXPoint not only easily causes chip if the limited current state duration is too long Temperature increases, increases the power consumption of system, and has the risk for burning piece.

Utility model content

To solve the above-mentioned problems, the purpose of the utility model is to provide a kind of novel LDO Zigzag type current-limiting protections Circuit.

In order to achieve the above objectives, the technical solution of the utility model is as follows: a kind of novel LDO Zigzag type current-limiting protection electricity Road, including LDO main part and returning type current limiting circuit main body；The LDO main part by error amplifier, transmission gate TG1, TG2, adjustment pipe, resistance pressure-dividing network, feed-forward capacitance C_FBIt is formed with applications circuit part；The resistance pressure-dividing network is by electricity Resistance R1, R2 are composed in series, and the resistance R1 ground connection, resistance R2 connects the drain electrode of adjustment pipe；The applications circuit part is by electricity Hinder R_loadWith capacitor C_OUTIt composes in parallel, is connected across resistance pressure-dividing network both ends；The feed-forward capacitance C_FBIt is connected to the both ends resistance R2； The negative input end of the error amplifier is connected between resistance R1, R2, output end pass through transmission gate TG1 after with transmission gate TG2 mono- The grid of connection adjustment pipe is played, the source electrode of the adjustment pipe connects power supply；The returning type current limiting circuit main body is by comparator, transmission Door TG3, TG4, phase inverter INV1, INV2, PMOS tube MP1, NMOS tube MN1, MN2, MN3 and resistance R3 composition；The NMOS tube The grid of MN3 connects the drain electrode of the adjustment pipe, and drain connecting resistance R3, and source electrode connects the drain electrode of NMOS tube MN1；The NMOS tube MN1, MN2 are controlled by bias voltage, source electrode ground connection；The source electrode of the PMOS tube MP1 connects power supply, the grid of PMOS tube MP1 and The drain electrode of NMOS tube MN2 is connected between the NMOS tube MN3 and resistance R3, and the resistance R3 other end is with PMOS tube MP1's Drain electrode, transmission gate TG2, TG3 link together；The one end the transmission gate TG4 connects the drain electrode of NMOS tube MN2, the other end and biography Defeated door TG3 connects the end in the same direction of the comparator together；The backward end of the comparator is connected to the error amplifier and biography Between defeated door TG1, output end is sequentially connected phase inverter INV1, INV2.

The beneficial effects of the utility model are: current-limiting circuit detects output voltage under limited current state, when output electric current reaches To preset maximum current value I_MAXWhen, output voltage and output electric current are all gradually reduced, and so that output electric current is reduced to another and are set The current threshold I set_TH, and output voltage is reduced to I_TH*R_load.Due to I_THThan maximum current value I_MAXIt is much smaller, then chip Apparent heating is not had, and the power consumption of whole system there will not be apparent increase, meet the hair of low power dissipation electron product Exhibition trend.Meanwhile the utility model has the advantages of simple structure and easy realization, and it is at low cost, there is very strong economy and practicability.

Detailed description of the invention

Fig. 1 is the utility model circuit diagram；Fig. 2 is the utility model Zigzag type current limliting simulation waveform；Fig. 3 is not With the comparison figure of current-limiting mode adjustment pipe power consumption.

Specific embodiment

Specific embodiment of the present utility model is described in detail with reference to the accompanying drawing.

As shown in Figure 1, a kind of novel LDO Zigzag type current-limiting protection circuit, including LDO main part and Zigzag type current limliting Circuit main body；Dotted box portion above circuit diagram is LDO main part, and the LDO main part is by error amplifier ERROR_AMP, transmission gate TG1, TG2, adjustment pipe P_pass, resistance pressure-dividing network, feed-forward capacitance C_FBWith applications circuit portion It is grouped as；LDO main body constitutes a complete feedback loop, in normal operation, is adjusted and is adjusted by feedback loop The grid voltage of homogeneous tube P_pass, the conducting degree of control adjustment pipe P_pass, meets under different loads current conditions, can be defeated Stable output voltage out, feed-forward capacitance C_FBFor increasing the stability of feedback loop.Resistance R_load、C_OUTIt is applications Circuit part, R_loadFor the size of fictitious load electric current, C_OUTHave the function of filtering out noise, stabilize the output voltage.Following Dotted box portion is returning type current limiting circuit main body, the returning type current limiting circuit main body by comparator COMP, transmission gate TG3, TG4, phase inverter INV1, INV2, PMOS tube MP1, NMOS tube MN1, MN2, MN3 and resistance R3 composition.Under limited current state, lead to The conducting degree of MN3 is crossed, to detect output voltage V_OUTSize, MN1, MN2 are by bias voltage V_biasControl, MN1, MN2 electric current Size determine maximum cut-off current I_MAXValue, the size of MN2 electric current determines I_THValue.

Its working principle is introduced in two kinds of situation.

The first situation: load current (I_load) it is smaller not up to cut-off current when, controlled by feedback loop, error is put The output voltage (AMP_OUT) of big device (ERROR_AMP) is higher, and the effect of this voltage and the backward end of comparator (COMP) input End, then the output voltage (COMP_OUT) of comparator is low, and after phase inverter INV1 level-one is reversed, phase inverter INV1's is defeated CTR_b is high level out, and after phase inverter INV1, INV2 two-stage is reversed, the output CTR of phase inverter INV2 is low level. CTR signal function is in the end P of transmission gate TG1, and CTR_b signal function is in the N-terminal of transmission gate TG1, and CTR signal function is in transmission The N-terminal of door TG2, CTR_b act on the end P of transmission gate TG2, and since CTR is low level, CTR_b is high level, then transmission gate TG1 conducting, TG2 cut-off, the grid voltage Vgate for adjusting pipe is the output voltage AMP_OUT of error amplifier, i.e., error is amplified The output voltage (AMP_OUT) of device (ERROR_AMP) acts on the grid of adjustment pipe P_pass, and feedback control loop works at this time, The output voltage of LDO can be stablized, the output voltage of LDO is at this time:

V_OUT=V_REF* (1+R2/R1) --- --- --- --- --- -- (formula 1.1)

For current limliting module, for CTR signal function in the N-terminal of transmission gate TG3, CTR_b acts on the end P of transmission gate TG3, CTR acts on the end P of transmission gate TG4, and CTR_b acts on the N-terminal of transmission gate TG4, and since CTR is low level, CTR_b is high electricity Flat, TG3 cut-off, TG4 conducting, then VR2 acts on the positive input of comparator (COMP), is electricity for comparator (COMP) Pressure VR2 is compared with output (AMP_OUT) voltage of error amplifier, and load current is smaller, feedback loop control error The output voltage of amplifier is higher than the voltage of VR2, and the output of comparator (COMP) is low level.Zigzag type current limliting in the case Circuit does not work.

Second situation: load current I_loadIt continues growing, when reaching cut-off current: when current limliting does not occur, negative feedback loop Road is worked, with load current I_loadIncrease, the output voltage AMP_OUT of error amplifier (ERROR_AMP) gradually drops It is low, as load current I_loadIncrease to the cut-off current I of setting_MAXWhen, the output voltage AMP_OUT of error amplifier, which is lower than, to be compared The output COMP_OUT of device positive input terminal voltage VR2, comparator become high level from original low level, by phase inverter After INV1 level-one is reversed, the output CTR_b of phase inverter INV1 is low level, and comparator output signal (COMP_OUT) is by anti- After phase device INV1, INV2 two-stage is reversed, the output CTR of phase inverter INV2 is high level.CTR signal function is in transmission gate TG1 The end P, CTR_b signal function is in the N-terminal of transmission gate TG1, and for CTR signal function in the N-terminal of transmission gate TG2, CTR_b acts on biography The end P of defeated door TG2, since CTR is low level, CTR_b is high level, then transmission gate TG1 ends, TG2 conducting, then negative-feedback Loop disconnects, and VR1 acts on the grid of adjustment pipe P_pass, and load current is determined by VR1 at this time.Under limited current state originally Feedback loop disconnects, and forms new regenerative feedback loop, this regenerative feedback loop is reduced rapidly output voltage and output electric current.It is right In current limliting module, CTR acts on the N-terminal of transmission gate TG3, and CTR_b acts on the end P of transmission gate TG3, and CTR acts on transmission gate The end P of TG4, CTR_b act on the N-terminal of transmission gate TG4, and since CTR is high level, CTR_b is low level, TG3 conducting, TG4 Cut-off, then VR1 acts on the end in the same direction of comparator (COMP), is the defeated of VR1 and error amplifier for comparator (COMP) (AMP_OUT) is compared out, and since VR1 is higher than the output voltage of error amplifier, comparator output is permanent high.

VR2=VDD-│ V_gsMP1│ --- --- --- --- --- -- (formula 1.2)

VR1=VR2+I1*R3----------------- (formula 1.3)

Under limited current state, due to output voltage V_OUTIt reduces, control MN3 conducting degree reduces, and passes through the total current of MP1 I1 reduces, then │ V_gsMP1│ reduces, and VR2 and VR1 increases known to (formula 1.2) and (formula 1.3), since VR1 is acted on and adjusts pipe P_ The grid of pass further reduces output voltage and output electric current, the output when output voltage, which is reduced to, keeps MN3 completely switched off Electric current is equal to preset I_TH, determined by MN2 branch current.

Input voltage VDD=5V in the design, output voltage V_OUT=3V, I_MAX=300mA, I_TH=100mA, is adopted respectively Carry out emulation comparison with constant current limliting and Zigzag type current limliting: Fig. 2 is this programme Zigzag type current-limited waveform figure, and Fig. 3 is constant current limliting Mode and Zigzag type current-limiting mode lower homogeneous tube power consumption in limited current state and compare figure, as seen from Figure 3 the power dissipation ratio of this programme Constant current-limiting mode reduces nearly 70%, and power consumption reduces bigger in the lower situation of output voltage, therefore returning type current limiting circuit exists It not will lead to chip temperature under limited current state and power consumption increase.

It is to be illustrated to the preferable implementation of the utility model, but the invention is not limited to the reality above Example is applied, those skilled in the art can also make various equivalent variations on the premise of without prejudice to spirit of the invention or replace It changes, these equivalent deformations or replacement are all included in the scope defined by the claims of the present application.

Claims (1)

1. a kind of novel LDO Zigzag type current-limiting protection circuit, it is characterised in that: including LDO main part and Zigzag type current limliting Circuit main body；The LDO main part is by error amplifier, transmission gate TG1, TG2, adjustment pipe, resistance pressure-dividing network, preceding feed Hold C_FBIt is formed with applications circuit part；The resistance pressure-dividing network is composed in series by resistance R1, R2, and the resistance R1 connects Ground, resistance R2 connect the drain electrode of adjustment pipe；The applications circuit part is by resistance R_loadWith capacitor C_OUTIt composes in parallel, bridges At resistance pressure-dividing network both ends；The feed-forward capacitance C_FBIt is connected to the both ends resistance R2；The negative input end of the error amplifier is connected to Between resistance R1, R2, output end connects the grid for adjusting pipe, the adjustment pipe after passing through transmission gate TG1 together with transmission gate TG2 Source electrode connect power supply；The returning type current limiting circuit main body by comparator, transmission gate TG3, TG4, phase inverter INV1, INV2, PMOS tube MP1, NMOS tube MN1, MN2, MN3 and resistance R3 composition；The grid of the NMOS tube MN3 connects the leakage of the adjustment pipe Pole, drain connecting resistance R3, and source electrode connects the drain electrode of NMOS tube MN1；NMOS tube MN1, MN2 is controlled by bias voltage, and source electrode connects Ground；The source electrode of the PMOS tube MP1 connects power supply, and the drain electrode of the grid and NMOS tube MN2 of PMOS tube MP1 is connected to the NMOS tube Between MN3 and resistance R3, the resistance R3 other end links together with the drain electrode of PMOS tube MP1, transmission gate TG2, TG3；Institute The drain electrode of the one end transmission gate TG4 connection NMOS tube MN2 is stated, the other end and transmission gate TG3 connect the in the same direction of the comparator together End；The backward end of the comparator is connected between the error amplifier and transmission gate TG1, and output end is sequentially connected phase inverter INV1、INV2。