CN209150103U - Small outline transistor SOT encapsulating structure - Google Patents
Small outline transistor SOT encapsulating structure Download PDFInfo
- Publication number
- CN209150103U CN209150103U CN201821760795.6U CN201821760795U CN209150103U CN 209150103 U CN209150103 U CN 209150103U CN 201821760795 U CN201821760795 U CN 201821760795U CN 209150103 U CN209150103 U CN 209150103U
- Authority
- CN
- China
- Prior art keywords
- pin
- plastic
- encapsulating structure
- sealed body
- distance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/4811—Connecting to a bonding area of the semiconductor or solid-state body located at the far end of the body with respect to the bonding area outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model relates to a kind of small outline transistor SOT encapsulating structures.The SOT encapsulating structure includes lead frame and plastic packaging in the plastic-sealed body outside lead frame, lead frame includes being located at spaced apart first pin and the second pin on the upside of plastic-sealed body and being located at spaced apart third pin and the 4th pin on the downside of plastic-sealed body, the distance on shown first pin and the opposite both sides of the second pin is greater than 1mm, the distance on third pin and the opposite both sides of the 4th pin is greater than 1mm, Ji Dao is provided in the middle part of lead frame, for being bonded chip.Above-mentioned SOT encapsulating structure the distance between meets the encapsulation requirement of most of product, while increasing pin by four pins of setting, realize it is good climb electric protection, reduce the manufacture difficulty of product to reduce the output of defective products.
Description
Technical field
The utility model relates to field of semiconductor package, more particularly to a kind of small outline transistor SOT encapsulating structure.
Background technique
In the manufacturing process of circuit board, along with the requirement of the control of cost and the small miniaturization of finished product, to integrated circuit
The density requirements of device are higher and higher, while can't reduce the reliability of product, thus small outer transistor npn npn SOT23 occur
Encapsulating structure.SOT23 encapsulating structure includes SOT23-3 and SOT23-5 packing forms.
It is as shown in Figure 1 the schematic diagram of small outline transistor SOT23-3 encapsulating structure, which includes
In the plastic-sealed body 10 outside lead frame, which includes the first pin 11 on the upside of plastic-sealed body for lead frame and plastic packaging
And it is located at spaced second pin 12 and third pin 13 on the downside of plastic-sealed body.The product type of this encapsulating structure production
It is limited.
It is illustrated in figure 2 the schematic diagram of small outline transistor SOT23-5 encapsulating structure, which includes
In the plastic-sealed body 20 outside lead frame, which includes being located at spaced the on the upside of plastic-sealed body for lead frame and plastic packaging
One pin 21 and the second pin 22, and it is located at spaced third pin 23, the 4th pin 24 and the 5th on the downside of plastic-sealed body
Pin 25.This encapsulating structure is particularly easy to high pressure creepage phenomenon occur, to increase the manufacture difficulty and defective products of product
Output.
Utility model content
Based on this, it is necessary in view of the above-mentioned problems, providing a kind of small outline transistor SOT encapsulating structure.
A kind of small outline transistor SOT encapsulating structure, the SOT encapsulating structure include: lead frame and plastic packaging in drawing
Plastic-sealed body outside wire frame, the lead frame include being located at spaced apart first pin and the second pipe on the upside of the plastic-sealed body
Foot and spaced apart third pin and the 4th pin on the downside of the plastic-sealed body, shown first pin and second pipe
The distance on the opposite both sides of foot is greater than 1mm, and the distance on the third pin and the opposite both sides of the 4th pin is greater than 1mm,
It is provided with Ji Dao in the middle part of the lead frame, for being bonded chip.
Above-mentioned SOT encapsulating structure is met the encapsulation requirement of most of product, is increased simultaneously by four pins of setting
The distance between pin, realize it is good climb electric protection, reduce the manufacture difficulty of product to reduce the production of defective products
Out.
First pin and the third pin are corresponding in a longitudinal direction in one of the embodiments, described
Second pin and the 4th pin are corresponding in a longitudinal direction.
The length of the plastic-sealed body is between 2.80mm-3.00mm in one of the embodiments, the width of the plastic-sealed body
Degree is between 1.50mm-1.70mm.
First pin and the opposite both sides of second pin and the plastic-sealed body in one of the embodiments,
Edge at a distance of 0.335mm or the third pin and the 4th pin opposite both sides and the plastic-sealed body edge
At a distance of 0.335mm.
The opposite both sides and described of first pin and second pin in one of the embodiments,
The edge of three-prong and the opposite both sides of the 4th pin with the plastic-sealed body is at a distance of 0.335mm.
The width of the plastic-sealed body is 1.60mm in one of the embodiments, and the length of the plastic-sealed body is
2.92mm。
First pin center and second pin center be at a distance of 1.90mm in one of the embodiments, alternatively,
Third pin center and the 4th pin center are at a distance of 1.90mm.
First pin center and second pin center and the third pipe in one of the embodiments,
Foot center and the 4th pin center are at a distance of 1.90mm.
First pin and the opposite both sides of second pin are at a distance of 1.55mm in one of the embodiments, or
Third pin described in person and the opposite both sides of the 4th pin are at a distance of 1.55mm.It can guarantee to possess in this way and good climb electric guarantor
Shield, combines the machining accuracy of partial circuit plate.
First pin and the opposite both sides of second pin and the third in one of the embodiments,
Pin and the opposite both sides of the 4th pin are at a distance of 1.55mm.It can guarantee to possess so good while climb electric protection
Take into account the machining accuracy of partial circuit plate.
Detailed description of the invention
Fig. 1 is the schematic diagram of small outline transistor SOT23-3 encapsulating structure；
Fig. 2 is the schematic diagram of small outline transistor SOT23-5 encapsulating structure；
Fig. 3 is the schematic diagram of small outline transistor SOT encapsulating structure in one embodiment；
Fig. 4 is the lead frame structure schematic diagram of small outline transistor SOT encapsulating structure in one embodiment；
Fig. 5 is that the load of small outline transistor SOT encapsulating structure in one embodiment is bonded wiring diagram.
Specific embodiment
It is with reference to the accompanying drawings and embodiments, right in order to which the objects, technical solutions and advantages of the application are more clearly understood
The application is further elaborated.It should be appreciated that specific embodiment described herein is only used to explain the application, and
It is not used in restriction the application.
In one embodiment, as shown in Figure 3-Figure 5, a kind of small outline transistor SOT encapsulating structure, the SOT are provided
Encapsulating structure includes lead frame and plastic packaging in the plastic-sealed body 30 outside lead frame, and lead frame includes between being located on the upside of plastic-sealed body
Every the first pin 31 of arrangement and the second pin 32 and it is located at spaced apart third pin 33 and the 4th pipe on the downside of plastic-sealed body
The distance on foot 34, shown first pin 31 and the opposite both sides of the second pin 32 is greater than 1mm, third pin 33 and the 4th pin 34
The distance on opposite both sides is greater than 1mm, base island 35 is provided in the middle part of lead frame, for being bonded chip 36.
In the embodiment of the present application, it can be bonded chip 36 on base island 35, which is bonded with pin, by lead
The outer plastic packaging plastics of frame form plastic-sealed body 30.
In the embodiment of the present application, SOT encapsulating structure by four pins of setting, want by the encapsulation for meeting most of product
It asks.Simultaneously because the distance between the first pin 31 and the second pin 32 are greater than 1mm, and third pin 33 and the 4th pin 34
The distance between be greater than 1mm, can resist at least 1000V climbs electricity, realize it is good climb electric protection, reduce the system of product
Difficulty is made to reduce the output of defective products.
In an alternative embodiment, the distance between the first pin and the second pin and third pin and the 4th
The distance between pin all can be 1mm.
In an alternative embodiment, referring to Fig. 3 and Fig. 2, the first pin 31, second of the application SOT encapsulating structure
The first pipe of pin 32, third pin 33 and the 4th pin 34 in the distribution and SOT23-5 encapsulating structure on plastic-sealed body 30
Foot 21, the second pin 22, the distributional class of third pin 23 and the 5th pin 25 on plastic-sealed body 20 are same.In this way relative to
SOT23-5 encapsulating structure, the SOT encapsulating structure in the application only reduce on the basis of SOT23-5 encapsulating structure
The 4th pin 24 on SOT23-5.Product in this way after the SOT encapsulating structure encapsulation of the application, in shape and originally
Product differentiation after the encapsulation of SOT23-5 encapsulating structure is little.The SOT encapsulating structure of the application is used on the circuit board of client
Product after encapsulation reduces the expense that client redesigns circuit board without changing to board design, save at
This.
It can be understood that in other embodiments, two pins can be removed in SOT23-6 encapsulating structure, to be formed
The application SOT encapsulating structure.
The first pin and third pin are corresponding in a longitudinal direction in one of the embodiments, the second pin and
Four pins are corresponding in a longitudinal direction.
Between 2.80mm-3.00mm, the width of plastic-sealed body is the length of plastic-sealed body in one of the embodiments,
Between 1.50mm-1.70mm.
In one of the embodiments, the first pin and the opposite both sides and plastic-sealed body of the second pin edge apart
The edge on 0.335mm or the opposite both sides and plastic-sealed body of third pin and the 4th pin is at a distance of 0.335mm.
The opposite both sides and third pin and the 4th of first pin and the second pin in one of the embodiments,
The opposite both sides of pin are with the edge of plastic-sealed body at a distance of 0.335mm.
The width of plastic-sealed body is 1.60mm in one of the embodiments, and the length of institute's plastic-sealed body is 2.92mm.
The first pin center and the second pin center are at a distance of 1.90mm in one of the embodiments, alternatively, third pin
Center and the 4th pin center are at a distance of 1.90mm.
First pin center and the second pin center and third pin center and the 4th in one of the embodiments,
Pin center is at a distance of 1.90mm.
The first pin and the opposite both sides of the second pin are at a distance of 1.55mm or third pipe in one of the embodiments,
Foot and the opposite both sides of the 4th pin are at a distance of 1.55mm.Can guarantee to possess in this way it is good climb electric protection, combine part
The machining accuracy of circuit board.
First pin and the opposite both sides and third pin of the second pin and the 4th pipe in one of the embodiments,
The opposite both sides of foot are at a distance of 1.55mm.It can guarantee that possessing good climb takes into account partial circuit plate while electric protection in this way
Machining accuracy.
Each technical characteristic of above embodiments can be combined arbitrarily, for simplicity of description, not to above-described embodiment
In each technical characteristic it is all possible combination be all described, as long as however, the combination of these technical characteristics be not present lance
Shield all should be considered as described in this specification.
Above embodiments only express the several embodiments of the utility model, and the description thereof is more specific and detailed, but simultaneously
The limitation to utility model patent range therefore cannot be interpreted as.It should be pointed out that for the ordinary skill people of this field
For member, without departing from the concept of the premise utility, various modifications and improvements can be made, these belong to this reality
With novel protection scope.Therefore, the scope of protection shall be subject to the appended claims for the utility model patent.
Claims (10)
1. a kind of small outline transistor SOT encapsulating structure, which is characterized in that the SOT encapsulating structure include: lead frame and
For plastic packaging in the plastic-sealed body outside lead frame, the lead frame includes being located at spaced apart first pin on the upside of the plastic-sealed body
With the second pin and spaced apart third pin and the 4th pin, shown first pin and institute on the downside of the plastic-sealed body
The distance for stating the opposite both sides of the second pin is greater than 1mm, the distance of the third pin and the opposite both sides of the 4th pin
Greater than 1mm, it is provided with Ji Dao in the middle part of the lead frame, for being bonded chip.
2. small outline transistor SOT encapsulating structure according to claim 1, which is characterized in that first pin and institute
It is corresponding in a longitudinal direction to state third pin, second pin and the 4th pin are corresponding in a longitudinal direction.
3. small outline transistor SOT encapsulating structure according to claim 1 or 2, which is characterized in that the length of the plastic-sealed body
Degree is between 2.80mm-3.00mm, and the width of the plastic-sealed body is between 1.50mm-1.70mm.
4. small outline transistor SOT encapsulating structure according to claim 3, which is characterized in that first pin and institute
The edge of the opposite both sides of the second pin stated and the plastic-sealed body is at a distance of 0.335mm or the third pin and described the
The opposite both sides of four pins and the edge of the plastic-sealed body are at a distance of 0.335mm.
5. small outline transistor SOT encapsulating structure according to claim 3, which is characterized in that first pin and institute
State the second pin opposite both sides and the third pin and the opposite both sides of the 4th pin with the plastic-sealed body
Edge at a distance of 0.335mm.
6. small outline transistor SOT encapsulating structure according to claim 3, which is characterized in that the width of the plastic-sealed body
Degree is 1.60mm, and the length of the plastic-sealed body is 2.92mm.
7. small outline transistor SOT encapsulating structure according to claim 3, which is characterized in that first pin center
With second pin center at a distance of 1.90mm, alternatively, third pin center and the 4th pin center are apart
1.90mm。
8. small outline transistor SOT encapsulating structure according to claim 3, which is characterized in that first pin center
With second pin center and third pin center and the 4th pin center at a distance of 1.90mm.
9. small outline transistor SOT encapsulating structure according to claim 8, which is characterized in that first pin and institute
The opposite both sides of the second pin are stated at a distance of 1.55mm or the third pin and the 4th pin opposite both sides apart
1.55mm。
10. small outline transistor SOT encapsulating structure according to claim 8, which is characterized in that first pin and institute
The opposite both sides of the second pin and the third pin and the opposite both sides of the 4th pin are stated at a distance of 1.55mm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821760795.6U CN209150103U (en) | 2018-10-29 | 2018-10-29 | Small outline transistor SOT encapsulating structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821760795.6U CN209150103U (en) | 2018-10-29 | 2018-10-29 | Small outline transistor SOT encapsulating structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209150103U true CN209150103U (en) | 2019-07-23 |
Family
ID=67269789
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201821760795.6U Active CN209150103U (en) | 2018-10-29 | 2018-10-29 | Small outline transistor SOT encapsulating structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN209150103U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116338443A (en) * | 2023-05-31 | 2023-06-27 | 上海聚跃检测技术有限公司 | Hot spot positioning method and sample preparation method of SOT chip |
-
2018
- 2018-10-29 CN CN201821760795.6U patent/CN209150103U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116338443A (en) * | 2023-05-31 | 2023-06-27 | 上海聚跃检测技术有限公司 | Hot spot positioning method and sample preparation method of SOT chip |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8368198B2 (en) | Stacked package of semiconductor device | |
| TW201828431A (en) | A Stack Frame for Electrical Connections and the Method to Fabricate Thereof | |
| US20110084374A1 (en) | Semiconductor package with sectioned bonding wire scheme | |
| CN107808868A (en) | Chip-packaging structure and its manufacture method | |
| CN209150103U (en) | Small outline transistor SOT encapsulating structure | |
| CN103579208A (en) | Three-dimensional integrated circuits and fabrication thereof | |
| WO2017071418A1 (en) | Semiconductor device and manufacturing method therefor | |
| JPH0541149U (en) | Semiconductor package | |
| US7479706B2 (en) | Chip package structure | |
| CN208336207U (en) | A kind of biradical island lead frame frame and its SOT33-5L packaging part | |
| CN105023877B (en) | Semiconductor chip, package structure and manufacturing method thereof | |
| CN206293435U (en) | Semiconductor devices and semiconductor package part | |
| CN105489578A (en) | Laminated chip packaging structure | |
| US20110147910A1 (en) | Method for stacking die in thin, small-outline package | |
| CN205984972U (en) | Lead frame structure | |
| KR101239458B1 (en) | Stepped-stacked semiconductor package and method of manufacturing the same | |
| KR20010068513A (en) | Stacked chip package comprising circuit board with windows | |
| US20060065983A1 (en) | Semiconductor package with wire bond arrangement to reduce cross talk for high speed circuits | |
| CN208923090U (en) | Outline Package TSOP encapsulating structure | |
| CN115910974B (en) | High density semiconductor integrated circuit lead frame | |
| US20150061160A1 (en) | Semiconductor device and method of manufacturing the semiconductor device | |
| CN212934607U (en) | Three-pin transistor packaging lead frame structure | |
| TWI473242B (en) | Chip package structure | |
| US7943433B2 (en) | Method of manufacturing semiconductor device | |
| TWM538236U (en) | Common source type packaging structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |