CN209134388U - RF local oscillator signal calibration circuit - Google Patents
RF local oscillator signal calibration circuit Download PDFInfo
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- CN209134388U CN209134388U CN201822231050.7U CN201822231050U CN209134388U CN 209134388 U CN209134388 U CN 209134388U CN 201822231050 U CN201822231050 U CN 201822231050U CN 209134388 U CN209134388 U CN 209134388U
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Abstract
The utility model discloses a kind of RF local oscillator signal calibration circuits, including decimal frequency divider, integer frequency divider, frequency mixer, low-pass filter, ADC converter and fpga chip；The decimal frequency divider is the decimal frequency divider based on Δ ∑ modulation technique；The fpga chip is configured to the initial value of modulation to decimal frequency divider, and the fpga chip is configured to the initial value of modulation to integer frequency divider；The decimal frequency divider connects the input terminal of frequency mixer with the output end of integer frequency divider, the input terminal of the output end connection low-pass filter of the frequency mixer, the input terminal of the output end connection ADC converter of the low-pass filter, the output end of the ADC converter connect fpga chip.The RF local oscillator signal calibration circuit of the utility model reduces the spuious of main signal frequency spectrum both sides by introducing calibrated channel, can be improved the performance of the system using the calibration circuit.
Description
Technical field
The utility model relates to wireless communication technology fields, and in particular to a kind of RF local oscillator signal calibration circuit.
Background technique
Fractional frequency division function in integrated wireless communication tester, in the PLL that use is integrated with Δ Σ decimal frequency divider
When, the spuious problem of integral boundary can be encountered: i.e. when the frequency of generation is close to phase demodulation frequency fpdIntegral multiple and half it is whole
When several times, main signal frequency spectrum both sides have spurious signal generation, and spurious signal is difficult to remove in the loop bandwidth of PLL.
Summary of the invention
The technical problem to be solved by the present invention is to provide a kind of RF local oscillator signal calibration circuits, are calibrated by introducing
Channel reduces the spuious of main signal frequency spectrum both sides, can be improved the performance of the system using the calibration circuit.
In order to solve the above-mentioned technical problem, the utility model provides a kind of RF local oscillator signal calibration circuit, including small
Modulus frequency divider, integer frequency divider, frequency mixer, low-pass filter, ADC converter and fpga chip；The decimal frequency divider is base
In the decimal frequency divider of Δ ∑ modulation technique；The fpga chip is configured to the initial value of modulation to decimal frequency divider, described
Fpga chip is configured to the initial value of modulation to integer frequency divider；The output end of the decimal frequency divider and integer frequency divider connects
Connect the input terminal of frequency mixer, the input terminal of the output end connection low-pass filter of the frequency mixer, the low-pass filter it is defeated
Outlet connects the input terminal of ADC converter, and the output end of the ADC converter connects fpga chip.
It further comprise the output that the fpga chip receives ADC converter in one preferred embodiment of the utility model
Signal, and the initial value for being allocated to decimal frequency divider for its modulation is generated according to the output signal of the ADC converter.
It further comprise that the decimal frequency divider or integer frequency divider are integrated in one preferred embodiment of the utility model
In synthesizer chip, phaselocked loop, phase discriminator, voltage controlled oscillator and frequency dividing are configured with inside the synthesizer chip
Device, the phase discriminator believe the control voltage that the phase difference of input signal and output signal is converted into being used to control voltage controlled oscillator
Number, the output signal of the voltage controlled oscillator feeds back to the phase discriminator after frequency divider frequency dividing.
It further comprise that the fpga chip output frequency division signal is allocated to institute in one preferred embodiment of the utility model
State synthesizer chip, the synthesizer chip carries out fractional frequency division or whole according to the fractional frequency signal that fpga chip exports
Number frequency dividing.
It further comprise the model of the synthesizer chip in one preferred embodiment of the utility model
LMX2592 series IC integrated chip.
It further comprise that the frequency of the phase discriminator is less than or equal in one preferred embodiment of the utility model
100MHz。
The utility model has the beneficial effects that the RF local oscillator signal calibration circuit of the utility model, fpga chip is to decimal
Respectively for the initial value of modulation, decimal frequency divider and integer frequency divider export decimal respectively for frequency divider and integer frequency divider configuration
Frequency signal after frequency dividing and integral frequency divisioil, two groups of frequency signals export two paths of signals after entering frequency mixer mixing, all the way high frequency
Signal is low pass filtering device and filters out, and the low frequency signal of frequency close to decimal frequency divider spurious frequency passes through low-pass filter all the way
It is converted into digital signal by ADC to be received by FPGA chip, the digital signal that fpga chip receives and decimal frequency divider are spuious
Power is related, and FPGA chip is used for its initial value modulated to decimal frequency divider according to the data-signal adjustment output received,
With this closed loop cycle until optimizing the spurious signal for inhibiting decimal frequency divider.The application reduces master by introducing calibrated channel
Signal spectrum both sides it is spuious, can be improved the performance of the system using the calibration circuit.
Detailed description of the invention
Fig. 1 is the structural block diagram of RF local oscillator signal calibration circuit in the preferred embodiment in the utility model；
Fig. 2 is the structural block diagram of phaselocked loop in the preferred embodiment in the utility model.
Specific embodiment
The utility model is described in further detail in the following with reference to the drawings and specific embodiments, so that those skilled in the art
The utility model may be better understood and can be practiced, but illustrated embodiment is not as the restriction to the utility model.
Embodiment
As shown in Figure 1, the present embodiment discloses a kind of RF local oscillator signal calibration circuit, including decimal frequency divider, integer point
Frequency device, frequency mixer, low-pass filter, ADC converter and fpga chip；Above-mentioned decimal frequency divider is based on Δ ∑ modulation technique
Decimal frequency divider；Above-mentioned fpga chip is configured to the initial value of modulation to decimal frequency divider, and above-mentioned fpga chip is to integer point
Frequency device is configured to the initial value of modulation；Above-mentioned decimal frequency divider connects the input of frequency mixer with the output end of integer frequency divider
End, the input terminal of the output end connection low-pass filter of above-mentioned frequency mixer, the output end connection ADC conversion of above-mentioned low-pass filter
The output end of the input terminal of device, above-mentioned ADC converter connects fpga chip.Above-mentioned fpga chip receives the output of ADC converter
Signal, and the initial value for being allocated to decimal frequency divider for its modulation is generated according to the output signal of above-mentioned ADC converter.
Specifically, fpga chip is configured to the initial value respectively modulated, decimal to decimal frequency divider and integer frequency divider
Frequency divider and integer frequency divider export the frequency signal after fractional frequency division and integral frequency divisioil respectively, and two groups of frequency signals enter mixing
Two paths of signals is exported after device mixing, is two frequency signal high-frequency signals after being added all the way, is two frequency signal phases all the way
Low frequency signal after subtracting；For example, integer frequency divider output frequency is the signal of 4G, decimal frequency divider output frequency is 4.001G's
Signal, two paths of signals export the signal that frequency all the way is 8.001G and all the way letter of 0.001G (1M) after frequency mixer is mixed
Number.Here low frequency signal is just the spurious frequency of decimal frequency divider.High-frequency signal is low pass filtering device and filters out all the way, and one
The low frequency signal of road frequency close to decimal frequency divider spurious frequency is converted into digital signal by ADC converter by low-pass filter
It is received by fpga chip, the digital signal that fpga chip receives is related to the spuious power of decimal frequency divider, fpga chip root
Adjust the initial value for being allocated to decimal frequency divider for its modulation one by one according to the data-signal received, with this closed loop cycle until
The spurious signal for inhibiting decimal frequency divider is optimized, record obtains the optimal initial value for inhibiting to configure when spurious signal, then gradually
Other frequency point Configuration Values are completed, calibration is finally completed.
In the preferred embodiment of the application, above-mentioned decimal frequency divider or integer frequency divider are integrated in frequency synthesizer core
On piece, that is, said frequencies chip combiner is provided simultaneously with fractional frequency division and integral frequency divisioil function, uses its fractional frequency division function
Synthesizer chip is used as the decimal frequency divider of the application, is used as this using the synthesizer chip of its integral frequency divisioil function
The integer frequency divider of application.
Further, said frequencies chip combiner is connect with fpga chip, receives the fractional frequency signal of fpga chip output,
And fractional frequency division or integral frequency divisioil are carried out according to the fractional frequency signal of fpga chip output, i.e., synthesizer chip is according to FPGA core
The fractional frequency signal selection of piece output is currently used as decimal frequency divider and is used using still integer frequency divider.Specifically, said frequencies
Phase-locked loop pll, phase discriminator PD, voltage controlled oscillator VCO and frequency divider are configured with inside chip combiner, above-mentioned phase discriminator PD will be defeated
The phase difference for entering signal and output signal is converted into control voltage signal for controlling voltage controlled oscillator VCO, above-mentioned voltage-controlled vibration
The output signal for swinging device VCO feeds back to above-mentioned phase discriminator PD after above-mentioned frequency divider frequency dividing.In view of the sampling of ADC converter
The frequency of frequency and precision and cost, above-mentioned phase discriminator is less than or equal to 100MHz.
In the present embodiment technical solution, it is preferable to use the IC collection of model LMX2592 series for said frequencies chip combiner
At chip, locking time can accomplish 25us, the reference clock of support can achieve 1.4G, and phase demodulation frequency can achieve
400MHz, and configurator is relatively easy.
Current embodiment require that supplementary explanation: the machine is by synthesizer chip, fpga chip, frequency mixer, low pass filtered
The specific hardware configuration composition such as wave device and ADC converter, fractional hardware have the participation of software program in the process of running, assist
The software program of the machine operation is existing reproducible software program, does not constitute the innovative point of the application.
In addition, current embodiment require that supplementary explanation: Δ ∑ modulation technique.
Embodiment described above is only preferred embodiments for fully illustrating the utility model, the utility model
Protection scope it is without being limited thereto.Those skilled in the art made equivalent substitute or change on the basis of the utility model
It changes, both is within the protection scope of the present invention.The protection scope of the utility model is subject to claims.
Claims (6)
1. a kind of RF local oscillator signal calibration circuit, it is characterised in that: including decimal frequency divider, integer frequency divider, frequency mixer, low
Bandpass filter, ADC converter and fpga chip；The fpga chip is configured to the initial value of modulation, institute to decimal frequency divider
State the initial value that fpga chip is configured to modulation to integer frequency divider；The output end of the decimal frequency divider and integer frequency divider
The input terminal of frequency mixer is connected, the output end of the frequency mixer connects the input terminal of low-pass filter, the low-pass filter
Output end connects the input terminal of ADC converter, and the output end of the ADC converter connects fpga chip.
2. RF local oscillator signal calibration circuit as described in claim 1, it is characterised in that: the fpga chip receives ADC and turns
The output signal of parallel operation, and generated according to the output signal of the ADC converter and be allocated to decimal frequency divider for its modulation
Initial value.
3. RF local oscillator signal calibration circuit as described in claim 1, it is characterised in that: the decimal frequency divider or integer point
Frequency device is integrated in synthesizer chip, and phaselocked loop, phase discriminator, voltage controlled oscillation are configured with inside the synthesizer chip
The phase difference of input signal and output signal is converted into being used to control the control of voltage controlled oscillator by device and frequency divider, the phase discriminator
The output signal of voltage signal processed, the voltage controlled oscillator feeds back to the phase discriminator after frequency divider frequency dividing.
4. RF local oscillator signal calibration circuit as claimed in claim 3, it is characterised in that: the fpga chip output frequency division letter
It number is allocated to the synthesizer chip, the synthesizer chip carries out small according to the fractional frequency signal that fpga chip exports
Number frequency dividing or integral frequency divisioil.
5. RF local oscillator signal calibration circuit as claimed in claim 3, it is characterised in that: the type of the synthesizer chip
Number be LMX2592 series IC integrated chip.
6. RF local oscillator signal calibration circuit as claimed in claim 3, it is characterised in that: the frequency of the phase discriminator be less than etc.
In 100MHz.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201822231050.7U CN209134388U (en) | 2018-12-28 | 2018-12-28 | RF local oscillator signal calibration circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201822231050.7U CN209134388U (en) | 2018-12-28 | 2018-12-28 | RF local oscillator signal calibration circuit |
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| Publication Number | Publication Date |
|---|---|
| CN209134388U true CN209134388U (en) | 2019-07-19 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201822231050.7U Active CN209134388U (en) | 2018-12-28 | 2018-12-28 | RF local oscillator signal calibration circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110995258A (en) * | 2019-12-13 | 2020-04-10 | 昆山普尚电子科技有限公司 | Circuit for reducing stray in local oscillator loop in wireless communication comprehensive tester |
-
2018
- 2018-12-28 CN CN201822231050.7U patent/CN209134388U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110995258A (en) * | 2019-12-13 | 2020-04-10 | 昆山普尚电子科技有限公司 | Circuit for reducing stray in local oscillator loop in wireless communication comprehensive tester |
| CN110995258B (en) * | 2019-12-13 | 2021-06-11 | 昆山普尚电子科技有限公司 | Circuit for reducing stray in local oscillator loop in wireless communication comprehensive tester |
| WO2021114333A1 (en) * | 2019-12-13 | 2021-06-17 | 昆山普尚电子科技有限公司 | Circuit for reducing spurs in local oscillator loop in wireless communication comprehensive tester |
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